rx.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677
  1. /*
  2. * Adaptec AAC series RAID controller driver
  3. * (c) Copyright 2001 Red Hat Inc.
  4. *
  5. * based on the old aacraid driver that is..
  6. * Adaptec aacraid device driver for Linux.
  7. *
  8. * Copyright (c) 2000-2010 Adaptec, Inc.
  9. * 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2, or (at your option)
  14. * any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; see the file COPYING. If not, write to
  23. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  24. *
  25. * Module Name:
  26. * rx.c
  27. *
  28. * Abstract: Hardware miniport for Drawbridge specific hardware functions.
  29. *
  30. */
  31. #include <linux/kernel.h>
  32. #include <linux/init.h>
  33. #include <linux/types.h>
  34. #include <linux/pci.h>
  35. #include <linux/spinlock.h>
  36. #include <linux/blkdev.h>
  37. #include <linux/delay.h>
  38. #include <linux/completion.h>
  39. #include <linux/time.h>
  40. #include <linux/interrupt.h>
  41. #include <scsi/scsi_host.h>
  42. #include "aacraid.h"
  43. static irqreturn_t aac_rx_intr_producer(int irq, void *dev_id)
  44. {
  45. struct aac_dev *dev = dev_id;
  46. unsigned long bellbits;
  47. u8 intstat = rx_readb(dev, MUnit.OISR);
  48. /*
  49. * Read mask and invert because drawbridge is reversed.
  50. * This allows us to only service interrupts that have
  51. * been enabled.
  52. * Check to see if this is our interrupt. If it isn't just return
  53. */
  54. if (likely(intstat & ~(dev->OIMR))) {
  55. bellbits = rx_readl(dev, OutboundDoorbellReg);
  56. if (unlikely(bellbits & DoorBellPrintfReady)) {
  57. aac_printf(dev, readl (&dev->IndexRegs->Mailbox[5]));
  58. rx_writel(dev, MUnit.ODR,DoorBellPrintfReady);
  59. rx_writel(dev, InboundDoorbellReg,DoorBellPrintfDone);
  60. }
  61. else if (unlikely(bellbits & DoorBellAdapterNormCmdReady)) {
  62. rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdReady);
  63. aac_command_normal(&dev->queues->queue[HostNormCmdQueue]);
  64. }
  65. else if (likely(bellbits & DoorBellAdapterNormRespReady)) {
  66. rx_writel(dev, MUnit.ODR,DoorBellAdapterNormRespReady);
  67. aac_response_normal(&dev->queues->queue[HostNormRespQueue]);
  68. }
  69. else if (unlikely(bellbits & DoorBellAdapterNormCmdNotFull)) {
  70. rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdNotFull);
  71. }
  72. else if (unlikely(bellbits & DoorBellAdapterNormRespNotFull)) {
  73. rx_writel(dev, MUnit.ODR, DoorBellAdapterNormCmdNotFull);
  74. rx_writel(dev, MUnit.ODR, DoorBellAdapterNormRespNotFull);
  75. }
  76. return IRQ_HANDLED;
  77. }
  78. return IRQ_NONE;
  79. }
  80. static irqreturn_t aac_rx_intr_message(int irq, void *dev_id)
  81. {
  82. int isAif, isFastResponse, isSpecial;
  83. struct aac_dev *dev = dev_id;
  84. u32 Index = rx_readl(dev, MUnit.OutboundQueue);
  85. if (unlikely(Index == 0xFFFFFFFFL))
  86. Index = rx_readl(dev, MUnit.OutboundQueue);
  87. if (likely(Index != 0xFFFFFFFFL)) {
  88. do {
  89. isAif = isFastResponse = isSpecial = 0;
  90. if (Index & 0x00000002L) {
  91. isAif = 1;
  92. if (Index == 0xFFFFFFFEL)
  93. isSpecial = 1;
  94. Index &= ~0x00000002L;
  95. } else {
  96. if (Index & 0x00000001L)
  97. isFastResponse = 1;
  98. Index >>= 2;
  99. }
  100. if (!isSpecial) {
  101. if (unlikely(aac_intr_normal(dev,
  102. Index, isAif,
  103. isFastResponse, NULL))) {
  104. rx_writel(dev,
  105. MUnit.OutboundQueue,
  106. Index);
  107. rx_writel(dev,
  108. MUnit.ODR,
  109. DoorBellAdapterNormRespReady);
  110. }
  111. }
  112. Index = rx_readl(dev, MUnit.OutboundQueue);
  113. } while (Index != 0xFFFFFFFFL);
  114. return IRQ_HANDLED;
  115. }
  116. return IRQ_NONE;
  117. }
  118. /**
  119. * aac_rx_disable_interrupt - Disable interrupts
  120. * @dev: Adapter
  121. */
  122. static void aac_rx_disable_interrupt(struct aac_dev *dev)
  123. {
  124. rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xff);
  125. }
  126. /**
  127. * aac_rx_enable_interrupt_producer - Enable interrupts
  128. * @dev: Adapter
  129. */
  130. static void aac_rx_enable_interrupt_producer(struct aac_dev *dev)
  131. {
  132. rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xfb);
  133. }
  134. /**
  135. * aac_rx_enable_interrupt_message - Enable interrupts
  136. * @dev: Adapter
  137. */
  138. static void aac_rx_enable_interrupt_message(struct aac_dev *dev)
  139. {
  140. rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xf7);
  141. }
  142. /**
  143. * rx_sync_cmd - send a command and wait
  144. * @dev: Adapter
  145. * @command: Command to execute
  146. * @p1: first parameter
  147. * @ret: adapter status
  148. *
  149. * This routine will send a synchronous command to the adapter and wait
  150. * for its completion.
  151. */
  152. static int rx_sync_cmd(struct aac_dev *dev, u32 command,
  153. u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
  154. u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
  155. {
  156. unsigned long start;
  157. int ok;
  158. /*
  159. * Write the command into Mailbox 0
  160. */
  161. writel(command, &dev->IndexRegs->Mailbox[0]);
  162. /*
  163. * Write the parameters into Mailboxes 1 - 6
  164. */
  165. writel(p1, &dev->IndexRegs->Mailbox[1]);
  166. writel(p2, &dev->IndexRegs->Mailbox[2]);
  167. writel(p3, &dev->IndexRegs->Mailbox[3]);
  168. writel(p4, &dev->IndexRegs->Mailbox[4]);
  169. /*
  170. * Clear the synch command doorbell to start on a clean slate.
  171. */
  172. rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
  173. /*
  174. * Disable doorbell interrupts
  175. */
  176. rx_writeb(dev, MUnit.OIMR, dev->OIMR = 0xff);
  177. /*
  178. * Force the completion of the mask register write before issuing
  179. * the interrupt.
  180. */
  181. rx_readb (dev, MUnit.OIMR);
  182. /*
  183. * Signal that there is a new synch command
  184. */
  185. rx_writel(dev, InboundDoorbellReg, INBOUNDDOORBELL_0);
  186. ok = 0;
  187. start = jiffies;
  188. /*
  189. * Wait up to 30 seconds
  190. */
  191. while (time_before(jiffies, start+30*HZ))
  192. {
  193. udelay(5); /* Delay 5 microseconds to let Mon960 get info. */
  194. /*
  195. * Mon960 will set doorbell0 bit when it has completed the command.
  196. */
  197. if (rx_readl(dev, OutboundDoorbellReg) & OUTBOUNDDOORBELL_0) {
  198. /*
  199. * Clear the doorbell.
  200. */
  201. rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
  202. ok = 1;
  203. break;
  204. }
  205. /*
  206. * Yield the processor in case we are slow
  207. */
  208. msleep(1);
  209. }
  210. if (unlikely(ok != 1)) {
  211. /*
  212. * Restore interrupt mask even though we timed out
  213. */
  214. aac_adapter_enable_int(dev);
  215. return -ETIMEDOUT;
  216. }
  217. /*
  218. * Pull the synch status from Mailbox 0.
  219. */
  220. if (status)
  221. *status = readl(&dev->IndexRegs->Mailbox[0]);
  222. if (r1)
  223. *r1 = readl(&dev->IndexRegs->Mailbox[1]);
  224. if (r2)
  225. *r2 = readl(&dev->IndexRegs->Mailbox[2]);
  226. if (r3)
  227. *r3 = readl(&dev->IndexRegs->Mailbox[3]);
  228. if (r4)
  229. *r4 = readl(&dev->IndexRegs->Mailbox[4]);
  230. /*
  231. * Clear the synch command doorbell.
  232. */
  233. rx_writel(dev, OutboundDoorbellReg, OUTBOUNDDOORBELL_0);
  234. /*
  235. * Restore interrupt mask
  236. */
  237. aac_adapter_enable_int(dev);
  238. return 0;
  239. }
  240. /**
  241. * aac_rx_interrupt_adapter - interrupt adapter
  242. * @dev: Adapter
  243. *
  244. * Send an interrupt to the i960 and breakpoint it.
  245. */
  246. static void aac_rx_interrupt_adapter(struct aac_dev *dev)
  247. {
  248. rx_sync_cmd(dev, BREAKPOINT_REQUEST, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
  249. }
  250. /**
  251. * aac_rx_notify_adapter - send an event to the adapter
  252. * @dev: Adapter
  253. * @event: Event to send
  254. *
  255. * Notify the i960 that something it probably cares about has
  256. * happened.
  257. */
  258. static void aac_rx_notify_adapter(struct aac_dev *dev, u32 event)
  259. {
  260. switch (event) {
  261. case AdapNormCmdQue:
  262. rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_1);
  263. break;
  264. case HostNormRespNotFull:
  265. rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_4);
  266. break;
  267. case AdapNormRespQue:
  268. rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_2);
  269. break;
  270. case HostNormCmdNotFull:
  271. rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_3);
  272. break;
  273. case HostShutdown:
  274. break;
  275. case FastIo:
  276. rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_6);
  277. break;
  278. case AdapPrintfDone:
  279. rx_writel(dev, MUnit.IDR,INBOUNDDOORBELL_5);
  280. break;
  281. default:
  282. BUG();
  283. break;
  284. }
  285. }
  286. /**
  287. * aac_rx_start_adapter - activate adapter
  288. * @dev: Adapter
  289. *
  290. * Start up processing on an i960 based AAC adapter
  291. */
  292. static void aac_rx_start_adapter(struct aac_dev *dev)
  293. {
  294. struct aac_init *init;
  295. init = dev->init;
  296. init->HostElapsedSeconds = cpu_to_le32(get_seconds());
  297. // We can only use a 32 bit address here
  298. rx_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, (u32)(ulong)dev->init_pa,
  299. 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
  300. }
  301. /**
  302. * aac_rx_check_health
  303. * @dev: device to check if healthy
  304. *
  305. * Will attempt to determine if the specified adapter is alive and
  306. * capable of handling requests, returning 0 if alive.
  307. */
  308. static int aac_rx_check_health(struct aac_dev *dev)
  309. {
  310. u32 status = rx_readl(dev, MUnit.OMRx[0]);
  311. /*
  312. * Check to see if the board failed any self tests.
  313. */
  314. if (unlikely(status & SELF_TEST_FAILED))
  315. return -1;
  316. /*
  317. * Check to see if the board panic'd.
  318. */
  319. if (unlikely(status & KERNEL_PANIC)) {
  320. char * buffer;
  321. struct POSTSTATUS {
  322. __le32 Post_Command;
  323. __le32 Post_Address;
  324. } * post;
  325. dma_addr_t paddr, baddr;
  326. int ret;
  327. if (likely((status & 0xFF000000L) == 0xBC000000L))
  328. return (status >> 16) & 0xFF;
  329. buffer = pci_alloc_consistent(dev->pdev, 512, &baddr);
  330. ret = -2;
  331. if (unlikely(buffer == NULL))
  332. return ret;
  333. post = pci_alloc_consistent(dev->pdev,
  334. sizeof(struct POSTSTATUS), &paddr);
  335. if (unlikely(post == NULL)) {
  336. pci_free_consistent(dev->pdev, 512, buffer, baddr);
  337. return ret;
  338. }
  339. memset(buffer, 0, 512);
  340. post->Post_Command = cpu_to_le32(COMMAND_POST_RESULTS);
  341. post->Post_Address = cpu_to_le32(baddr);
  342. rx_writel(dev, MUnit.IMRx[0], paddr);
  343. rx_sync_cmd(dev, COMMAND_POST_RESULTS, baddr, 0, 0, 0, 0, 0,
  344. NULL, NULL, NULL, NULL, NULL);
  345. pci_free_consistent(dev->pdev, sizeof(struct POSTSTATUS),
  346. post, paddr);
  347. if (likely((buffer[0] == '0') && ((buffer[1] == 'x') || (buffer[1] == 'X')))) {
  348. ret = (hex_to_bin(buffer[2]) << 4) +
  349. hex_to_bin(buffer[3]);
  350. }
  351. pci_free_consistent(dev->pdev, 512, buffer, baddr);
  352. return ret;
  353. }
  354. /*
  355. * Wait for the adapter to be up and running.
  356. */
  357. if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
  358. return -3;
  359. /*
  360. * Everything is OK
  361. */
  362. return 0;
  363. }
  364. /**
  365. * aac_rx_deliver_producer
  366. * @fib: fib to issue
  367. *
  368. * Will send a fib, returning 0 if successful.
  369. */
  370. int aac_rx_deliver_producer(struct fib * fib)
  371. {
  372. struct aac_dev *dev = fib->dev;
  373. struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
  374. u32 Index;
  375. unsigned long nointr = 0;
  376. aac_queue_get( dev, &Index, AdapNormCmdQueue, fib->hw_fib_va, 1, fib, &nointr);
  377. atomic_inc(&q->numpending);
  378. *(q->headers.producer) = cpu_to_le32(Index + 1);
  379. if (!(nointr & aac_config.irq_mod))
  380. aac_adapter_notify(dev, AdapNormCmdQueue);
  381. return 0;
  382. }
  383. /**
  384. * aac_rx_deliver_message
  385. * @fib: fib to issue
  386. *
  387. * Will send a fib, returning 0 if successful.
  388. */
  389. static int aac_rx_deliver_message(struct fib * fib)
  390. {
  391. struct aac_dev *dev = fib->dev;
  392. struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
  393. u32 Index;
  394. u64 addr;
  395. volatile void __iomem *device;
  396. unsigned long count = 10000000L; /* 50 seconds */
  397. atomic_inc(&q->numpending);
  398. for(;;) {
  399. Index = rx_readl(dev, MUnit.InboundQueue);
  400. if (unlikely(Index == 0xFFFFFFFFL))
  401. Index = rx_readl(dev, MUnit.InboundQueue);
  402. if (likely(Index != 0xFFFFFFFFL))
  403. break;
  404. if (--count == 0) {
  405. atomic_dec(&q->numpending);
  406. return -ETIMEDOUT;
  407. }
  408. udelay(5);
  409. }
  410. device = dev->base + Index;
  411. addr = fib->hw_fib_pa;
  412. writel((u32)(addr & 0xffffffff), device);
  413. device += sizeof(u32);
  414. writel((u32)(addr >> 32), device);
  415. device += sizeof(u32);
  416. writel(le16_to_cpu(fib->hw_fib_va->header.Size), device);
  417. rx_writel(dev, MUnit.InboundQueue, Index);
  418. return 0;
  419. }
  420. /**
  421. * aac_rx_ioremap
  422. * @size: mapping resize request
  423. *
  424. */
  425. static int aac_rx_ioremap(struct aac_dev * dev, u32 size)
  426. {
  427. if (!size) {
  428. iounmap(dev->regs.rx);
  429. return 0;
  430. }
  431. dev->base = dev->regs.rx = ioremap(dev->base_start, size);
  432. if (dev->base == NULL)
  433. return -1;
  434. dev->IndexRegs = &dev->regs.rx->IndexRegs;
  435. return 0;
  436. }
  437. static int aac_rx_restart_adapter(struct aac_dev *dev, int bled)
  438. {
  439. u32 var = 0;
  440. if (!(dev->supplement_adapter_info.SupportedOptions2 &
  441. AAC_OPTION_MU_RESET) || (bled >= 0) || (bled == -2)) {
  442. if (bled)
  443. printk(KERN_ERR "%s%d: adapter kernel panic'd %x.\n",
  444. dev->name, dev->id, bled);
  445. else {
  446. bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS,
  447. 0, 0, 0, 0, 0, 0, &var, NULL, NULL, NULL, NULL);
  448. if (!bled && (var != 0x00000001) && (var != 0x3803000F))
  449. bled = -EINVAL;
  450. }
  451. if (bled && (bled != -ETIMEDOUT))
  452. bled = aac_adapter_sync_cmd(dev, IOP_RESET,
  453. 0, 0, 0, 0, 0, 0, &var, NULL, NULL, NULL, NULL);
  454. if (bled && (bled != -ETIMEDOUT))
  455. return -EINVAL;
  456. }
  457. if (bled && (var == 0x3803000F)) { /* USE_OTHER_METHOD */
  458. rx_writel(dev, MUnit.reserved2, 3);
  459. msleep(5000); /* Delay 5 seconds */
  460. var = 0x00000001;
  461. }
  462. if (bled && (var != 0x00000001))
  463. return -EINVAL;
  464. ssleep(5);
  465. if (rx_readl(dev, MUnit.OMRx[0]) & KERNEL_PANIC)
  466. return -ENODEV;
  467. if (startup_timeout < 300)
  468. startup_timeout = 300;
  469. return 0;
  470. }
  471. /**
  472. * aac_rx_select_comm - Select communications method
  473. * @dev: Adapter
  474. * @comm: communications method
  475. */
  476. int aac_rx_select_comm(struct aac_dev *dev, int comm)
  477. {
  478. switch (comm) {
  479. case AAC_COMM_PRODUCER:
  480. dev->a_ops.adapter_enable_int = aac_rx_enable_interrupt_producer;
  481. dev->a_ops.adapter_intr = aac_rx_intr_producer;
  482. dev->a_ops.adapter_deliver = aac_rx_deliver_producer;
  483. break;
  484. case AAC_COMM_MESSAGE:
  485. dev->a_ops.adapter_enable_int = aac_rx_enable_interrupt_message;
  486. dev->a_ops.adapter_intr = aac_rx_intr_message;
  487. dev->a_ops.adapter_deliver = aac_rx_deliver_message;
  488. break;
  489. default:
  490. return 1;
  491. }
  492. return 0;
  493. }
  494. /**
  495. * aac_rx_init - initialize an i960 based AAC card
  496. * @dev: device to configure
  497. *
  498. * Allocate and set up resources for the i960 based AAC variants. The
  499. * device_interface in the commregion will be allocated and linked
  500. * to the comm region.
  501. */
  502. int _aac_rx_init(struct aac_dev *dev)
  503. {
  504. unsigned long start;
  505. unsigned long status;
  506. int restart = 0;
  507. int instance = dev->id;
  508. const char * name = dev->name;
  509. if (aac_adapter_ioremap(dev, dev->base_size)) {
  510. printk(KERN_WARNING "%s: unable to map adapter.\n", name);
  511. goto error_iounmap;
  512. }
  513. /* Failure to reset here is an option ... */
  514. dev->a_ops.adapter_sync_cmd = rx_sync_cmd;
  515. dev->a_ops.adapter_enable_int = aac_rx_disable_interrupt;
  516. dev->OIMR = status = rx_readb (dev, MUnit.OIMR);
  517. if ((((status & 0x0c) != 0x0c) || aac_reset_devices || reset_devices) &&
  518. !aac_rx_restart_adapter(dev, 0))
  519. /* Make sure the Hardware FIFO is empty */
  520. while ((++restart < 512) &&
  521. (rx_readl(dev, MUnit.OutboundQueue) != 0xFFFFFFFFL));
  522. /*
  523. * Check to see if the board panic'd while booting.
  524. */
  525. status = rx_readl(dev, MUnit.OMRx[0]);
  526. if (status & KERNEL_PANIC) {
  527. if (aac_rx_restart_adapter(dev, aac_rx_check_health(dev)))
  528. goto error_iounmap;
  529. ++restart;
  530. }
  531. /*
  532. * Check to see if the board failed any self tests.
  533. */
  534. status = rx_readl(dev, MUnit.OMRx[0]);
  535. if (status & SELF_TEST_FAILED) {
  536. printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
  537. goto error_iounmap;
  538. }
  539. /*
  540. * Check to see if the monitor panic'd while booting.
  541. */
  542. if (status & MONITOR_PANIC) {
  543. printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
  544. goto error_iounmap;
  545. }
  546. start = jiffies;
  547. /*
  548. * Wait for the adapter to be up and running. Wait up to 3 minutes
  549. */
  550. while (!((status = rx_readl(dev, MUnit.OMRx[0])) & KERNEL_UP_AND_RUNNING))
  551. {
  552. if ((restart &&
  553. (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
  554. time_after(jiffies, start+HZ*startup_timeout)) {
  555. printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
  556. dev->name, instance, status);
  557. goto error_iounmap;
  558. }
  559. if (!restart &&
  560. ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
  561. time_after(jiffies, start + HZ *
  562. ((startup_timeout > 60)
  563. ? (startup_timeout - 60)
  564. : (startup_timeout / 2))))) {
  565. if (likely(!aac_rx_restart_adapter(dev, aac_rx_check_health(dev))))
  566. start = jiffies;
  567. ++restart;
  568. }
  569. msleep(1);
  570. }
  571. if (restart && aac_commit)
  572. aac_commit = 1;
  573. /*
  574. * Fill in the common function dispatch table.
  575. */
  576. dev->a_ops.adapter_interrupt = aac_rx_interrupt_adapter;
  577. dev->a_ops.adapter_disable_int = aac_rx_disable_interrupt;
  578. dev->a_ops.adapter_notify = aac_rx_notify_adapter;
  579. dev->a_ops.adapter_sync_cmd = rx_sync_cmd;
  580. dev->a_ops.adapter_check_health = aac_rx_check_health;
  581. dev->a_ops.adapter_restart = aac_rx_restart_adapter;
  582. /*
  583. * First clear out all interrupts. Then enable the one's that we
  584. * can handle.
  585. */
  586. aac_adapter_comm(dev, AAC_COMM_PRODUCER);
  587. aac_adapter_disable_int(dev);
  588. rx_writel(dev, MUnit.ODR, 0xffffffff);
  589. aac_adapter_enable_int(dev);
  590. if (aac_init_adapter(dev) == NULL)
  591. goto error_iounmap;
  592. aac_adapter_comm(dev, dev->comm_interface);
  593. dev->sync_mode = 0; /* sync. mode not supported */
  594. dev->msi = aac_msi && !pci_enable_msi(dev->pdev);
  595. if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
  596. IRQF_SHARED, "aacraid", dev) < 0) {
  597. if (dev->msi)
  598. pci_disable_msi(dev->pdev);
  599. printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
  600. name, instance);
  601. goto error_iounmap;
  602. }
  603. dev->dbg_base = dev->base_start;
  604. dev->dbg_base_mapped = dev->base;
  605. dev->dbg_size = dev->base_size;
  606. aac_adapter_enable_int(dev);
  607. /*
  608. * Tell the adapter that all is configured, and it can
  609. * start accepting requests
  610. */
  611. aac_rx_start_adapter(dev);
  612. return 0;
  613. error_iounmap:
  614. return -1;
  615. }
  616. int aac_rx_init(struct aac_dev *dev)
  617. {
  618. /*
  619. * Fill in the function dispatch table.
  620. */
  621. dev->a_ops.adapter_ioremap = aac_rx_ioremap;
  622. dev->a_ops.adapter_comm = aac_rx_select_comm;
  623. return _aac_rx_init(dev);
  624. }