qca_spi.c 24 KB

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  1. /*
  2. * Copyright (c) 2011, 2012, Qualcomm Atheros Communications Inc.
  3. * Copyright (c) 2014, I2SE GmbH
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software
  6. * for any purpose with or without fee is hereby granted, provided
  7. * that the above copyright notice and this permission notice appear
  8. * in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL
  13. * THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR
  14. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
  15. * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
  16. * NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. /* This module implements the Qualcomm Atheros SPI protocol for
  20. * kernel-based SPI device; it is essentially an Ethernet-to-SPI
  21. * serial converter;
  22. */
  23. #include <linux/errno.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/if_arp.h>
  26. #include <linux/if_ether.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/jiffies.h>
  30. #include <linux/kernel.h>
  31. #include <linux/kthread.h>
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/of.h>
  36. #include <linux/of_device.h>
  37. #include <linux/of_net.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/spi/spi.h>
  41. #include <linux/types.h>
  42. #include "qca_7k.h"
  43. #include "qca_debug.h"
  44. #include "qca_framing.h"
  45. #include "qca_spi.h"
  46. #define MAX_DMA_BURST_LEN 5000
  47. /* Modules parameters */
  48. #define QCASPI_CLK_SPEED_MIN 1000000
  49. #define QCASPI_CLK_SPEED_MAX 16000000
  50. #define QCASPI_CLK_SPEED 8000000
  51. static int qcaspi_clkspeed;
  52. module_param(qcaspi_clkspeed, int, 0);
  53. MODULE_PARM_DESC(qcaspi_clkspeed, "SPI bus clock speed (Hz). Use 1000000-16000000.");
  54. #define QCASPI_BURST_LEN_MIN 1
  55. #define QCASPI_BURST_LEN_MAX MAX_DMA_BURST_LEN
  56. static int qcaspi_burst_len = MAX_DMA_BURST_LEN;
  57. module_param(qcaspi_burst_len, int, 0);
  58. MODULE_PARM_DESC(qcaspi_burst_len, "Number of data bytes per burst. Use 1-5000.");
  59. #define QCASPI_PLUGGABLE_MIN 0
  60. #define QCASPI_PLUGGABLE_MAX 1
  61. static int qcaspi_pluggable = QCASPI_PLUGGABLE_MIN;
  62. module_param(qcaspi_pluggable, int, 0);
  63. MODULE_PARM_DESC(qcaspi_pluggable, "Pluggable SPI connection (yes/no).");
  64. #define QCASPI_MTU QCAFRM_ETHMAXMTU
  65. #define QCASPI_TX_TIMEOUT (1 * HZ)
  66. #define QCASPI_QCA7K_REBOOT_TIME_MS 1000
  67. static void
  68. start_spi_intr_handling(struct qcaspi *qca, u16 *intr_cause)
  69. {
  70. *intr_cause = 0;
  71. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  72. qcaspi_read_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  73. netdev_dbg(qca->net_dev, "interrupts: 0x%04x\n", *intr_cause);
  74. }
  75. static void
  76. end_spi_intr_handling(struct qcaspi *qca, u16 intr_cause)
  77. {
  78. u16 intr_enable = (SPI_INT_CPU_ON |
  79. SPI_INT_PKT_AVLBL |
  80. SPI_INT_RDBUF_ERR |
  81. SPI_INT_WRBUF_ERR);
  82. qcaspi_write_register(qca, SPI_REG_INTR_CAUSE, intr_cause);
  83. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, intr_enable);
  84. netdev_dbg(qca->net_dev, "acking int: 0x%04x\n", intr_cause);
  85. }
  86. static u32
  87. qcaspi_write_burst(struct qcaspi *qca, u8 *src, u32 len)
  88. {
  89. __be16 cmd;
  90. struct spi_message *msg = &qca->spi_msg2;
  91. struct spi_transfer *transfer = &qca->spi_xfer2[0];
  92. int ret;
  93. cmd = cpu_to_be16(QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  94. transfer->tx_buf = &cmd;
  95. transfer->rx_buf = NULL;
  96. transfer->len = QCASPI_CMD_LEN;
  97. transfer = &qca->spi_xfer2[1];
  98. transfer->tx_buf = src;
  99. transfer->rx_buf = NULL;
  100. transfer->len = len;
  101. ret = spi_sync(qca->spi_dev, msg);
  102. if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) {
  103. qcaspi_spi_error(qca);
  104. return 0;
  105. }
  106. return len;
  107. }
  108. static u32
  109. qcaspi_write_legacy(struct qcaspi *qca, u8 *src, u32 len)
  110. {
  111. struct spi_message *msg = &qca->spi_msg1;
  112. struct spi_transfer *transfer = &qca->spi_xfer1;
  113. int ret;
  114. transfer->tx_buf = src;
  115. transfer->rx_buf = NULL;
  116. transfer->len = len;
  117. ret = spi_sync(qca->spi_dev, msg);
  118. if (ret || (msg->actual_length != len)) {
  119. qcaspi_spi_error(qca);
  120. return 0;
  121. }
  122. return len;
  123. }
  124. static u32
  125. qcaspi_read_burst(struct qcaspi *qca, u8 *dst, u32 len)
  126. {
  127. struct spi_message *msg = &qca->spi_msg2;
  128. __be16 cmd;
  129. struct spi_transfer *transfer = &qca->spi_xfer2[0];
  130. int ret;
  131. cmd = cpu_to_be16(QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  132. transfer->tx_buf = &cmd;
  133. transfer->rx_buf = NULL;
  134. transfer->len = QCASPI_CMD_LEN;
  135. transfer = &qca->spi_xfer2[1];
  136. transfer->tx_buf = NULL;
  137. transfer->rx_buf = dst;
  138. transfer->len = len;
  139. ret = spi_sync(qca->spi_dev, msg);
  140. if (ret || (msg->actual_length != QCASPI_CMD_LEN + len)) {
  141. qcaspi_spi_error(qca);
  142. return 0;
  143. }
  144. return len;
  145. }
  146. static u32
  147. qcaspi_read_legacy(struct qcaspi *qca, u8 *dst, u32 len)
  148. {
  149. struct spi_message *msg = &qca->spi_msg1;
  150. struct spi_transfer *transfer = &qca->spi_xfer1;
  151. int ret;
  152. transfer->tx_buf = NULL;
  153. transfer->rx_buf = dst;
  154. transfer->len = len;
  155. ret = spi_sync(qca->spi_dev, msg);
  156. if (ret || (msg->actual_length != len)) {
  157. qcaspi_spi_error(qca);
  158. return 0;
  159. }
  160. return len;
  161. }
  162. static int
  163. qcaspi_tx_frame(struct qcaspi *qca, struct sk_buff *skb)
  164. {
  165. u32 count;
  166. u32 written;
  167. u32 offset;
  168. u32 len;
  169. len = skb->len;
  170. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, len);
  171. if (qca->legacy_mode)
  172. qcaspi_tx_cmd(qca, QCA7K_SPI_WRITE | QCA7K_SPI_EXTERNAL);
  173. offset = 0;
  174. while (len) {
  175. count = len;
  176. if (count > qca->burst_len)
  177. count = qca->burst_len;
  178. if (qca->legacy_mode) {
  179. written = qcaspi_write_legacy(qca,
  180. skb->data + offset,
  181. count);
  182. } else {
  183. written = qcaspi_write_burst(qca,
  184. skb->data + offset,
  185. count);
  186. }
  187. if (written != count)
  188. return -1;
  189. offset += count;
  190. len -= count;
  191. }
  192. return 0;
  193. }
  194. static int
  195. qcaspi_transmit(struct qcaspi *qca)
  196. {
  197. struct net_device_stats *n_stats = &qca->net_dev->stats;
  198. u16 available = 0;
  199. u32 pkt_len;
  200. u16 new_head;
  201. u16 packets = 0;
  202. if (qca->txr.skb[qca->txr.head] == NULL)
  203. return 0;
  204. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA, &available);
  205. while (qca->txr.skb[qca->txr.head]) {
  206. pkt_len = qca->txr.skb[qca->txr.head]->len + QCASPI_HW_PKT_LEN;
  207. if (available < pkt_len) {
  208. if (packets == 0)
  209. qca->stats.write_buf_miss++;
  210. break;
  211. }
  212. if (qcaspi_tx_frame(qca, qca->txr.skb[qca->txr.head]) == -1) {
  213. qca->stats.write_err++;
  214. return -1;
  215. }
  216. packets++;
  217. n_stats->tx_packets++;
  218. n_stats->tx_bytes += qca->txr.skb[qca->txr.head]->len;
  219. available -= pkt_len;
  220. /* remove the skb from the queue */
  221. /* XXX After inconsistent lock states netif_tx_lock()
  222. * has been replaced by netif_tx_lock_bh() and so on.
  223. */
  224. netif_tx_lock_bh(qca->net_dev);
  225. dev_kfree_skb(qca->txr.skb[qca->txr.head]);
  226. qca->txr.skb[qca->txr.head] = NULL;
  227. qca->txr.size -= pkt_len;
  228. new_head = qca->txr.head + 1;
  229. if (new_head >= qca->txr.count)
  230. new_head = 0;
  231. qca->txr.head = new_head;
  232. if (netif_queue_stopped(qca->net_dev))
  233. netif_wake_queue(qca->net_dev);
  234. netif_tx_unlock_bh(qca->net_dev);
  235. }
  236. return 0;
  237. }
  238. static int
  239. qcaspi_receive(struct qcaspi *qca)
  240. {
  241. struct net_device *net_dev = qca->net_dev;
  242. struct net_device_stats *n_stats = &net_dev->stats;
  243. u16 available = 0;
  244. u32 bytes_read;
  245. u8 *cp;
  246. /* Allocate rx SKB if we don't have one available. */
  247. if (!qca->rx_skb) {
  248. qca->rx_skb = netdev_alloc_skb(net_dev,
  249. net_dev->mtu + VLAN_ETH_HLEN);
  250. if (!qca->rx_skb) {
  251. netdev_dbg(net_dev, "out of RX resources\n");
  252. qca->stats.out_of_mem++;
  253. return -1;
  254. }
  255. }
  256. /* Read the packet size. */
  257. qcaspi_read_register(qca, SPI_REG_RDBUF_BYTE_AVA, &available);
  258. netdev_dbg(net_dev, "qcaspi_receive: SPI_REG_RDBUF_BYTE_AVA: Value: %08x\n",
  259. available);
  260. if (available == 0) {
  261. netdev_dbg(net_dev, "qcaspi_receive called without any data being available!\n");
  262. return -1;
  263. }
  264. qcaspi_write_register(qca, SPI_REG_BFR_SIZE, available);
  265. if (qca->legacy_mode)
  266. qcaspi_tx_cmd(qca, QCA7K_SPI_READ | QCA7K_SPI_EXTERNAL);
  267. while (available) {
  268. u32 count = available;
  269. if (count > qca->burst_len)
  270. count = qca->burst_len;
  271. if (qca->legacy_mode) {
  272. bytes_read = qcaspi_read_legacy(qca, qca->rx_buffer,
  273. count);
  274. } else {
  275. bytes_read = qcaspi_read_burst(qca, qca->rx_buffer,
  276. count);
  277. }
  278. netdev_dbg(net_dev, "available: %d, byte read: %d\n",
  279. available, bytes_read);
  280. if (bytes_read) {
  281. available -= bytes_read;
  282. } else {
  283. qca->stats.read_err++;
  284. return -1;
  285. }
  286. cp = qca->rx_buffer;
  287. while ((bytes_read--) && (qca->rx_skb)) {
  288. s32 retcode;
  289. retcode = qcafrm_fsm_decode(&qca->frm_handle,
  290. qca->rx_skb->data,
  291. skb_tailroom(qca->rx_skb),
  292. *cp);
  293. cp++;
  294. switch (retcode) {
  295. case QCAFRM_GATHER:
  296. case QCAFRM_NOHEAD:
  297. break;
  298. case QCAFRM_NOTAIL:
  299. netdev_dbg(net_dev, "no RX tail\n");
  300. n_stats->rx_errors++;
  301. n_stats->rx_dropped++;
  302. break;
  303. case QCAFRM_INVLEN:
  304. netdev_dbg(net_dev, "invalid RX length\n");
  305. n_stats->rx_errors++;
  306. n_stats->rx_dropped++;
  307. break;
  308. default:
  309. qca->rx_skb->dev = qca->net_dev;
  310. n_stats->rx_packets++;
  311. n_stats->rx_bytes += retcode;
  312. skb_put(qca->rx_skb, retcode);
  313. qca->rx_skb->protocol = eth_type_trans(
  314. qca->rx_skb, qca->rx_skb->dev);
  315. qca->rx_skb->ip_summed = CHECKSUM_UNNECESSARY;
  316. netif_rx_ni(qca->rx_skb);
  317. qca->rx_skb = netdev_alloc_skb(net_dev,
  318. net_dev->mtu + VLAN_ETH_HLEN);
  319. if (!qca->rx_skb) {
  320. netdev_dbg(net_dev, "out of RX resources\n");
  321. n_stats->rx_errors++;
  322. qca->stats.out_of_mem++;
  323. break;
  324. }
  325. }
  326. }
  327. }
  328. return 0;
  329. }
  330. /* Check that tx ring stores only so much bytes
  331. * that fit into the internal QCA buffer.
  332. */
  333. static int
  334. qcaspi_tx_ring_has_space(struct tx_ring *txr)
  335. {
  336. if (txr->skb[txr->tail])
  337. return 0;
  338. return (txr->size + QCAFRM_ETHMAXLEN < QCASPI_HW_BUF_LEN) ? 1 : 0;
  339. }
  340. /* Flush the tx ring. This function is only safe to
  341. * call from the qcaspi_spi_thread.
  342. */
  343. static void
  344. qcaspi_flush_tx_ring(struct qcaspi *qca)
  345. {
  346. int i;
  347. /* XXX After inconsistent lock states netif_tx_lock()
  348. * has been replaced by netif_tx_lock_bh() and so on.
  349. */
  350. netif_tx_lock_bh(qca->net_dev);
  351. for (i = 0; i < TX_RING_MAX_LEN; i++) {
  352. if (qca->txr.skb[i]) {
  353. dev_kfree_skb(qca->txr.skb[i]);
  354. qca->txr.skb[i] = NULL;
  355. qca->net_dev->stats.tx_dropped++;
  356. }
  357. }
  358. qca->txr.tail = 0;
  359. qca->txr.head = 0;
  360. qca->txr.size = 0;
  361. netif_tx_unlock_bh(qca->net_dev);
  362. }
  363. static void
  364. qcaspi_qca7k_sync(struct qcaspi *qca, int event)
  365. {
  366. u16 signature = 0;
  367. u16 spi_config;
  368. u16 wrbuf_space = 0;
  369. static u16 reset_count;
  370. if (event == QCASPI_EVENT_CPUON) {
  371. /* Read signature twice, if not valid
  372. * go back to unknown state.
  373. */
  374. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  375. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  376. if (signature != QCASPI_GOOD_SIGNATURE) {
  377. qca->sync = QCASPI_SYNC_UNKNOWN;
  378. netdev_dbg(qca->net_dev, "sync: got CPU on, but signature was invalid, restart\n");
  379. } else {
  380. /* ensure that the WRBUF is empty */
  381. qcaspi_read_register(qca, SPI_REG_WRBUF_SPC_AVA,
  382. &wrbuf_space);
  383. if (wrbuf_space != QCASPI_HW_BUF_LEN) {
  384. netdev_dbg(qca->net_dev, "sync: got CPU on, but wrbuf not empty. reset!\n");
  385. qca->sync = QCASPI_SYNC_UNKNOWN;
  386. } else {
  387. netdev_dbg(qca->net_dev, "sync: got CPU on, now in sync\n");
  388. qca->sync = QCASPI_SYNC_READY;
  389. return;
  390. }
  391. }
  392. }
  393. switch (qca->sync) {
  394. case QCASPI_SYNC_READY:
  395. /* Read signature, if not valid go to unknown state. */
  396. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  397. if (signature != QCASPI_GOOD_SIGNATURE) {
  398. qca->sync = QCASPI_SYNC_UNKNOWN;
  399. netdev_dbg(qca->net_dev, "sync: bad signature, restart\n");
  400. /* don't reset right away */
  401. return;
  402. }
  403. break;
  404. case QCASPI_SYNC_UNKNOWN:
  405. /* Read signature, if not valid stay in unknown state */
  406. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  407. if (signature != QCASPI_GOOD_SIGNATURE) {
  408. netdev_dbg(qca->net_dev, "sync: could not read signature to reset device, retry.\n");
  409. return;
  410. }
  411. /* TODO: use GPIO to reset QCA7000 in legacy mode*/
  412. netdev_dbg(qca->net_dev, "sync: resetting device.\n");
  413. qcaspi_read_register(qca, SPI_REG_SPI_CONFIG, &spi_config);
  414. spi_config |= QCASPI_SLAVE_RESET_BIT;
  415. qcaspi_write_register(qca, SPI_REG_SPI_CONFIG, spi_config);
  416. qca->sync = QCASPI_SYNC_RESET;
  417. qca->stats.trig_reset++;
  418. reset_count = 0;
  419. break;
  420. case QCASPI_SYNC_RESET:
  421. reset_count++;
  422. netdev_dbg(qca->net_dev, "sync: waiting for CPU on, count %u.\n",
  423. reset_count);
  424. if (reset_count >= QCASPI_RESET_TIMEOUT) {
  425. /* reset did not seem to take place, try again */
  426. qca->sync = QCASPI_SYNC_UNKNOWN;
  427. qca->stats.reset_timeout++;
  428. netdev_dbg(qca->net_dev, "sync: reset timeout, restarting process.\n");
  429. }
  430. break;
  431. }
  432. }
  433. static int
  434. qcaspi_spi_thread(void *data)
  435. {
  436. struct qcaspi *qca = data;
  437. u16 intr_cause = 0;
  438. netdev_info(qca->net_dev, "SPI thread created\n");
  439. while (!kthread_should_stop()) {
  440. set_current_state(TASK_INTERRUPTIBLE);
  441. if ((qca->intr_req == qca->intr_svc) &&
  442. (qca->txr.skb[qca->txr.head] == NULL) &&
  443. (qca->sync == QCASPI_SYNC_READY))
  444. schedule();
  445. set_current_state(TASK_RUNNING);
  446. netdev_dbg(qca->net_dev, "have work to do. int: %d, tx_skb: %p\n",
  447. qca->intr_req - qca->intr_svc,
  448. qca->txr.skb[qca->txr.head]);
  449. qcaspi_qca7k_sync(qca, QCASPI_EVENT_UPDATE);
  450. if (qca->sync != QCASPI_SYNC_READY) {
  451. netdev_dbg(qca->net_dev, "sync: not ready %u, turn off carrier and flush\n",
  452. (unsigned int)qca->sync);
  453. netif_stop_queue(qca->net_dev);
  454. netif_carrier_off(qca->net_dev);
  455. qcaspi_flush_tx_ring(qca);
  456. msleep(QCASPI_QCA7K_REBOOT_TIME_MS);
  457. }
  458. if (qca->intr_svc != qca->intr_req) {
  459. qca->intr_svc = qca->intr_req;
  460. start_spi_intr_handling(qca, &intr_cause);
  461. if (intr_cause & SPI_INT_CPU_ON) {
  462. qcaspi_qca7k_sync(qca, QCASPI_EVENT_CPUON);
  463. /* not synced. */
  464. if (qca->sync != QCASPI_SYNC_READY)
  465. continue;
  466. qca->stats.device_reset++;
  467. netif_wake_queue(qca->net_dev);
  468. netif_carrier_on(qca->net_dev);
  469. }
  470. if (intr_cause & SPI_INT_RDBUF_ERR) {
  471. /* restart sync */
  472. netdev_dbg(qca->net_dev, "===> rdbuf error!\n");
  473. qca->stats.read_buf_err++;
  474. qca->sync = QCASPI_SYNC_UNKNOWN;
  475. continue;
  476. }
  477. if (intr_cause & SPI_INT_WRBUF_ERR) {
  478. /* restart sync */
  479. netdev_dbg(qca->net_dev, "===> wrbuf error!\n");
  480. qca->stats.write_buf_err++;
  481. qca->sync = QCASPI_SYNC_UNKNOWN;
  482. continue;
  483. }
  484. /* can only handle other interrupts
  485. * if sync has occurred
  486. */
  487. if (qca->sync == QCASPI_SYNC_READY) {
  488. if (intr_cause & SPI_INT_PKT_AVLBL)
  489. qcaspi_receive(qca);
  490. }
  491. end_spi_intr_handling(qca, intr_cause);
  492. }
  493. if (qca->sync == QCASPI_SYNC_READY)
  494. qcaspi_transmit(qca);
  495. }
  496. set_current_state(TASK_RUNNING);
  497. netdev_info(qca->net_dev, "SPI thread exit\n");
  498. return 0;
  499. }
  500. static irqreturn_t
  501. qcaspi_intr_handler(int irq, void *data)
  502. {
  503. struct qcaspi *qca = data;
  504. qca->intr_req++;
  505. if (qca->spi_thread &&
  506. qca->spi_thread->state != TASK_RUNNING)
  507. wake_up_process(qca->spi_thread);
  508. return IRQ_HANDLED;
  509. }
  510. int
  511. qcaspi_netdev_open(struct net_device *dev)
  512. {
  513. struct qcaspi *qca = netdev_priv(dev);
  514. int ret = 0;
  515. if (!qca)
  516. return -EINVAL;
  517. qca->intr_req = 1;
  518. qca->intr_svc = 0;
  519. qca->sync = QCASPI_SYNC_UNKNOWN;
  520. qcafrm_fsm_init(&qca->frm_handle);
  521. qca->spi_thread = kthread_run((void *)qcaspi_spi_thread,
  522. qca, "%s", dev->name);
  523. if (IS_ERR(qca->spi_thread)) {
  524. netdev_err(dev, "%s: unable to start kernel thread.\n",
  525. QCASPI_DRV_NAME);
  526. return PTR_ERR(qca->spi_thread);
  527. }
  528. ret = request_irq(qca->spi_dev->irq, qcaspi_intr_handler, 0,
  529. dev->name, qca);
  530. if (ret) {
  531. netdev_err(dev, "%s: unable to get IRQ %d (irqval=%d).\n",
  532. QCASPI_DRV_NAME, qca->spi_dev->irq, ret);
  533. kthread_stop(qca->spi_thread);
  534. return ret;
  535. }
  536. netif_start_queue(qca->net_dev);
  537. return 0;
  538. }
  539. int
  540. qcaspi_netdev_close(struct net_device *dev)
  541. {
  542. struct qcaspi *qca = netdev_priv(dev);
  543. netif_stop_queue(dev);
  544. qcaspi_write_register(qca, SPI_REG_INTR_ENABLE, 0);
  545. free_irq(qca->spi_dev->irq, qca);
  546. kthread_stop(qca->spi_thread);
  547. qca->spi_thread = NULL;
  548. qcaspi_flush_tx_ring(qca);
  549. return 0;
  550. }
  551. static netdev_tx_t
  552. qcaspi_netdev_xmit(struct sk_buff *skb, struct net_device *dev)
  553. {
  554. u32 frame_len;
  555. u8 *ptmp;
  556. struct qcaspi *qca = netdev_priv(dev);
  557. u16 new_tail;
  558. struct sk_buff *tskb;
  559. u8 pad_len = 0;
  560. if (skb->len < QCAFRM_ETHMINLEN)
  561. pad_len = QCAFRM_ETHMINLEN - skb->len;
  562. if (qca->txr.skb[qca->txr.tail]) {
  563. netdev_warn(qca->net_dev, "queue was unexpectedly full!\n");
  564. netif_stop_queue(qca->net_dev);
  565. qca->stats.ring_full++;
  566. return NETDEV_TX_BUSY;
  567. }
  568. if ((skb_headroom(skb) < QCAFRM_HEADER_LEN) ||
  569. (skb_tailroom(skb) < QCAFRM_FOOTER_LEN + pad_len)) {
  570. tskb = skb_copy_expand(skb, QCAFRM_HEADER_LEN,
  571. QCAFRM_FOOTER_LEN + pad_len, GFP_ATOMIC);
  572. if (!tskb) {
  573. netdev_dbg(qca->net_dev, "could not allocate tx_buff\n");
  574. qca->stats.out_of_mem++;
  575. return NETDEV_TX_BUSY;
  576. }
  577. dev_kfree_skb(skb);
  578. skb = tskb;
  579. }
  580. frame_len = skb->len + pad_len;
  581. ptmp = skb_push(skb, QCAFRM_HEADER_LEN);
  582. qcafrm_create_header(ptmp, frame_len);
  583. if (pad_len) {
  584. ptmp = skb_put(skb, pad_len);
  585. memset(ptmp, 0, pad_len);
  586. }
  587. ptmp = skb_put(skb, QCAFRM_FOOTER_LEN);
  588. qcafrm_create_footer(ptmp);
  589. netdev_dbg(qca->net_dev, "Tx-ing packet: Size: 0x%08x\n",
  590. skb->len);
  591. qca->txr.size += skb->len + QCASPI_HW_PKT_LEN;
  592. new_tail = qca->txr.tail + 1;
  593. if (new_tail >= qca->txr.count)
  594. new_tail = 0;
  595. qca->txr.skb[qca->txr.tail] = skb;
  596. qca->txr.tail = new_tail;
  597. if (!qcaspi_tx_ring_has_space(&qca->txr)) {
  598. netif_stop_queue(qca->net_dev);
  599. qca->stats.ring_full++;
  600. }
  601. dev->trans_start = jiffies;
  602. if (qca->spi_thread &&
  603. qca->spi_thread->state != TASK_RUNNING)
  604. wake_up_process(qca->spi_thread);
  605. return NETDEV_TX_OK;
  606. }
  607. static void
  608. qcaspi_netdev_tx_timeout(struct net_device *dev)
  609. {
  610. struct qcaspi *qca = netdev_priv(dev);
  611. netdev_info(qca->net_dev, "Transmit timeout at %ld, latency %ld\n",
  612. jiffies, jiffies - dev->trans_start);
  613. qca->net_dev->stats.tx_errors++;
  614. /* wake the queue if there is room */
  615. if (qcaspi_tx_ring_has_space(&qca->txr))
  616. netif_wake_queue(dev);
  617. }
  618. static int
  619. qcaspi_netdev_init(struct net_device *dev)
  620. {
  621. struct qcaspi *qca = netdev_priv(dev);
  622. dev->mtu = QCASPI_MTU;
  623. dev->type = ARPHRD_ETHER;
  624. qca->clkspeed = qcaspi_clkspeed;
  625. qca->burst_len = qcaspi_burst_len;
  626. qca->spi_thread = NULL;
  627. qca->buffer_size = (dev->mtu + VLAN_ETH_HLEN + QCAFRM_HEADER_LEN +
  628. QCAFRM_FOOTER_LEN + 4) * 4;
  629. memset(&qca->stats, 0, sizeof(struct qcaspi_stats));
  630. qca->rx_buffer = kmalloc(qca->buffer_size, GFP_KERNEL);
  631. if (!qca->rx_buffer)
  632. return -ENOBUFS;
  633. qca->rx_skb = netdev_alloc_skb(dev, qca->net_dev->mtu + VLAN_ETH_HLEN);
  634. if (!qca->rx_skb) {
  635. kfree(qca->rx_buffer);
  636. netdev_info(qca->net_dev, "Failed to allocate RX sk_buff.\n");
  637. return -ENOBUFS;
  638. }
  639. return 0;
  640. }
  641. static void
  642. qcaspi_netdev_uninit(struct net_device *dev)
  643. {
  644. struct qcaspi *qca = netdev_priv(dev);
  645. kfree(qca->rx_buffer);
  646. qca->buffer_size = 0;
  647. if (qca->rx_skb)
  648. dev_kfree_skb(qca->rx_skb);
  649. }
  650. static int
  651. qcaspi_netdev_change_mtu(struct net_device *dev, int new_mtu)
  652. {
  653. if ((new_mtu < QCAFRM_ETHMINMTU) || (new_mtu > QCAFRM_ETHMAXMTU))
  654. return -EINVAL;
  655. dev->mtu = new_mtu;
  656. return 0;
  657. }
  658. static const struct net_device_ops qcaspi_netdev_ops = {
  659. .ndo_init = qcaspi_netdev_init,
  660. .ndo_uninit = qcaspi_netdev_uninit,
  661. .ndo_open = qcaspi_netdev_open,
  662. .ndo_stop = qcaspi_netdev_close,
  663. .ndo_start_xmit = qcaspi_netdev_xmit,
  664. .ndo_change_mtu = qcaspi_netdev_change_mtu,
  665. .ndo_set_mac_address = eth_mac_addr,
  666. .ndo_tx_timeout = qcaspi_netdev_tx_timeout,
  667. .ndo_validate_addr = eth_validate_addr,
  668. };
  669. static void
  670. qcaspi_netdev_setup(struct net_device *dev)
  671. {
  672. struct qcaspi *qca = NULL;
  673. dev->netdev_ops = &qcaspi_netdev_ops;
  674. qcaspi_set_ethtool_ops(dev);
  675. dev->watchdog_timeo = QCASPI_TX_TIMEOUT;
  676. dev->flags = IFF_MULTICAST;
  677. dev->tx_queue_len = 100;
  678. qca = netdev_priv(dev);
  679. memset(qca, 0, sizeof(struct qcaspi));
  680. memset(&qca->spi_xfer1, 0, sizeof(struct spi_transfer));
  681. memset(&qca->spi_xfer2, 0, sizeof(struct spi_transfer) * 2);
  682. spi_message_init(&qca->spi_msg1);
  683. spi_message_add_tail(&qca->spi_xfer1, &qca->spi_msg1);
  684. spi_message_init(&qca->spi_msg2);
  685. spi_message_add_tail(&qca->spi_xfer2[0], &qca->spi_msg2);
  686. spi_message_add_tail(&qca->spi_xfer2[1], &qca->spi_msg2);
  687. memset(&qca->txr, 0, sizeof(qca->txr));
  688. qca->txr.count = TX_RING_MAX_LEN;
  689. }
  690. static const struct of_device_id qca_spi_of_match[] = {
  691. { .compatible = "qca,qca7000" },
  692. { /* sentinel */ }
  693. };
  694. MODULE_DEVICE_TABLE(of, qca_spi_of_match);
  695. static int
  696. qca_spi_probe(struct spi_device *spi)
  697. {
  698. struct qcaspi *qca = NULL;
  699. struct net_device *qcaspi_devs = NULL;
  700. u8 legacy_mode = 0;
  701. u16 signature;
  702. const char *mac;
  703. if (!spi->dev.of_node) {
  704. dev_err(&spi->dev, "Missing device tree\n");
  705. return -EINVAL;
  706. }
  707. legacy_mode = of_property_read_bool(spi->dev.of_node,
  708. "qca,legacy-mode");
  709. if (qcaspi_clkspeed == 0) {
  710. if (spi->max_speed_hz)
  711. qcaspi_clkspeed = spi->max_speed_hz;
  712. else
  713. qcaspi_clkspeed = QCASPI_CLK_SPEED;
  714. }
  715. if ((qcaspi_clkspeed < QCASPI_CLK_SPEED_MIN) ||
  716. (qcaspi_clkspeed > QCASPI_CLK_SPEED_MAX)) {
  717. dev_info(&spi->dev, "Invalid clkspeed: %d\n",
  718. qcaspi_clkspeed);
  719. return -EINVAL;
  720. }
  721. if ((qcaspi_burst_len < QCASPI_BURST_LEN_MIN) ||
  722. (qcaspi_burst_len > QCASPI_BURST_LEN_MAX)) {
  723. dev_info(&spi->dev, "Invalid burst len: %d\n",
  724. qcaspi_burst_len);
  725. return -EINVAL;
  726. }
  727. if ((qcaspi_pluggable < QCASPI_PLUGGABLE_MIN) ||
  728. (qcaspi_pluggable > QCASPI_PLUGGABLE_MAX)) {
  729. dev_info(&spi->dev, "Invalid pluggable: %d\n",
  730. qcaspi_pluggable);
  731. return -EINVAL;
  732. }
  733. dev_info(&spi->dev, "ver=%s, clkspeed=%d, burst_len=%d, pluggable=%d\n",
  734. QCASPI_DRV_VERSION,
  735. qcaspi_clkspeed,
  736. qcaspi_burst_len,
  737. qcaspi_pluggable);
  738. spi->mode = SPI_MODE_3;
  739. spi->max_speed_hz = qcaspi_clkspeed;
  740. if (spi_setup(spi) < 0) {
  741. dev_err(&spi->dev, "Unable to setup SPI device\n");
  742. return -EFAULT;
  743. }
  744. qcaspi_devs = alloc_etherdev(sizeof(struct qcaspi));
  745. if (!qcaspi_devs)
  746. return -ENOMEM;
  747. qcaspi_netdev_setup(qcaspi_devs);
  748. qca = netdev_priv(qcaspi_devs);
  749. if (!qca) {
  750. free_netdev(qcaspi_devs);
  751. dev_err(&spi->dev, "Fail to retrieve private structure\n");
  752. return -ENOMEM;
  753. }
  754. qca->net_dev = qcaspi_devs;
  755. qca->spi_dev = spi;
  756. qca->legacy_mode = legacy_mode;
  757. spi_set_drvdata(spi, qcaspi_devs);
  758. mac = of_get_mac_address(spi->dev.of_node);
  759. if (mac)
  760. ether_addr_copy(qca->net_dev->dev_addr, mac);
  761. if (!is_valid_ether_addr(qca->net_dev->dev_addr)) {
  762. eth_hw_addr_random(qca->net_dev);
  763. dev_info(&spi->dev, "Using random MAC address: %pM\n",
  764. qca->net_dev->dev_addr);
  765. }
  766. netif_carrier_off(qca->net_dev);
  767. if (!qcaspi_pluggable) {
  768. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  769. qcaspi_read_register(qca, SPI_REG_SIGNATURE, &signature);
  770. if (signature != QCASPI_GOOD_SIGNATURE) {
  771. dev_err(&spi->dev, "Invalid signature (0x%04X)\n",
  772. signature);
  773. free_netdev(qcaspi_devs);
  774. return -EFAULT;
  775. }
  776. }
  777. if (register_netdev(qcaspi_devs)) {
  778. dev_info(&spi->dev, "Unable to register net device %s\n",
  779. qcaspi_devs->name);
  780. free_netdev(qcaspi_devs);
  781. return -EFAULT;
  782. }
  783. qcaspi_init_device_debugfs(qca);
  784. return 0;
  785. }
  786. static int
  787. qca_spi_remove(struct spi_device *spi)
  788. {
  789. struct net_device *qcaspi_devs = spi_get_drvdata(spi);
  790. struct qcaspi *qca = netdev_priv(qcaspi_devs);
  791. qcaspi_remove_device_debugfs(qca);
  792. unregister_netdev(qcaspi_devs);
  793. free_netdev(qcaspi_devs);
  794. return 0;
  795. }
  796. static const struct spi_device_id qca_spi_id[] = {
  797. { "qca7000", 0 },
  798. { /* sentinel */ }
  799. };
  800. MODULE_DEVICE_TABLE(spi, qca_spi_id);
  801. static struct spi_driver qca_spi_driver = {
  802. .driver = {
  803. .name = QCASPI_DRV_NAME,
  804. .owner = THIS_MODULE,
  805. .of_match_table = qca_spi_of_match,
  806. },
  807. .id_table = qca_spi_id,
  808. .probe = qca_spi_probe,
  809. .remove = qca_spi_remove,
  810. };
  811. module_spi_driver(qca_spi_driver);
  812. MODULE_DESCRIPTION("Qualcomm Atheros SPI Driver");
  813. MODULE_AUTHOR("Qualcomm Atheros Communications");
  814. MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
  815. MODULE_LICENSE("Dual BSD/GPL");
  816. MODULE_VERSION(QCASPI_DRV_VERSION);