xgene_enet_main.c 32 KB

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  1. /* Applied Micro X-Gene SoC Ethernet Driver
  2. *
  3. * Copyright (c) 2014, Applied Micro Circuits Corporation
  4. * Authors: Iyappan Subramanian <isubramanian@apm.com>
  5. * Ravi Patel <rapatel@apm.com>
  6. * Keyur Chudgar <kchudgar@apm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include "xgene_enet_main.h"
  22. #include "xgene_enet_hw.h"
  23. #include "xgene_enet_sgmac.h"
  24. #include "xgene_enet_xgmac.h"
  25. #define RES_ENET_CSR 0
  26. #define RES_RING_CSR 1
  27. #define RES_RING_CMD 2
  28. static const struct of_device_id xgene_enet_of_match[];
  29. static const struct acpi_device_id xgene_enet_acpi_match[];
  30. static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
  31. {
  32. struct xgene_enet_raw_desc16 *raw_desc;
  33. int i;
  34. for (i = 0; i < buf_pool->slots; i++) {
  35. raw_desc = &buf_pool->raw_desc16[i];
  36. /* Hardware expects descriptor in little endian format */
  37. raw_desc->m0 = cpu_to_le64(i |
  38. SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
  39. SET_VAL(STASH, 3));
  40. }
  41. }
  42. static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
  43. u32 nbuf)
  44. {
  45. struct sk_buff *skb;
  46. struct xgene_enet_raw_desc16 *raw_desc;
  47. struct xgene_enet_pdata *pdata;
  48. struct net_device *ndev;
  49. struct device *dev;
  50. dma_addr_t dma_addr;
  51. u32 tail = buf_pool->tail;
  52. u32 slots = buf_pool->slots - 1;
  53. u16 bufdatalen, len;
  54. int i;
  55. ndev = buf_pool->ndev;
  56. dev = ndev_to_dev(buf_pool->ndev);
  57. pdata = netdev_priv(ndev);
  58. bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
  59. len = XGENE_ENET_MAX_MTU;
  60. for (i = 0; i < nbuf; i++) {
  61. raw_desc = &buf_pool->raw_desc16[tail];
  62. skb = netdev_alloc_skb_ip_align(ndev, len);
  63. if (unlikely(!skb))
  64. return -ENOMEM;
  65. buf_pool->rx_skb[tail] = skb;
  66. dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
  67. if (dma_mapping_error(dev, dma_addr)) {
  68. netdev_err(ndev, "DMA mapping error\n");
  69. dev_kfree_skb_any(skb);
  70. return -EINVAL;
  71. }
  72. raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
  73. SET_VAL(BUFDATALEN, bufdatalen) |
  74. SET_BIT(COHERENT));
  75. tail = (tail + 1) & slots;
  76. }
  77. pdata->ring_ops->wr_cmd(buf_pool, nbuf);
  78. buf_pool->tail = tail;
  79. return 0;
  80. }
  81. static u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
  82. {
  83. struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  84. return ((u16)pdata->rm << 10) | ring->num;
  85. }
  86. static u8 xgene_enet_hdr_len(const void *data)
  87. {
  88. const struct ethhdr *eth = data;
  89. return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
  90. }
  91. static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
  92. {
  93. struct xgene_enet_pdata *pdata = netdev_priv(buf_pool->ndev);
  94. struct xgene_enet_raw_desc16 *raw_desc;
  95. u32 slots = buf_pool->slots - 1;
  96. u32 tail = buf_pool->tail;
  97. u32 userinfo;
  98. int i, len;
  99. len = pdata->ring_ops->len(buf_pool);
  100. for (i = 0; i < len; i++) {
  101. tail = (tail - 1) & slots;
  102. raw_desc = &buf_pool->raw_desc16[tail];
  103. /* Hardware stores descriptor in little endian format */
  104. userinfo = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
  105. dev_kfree_skb_any(buf_pool->rx_skb[userinfo]);
  106. }
  107. pdata->ring_ops->wr_cmd(buf_pool, -len);
  108. buf_pool->tail = tail;
  109. }
  110. static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
  111. {
  112. struct xgene_enet_desc_ring *rx_ring = data;
  113. if (napi_schedule_prep(&rx_ring->napi)) {
  114. disable_irq_nosync(irq);
  115. __napi_schedule(&rx_ring->napi);
  116. }
  117. return IRQ_HANDLED;
  118. }
  119. static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
  120. struct xgene_enet_raw_desc *raw_desc)
  121. {
  122. struct sk_buff *skb;
  123. struct device *dev;
  124. u16 skb_index;
  125. u8 status;
  126. int ret = 0;
  127. skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
  128. skb = cp_ring->cp_skb[skb_index];
  129. dev = ndev_to_dev(cp_ring->ndev);
  130. dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
  131. GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1)),
  132. DMA_TO_DEVICE);
  133. /* Checking for error */
  134. status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
  135. if (unlikely(status > 2)) {
  136. xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev),
  137. status);
  138. ret = -EIO;
  139. }
  140. if (likely(skb)) {
  141. dev_kfree_skb_any(skb);
  142. } else {
  143. netdev_err(cp_ring->ndev, "completion skb is NULL\n");
  144. ret = -EIO;
  145. }
  146. return ret;
  147. }
  148. static u64 xgene_enet_work_msg(struct sk_buff *skb)
  149. {
  150. struct iphdr *iph;
  151. u8 l3hlen, l4hlen = 0;
  152. u8 csum_enable = 0;
  153. u8 proto = 0;
  154. u8 ethhdr;
  155. u64 hopinfo;
  156. if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
  157. unlikely(skb->protocol != htons(ETH_P_8021Q)))
  158. goto out;
  159. if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
  160. goto out;
  161. iph = ip_hdr(skb);
  162. if (unlikely(ip_is_fragment(iph)))
  163. goto out;
  164. if (likely(iph->protocol == IPPROTO_TCP)) {
  165. l4hlen = tcp_hdrlen(skb) >> 2;
  166. csum_enable = 1;
  167. proto = TSO_IPPROTO_TCP;
  168. } else if (iph->protocol == IPPROTO_UDP) {
  169. l4hlen = UDP_HDR_SIZE;
  170. csum_enable = 1;
  171. }
  172. out:
  173. l3hlen = ip_hdrlen(skb) >> 2;
  174. ethhdr = xgene_enet_hdr_len(skb->data);
  175. hopinfo = SET_VAL(TCPHDR, l4hlen) |
  176. SET_VAL(IPHDR, l3hlen) |
  177. SET_VAL(ETHHDR, ethhdr) |
  178. SET_VAL(EC, csum_enable) |
  179. SET_VAL(IS, proto) |
  180. SET_BIT(IC) |
  181. SET_BIT(TYPE_ETH_WORK_MESSAGE);
  182. return hopinfo;
  183. }
  184. static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
  185. struct sk_buff *skb)
  186. {
  187. struct device *dev = ndev_to_dev(tx_ring->ndev);
  188. struct xgene_enet_raw_desc *raw_desc;
  189. dma_addr_t dma_addr;
  190. u16 tail = tx_ring->tail;
  191. u64 hopinfo;
  192. raw_desc = &tx_ring->raw_desc[tail];
  193. memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
  194. dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
  195. if (dma_mapping_error(dev, dma_addr)) {
  196. netdev_err(tx_ring->ndev, "DMA mapping error\n");
  197. return -EINVAL;
  198. }
  199. /* Hardware expects descriptor in little endian format */
  200. raw_desc->m0 = cpu_to_le64(tail);
  201. raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
  202. SET_VAL(BUFDATALEN, skb->len) |
  203. SET_BIT(COHERENT));
  204. hopinfo = xgene_enet_work_msg(skb);
  205. raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
  206. hopinfo);
  207. tx_ring->cp_ring->cp_skb[tail] = skb;
  208. return 0;
  209. }
  210. static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
  211. struct net_device *ndev)
  212. {
  213. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  214. struct xgene_enet_desc_ring *tx_ring = pdata->tx_ring;
  215. struct xgene_enet_desc_ring *cp_ring = tx_ring->cp_ring;
  216. u32 tx_level, cq_level;
  217. tx_level = pdata->ring_ops->len(tx_ring);
  218. cq_level = pdata->ring_ops->len(cp_ring);
  219. if (unlikely(tx_level > pdata->tx_qcnt_hi ||
  220. cq_level > pdata->cp_qcnt_hi)) {
  221. netif_stop_queue(ndev);
  222. return NETDEV_TX_BUSY;
  223. }
  224. if (xgene_enet_setup_tx_desc(tx_ring, skb)) {
  225. dev_kfree_skb_any(skb);
  226. return NETDEV_TX_OK;
  227. }
  228. pdata->ring_ops->wr_cmd(tx_ring, 1);
  229. skb_tx_timestamp(skb);
  230. tx_ring->tail = (tx_ring->tail + 1) & (tx_ring->slots - 1);
  231. pdata->stats.tx_packets++;
  232. pdata->stats.tx_bytes += skb->len;
  233. return NETDEV_TX_OK;
  234. }
  235. static void xgene_enet_skip_csum(struct sk_buff *skb)
  236. {
  237. struct iphdr *iph = ip_hdr(skb);
  238. if (!ip_is_fragment(iph) ||
  239. (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) {
  240. skb->ip_summed = CHECKSUM_UNNECESSARY;
  241. }
  242. }
  243. static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
  244. struct xgene_enet_raw_desc *raw_desc)
  245. {
  246. struct net_device *ndev;
  247. struct xgene_enet_pdata *pdata;
  248. struct device *dev;
  249. struct xgene_enet_desc_ring *buf_pool;
  250. u32 datalen, skb_index;
  251. struct sk_buff *skb;
  252. u8 status;
  253. int ret = 0;
  254. ndev = rx_ring->ndev;
  255. pdata = netdev_priv(ndev);
  256. dev = ndev_to_dev(rx_ring->ndev);
  257. buf_pool = rx_ring->buf_pool;
  258. dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
  259. XGENE_ENET_MAX_MTU, DMA_FROM_DEVICE);
  260. skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
  261. skb = buf_pool->rx_skb[skb_index];
  262. /* checking for error */
  263. status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
  264. if (unlikely(status > 2)) {
  265. dev_kfree_skb_any(skb);
  266. xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev),
  267. status);
  268. pdata->stats.rx_dropped++;
  269. ret = -EIO;
  270. goto out;
  271. }
  272. /* strip off CRC as HW isn't doing this */
  273. datalen = GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1));
  274. datalen -= 4;
  275. prefetch(skb->data - NET_IP_ALIGN);
  276. skb_put(skb, datalen);
  277. skb_checksum_none_assert(skb);
  278. skb->protocol = eth_type_trans(skb, ndev);
  279. if (likely((ndev->features & NETIF_F_IP_CSUM) &&
  280. skb->protocol == htons(ETH_P_IP))) {
  281. xgene_enet_skip_csum(skb);
  282. }
  283. pdata->stats.rx_packets++;
  284. pdata->stats.rx_bytes += datalen;
  285. napi_gro_receive(&rx_ring->napi, skb);
  286. out:
  287. if (--rx_ring->nbufpool == 0) {
  288. ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
  289. rx_ring->nbufpool = NUM_BUFPOOL;
  290. }
  291. return ret;
  292. }
  293. static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
  294. {
  295. return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
  296. }
  297. static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
  298. int budget)
  299. {
  300. struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
  301. struct xgene_enet_raw_desc *raw_desc;
  302. u16 head = ring->head;
  303. u16 slots = ring->slots - 1;
  304. int ret, count = 0;
  305. do {
  306. raw_desc = &ring->raw_desc[head];
  307. if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
  308. break;
  309. /* read fpqnum field after dataaddr field */
  310. dma_rmb();
  311. if (is_rx_desc(raw_desc))
  312. ret = xgene_enet_rx_frame(ring, raw_desc);
  313. else
  314. ret = xgene_enet_tx_completion(ring, raw_desc);
  315. xgene_enet_mark_desc_slot_empty(raw_desc);
  316. head = (head + 1) & slots;
  317. count++;
  318. if (ret)
  319. break;
  320. } while (--budget);
  321. if (likely(count)) {
  322. pdata->ring_ops->wr_cmd(ring, -count);
  323. ring->head = head;
  324. if (netif_queue_stopped(ring->ndev)) {
  325. if (pdata->ring_ops->len(ring) < pdata->cp_qcnt_low)
  326. netif_wake_queue(ring->ndev);
  327. }
  328. }
  329. return count;
  330. }
  331. static int xgene_enet_napi(struct napi_struct *napi, const int budget)
  332. {
  333. struct xgene_enet_desc_ring *ring;
  334. int processed;
  335. ring = container_of(napi, struct xgene_enet_desc_ring, napi);
  336. processed = xgene_enet_process_ring(ring, budget);
  337. if (processed != budget) {
  338. napi_complete(napi);
  339. enable_irq(ring->irq);
  340. }
  341. return processed;
  342. }
  343. static void xgene_enet_timeout(struct net_device *ndev)
  344. {
  345. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  346. pdata->mac_ops->reset(pdata);
  347. }
  348. static int xgene_enet_register_irq(struct net_device *ndev)
  349. {
  350. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  351. struct device *dev = ndev_to_dev(ndev);
  352. struct xgene_enet_desc_ring *ring;
  353. int ret;
  354. ring = pdata->rx_ring;
  355. ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
  356. IRQF_SHARED, ring->irq_name, ring);
  357. if (ret)
  358. netdev_err(ndev, "Failed to request irq %s\n", ring->irq_name);
  359. if (pdata->cq_cnt) {
  360. ring = pdata->tx_ring->cp_ring;
  361. ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
  362. IRQF_SHARED, ring->irq_name, ring);
  363. if (ret) {
  364. netdev_err(ndev, "Failed to request irq %s\n",
  365. ring->irq_name);
  366. }
  367. }
  368. return ret;
  369. }
  370. static void xgene_enet_free_irq(struct net_device *ndev)
  371. {
  372. struct xgene_enet_pdata *pdata;
  373. struct device *dev;
  374. pdata = netdev_priv(ndev);
  375. dev = ndev_to_dev(ndev);
  376. devm_free_irq(dev, pdata->rx_ring->irq, pdata->rx_ring);
  377. if (pdata->cq_cnt) {
  378. devm_free_irq(dev, pdata->tx_ring->cp_ring->irq,
  379. pdata->tx_ring->cp_ring);
  380. }
  381. }
  382. static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
  383. {
  384. struct napi_struct *napi;
  385. napi = &pdata->rx_ring->napi;
  386. napi_enable(napi);
  387. if (pdata->cq_cnt) {
  388. napi = &pdata->tx_ring->cp_ring->napi;
  389. napi_enable(napi);
  390. }
  391. }
  392. static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
  393. {
  394. struct napi_struct *napi;
  395. napi = &pdata->rx_ring->napi;
  396. napi_disable(napi);
  397. if (pdata->cq_cnt) {
  398. napi = &pdata->tx_ring->cp_ring->napi;
  399. napi_disable(napi);
  400. }
  401. }
  402. static int xgene_enet_open(struct net_device *ndev)
  403. {
  404. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  405. struct xgene_mac_ops *mac_ops = pdata->mac_ops;
  406. int ret;
  407. mac_ops->tx_enable(pdata);
  408. mac_ops->rx_enable(pdata);
  409. ret = xgene_enet_register_irq(ndev);
  410. if (ret)
  411. return ret;
  412. xgene_enet_napi_enable(pdata);
  413. if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
  414. phy_start(pdata->phy_dev);
  415. else
  416. schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
  417. netif_carrier_off(ndev);
  418. netif_start_queue(ndev);
  419. return ret;
  420. }
  421. static int xgene_enet_close(struct net_device *ndev)
  422. {
  423. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  424. struct xgene_mac_ops *mac_ops = pdata->mac_ops;
  425. netif_stop_queue(ndev);
  426. if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
  427. phy_stop(pdata->phy_dev);
  428. else
  429. cancel_delayed_work_sync(&pdata->link_work);
  430. xgene_enet_napi_disable(pdata);
  431. xgene_enet_free_irq(ndev);
  432. xgene_enet_process_ring(pdata->rx_ring, -1);
  433. mac_ops->tx_disable(pdata);
  434. mac_ops->rx_disable(pdata);
  435. return 0;
  436. }
  437. static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
  438. {
  439. struct xgene_enet_pdata *pdata;
  440. struct device *dev;
  441. pdata = netdev_priv(ring->ndev);
  442. dev = ndev_to_dev(ring->ndev);
  443. pdata->ring_ops->clear(ring);
  444. dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
  445. }
  446. static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
  447. {
  448. struct xgene_enet_desc_ring *buf_pool;
  449. if (pdata->tx_ring) {
  450. xgene_enet_delete_ring(pdata->tx_ring);
  451. pdata->tx_ring = NULL;
  452. }
  453. if (pdata->rx_ring) {
  454. buf_pool = pdata->rx_ring->buf_pool;
  455. xgene_enet_delete_bufpool(buf_pool);
  456. xgene_enet_delete_ring(buf_pool);
  457. xgene_enet_delete_ring(pdata->rx_ring);
  458. pdata->rx_ring = NULL;
  459. }
  460. }
  461. static int xgene_enet_get_ring_size(struct device *dev,
  462. enum xgene_enet_ring_cfgsize cfgsize)
  463. {
  464. int size = -EINVAL;
  465. switch (cfgsize) {
  466. case RING_CFGSIZE_512B:
  467. size = 0x200;
  468. break;
  469. case RING_CFGSIZE_2KB:
  470. size = 0x800;
  471. break;
  472. case RING_CFGSIZE_16KB:
  473. size = 0x4000;
  474. break;
  475. case RING_CFGSIZE_64KB:
  476. size = 0x10000;
  477. break;
  478. case RING_CFGSIZE_512KB:
  479. size = 0x80000;
  480. break;
  481. default:
  482. dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
  483. break;
  484. }
  485. return size;
  486. }
  487. static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
  488. {
  489. struct xgene_enet_pdata *pdata;
  490. struct device *dev;
  491. if (!ring)
  492. return;
  493. dev = ndev_to_dev(ring->ndev);
  494. pdata = netdev_priv(ring->ndev);
  495. if (ring->desc_addr) {
  496. pdata->ring_ops->clear(ring);
  497. dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
  498. }
  499. devm_kfree(dev, ring);
  500. }
  501. static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
  502. {
  503. struct device *dev = &pdata->pdev->dev;
  504. struct xgene_enet_desc_ring *ring;
  505. ring = pdata->tx_ring;
  506. if (ring) {
  507. if (ring->cp_ring && ring->cp_ring->cp_skb)
  508. devm_kfree(dev, ring->cp_ring->cp_skb);
  509. if (ring->cp_ring && pdata->cq_cnt)
  510. xgene_enet_free_desc_ring(ring->cp_ring);
  511. xgene_enet_free_desc_ring(ring);
  512. }
  513. ring = pdata->rx_ring;
  514. if (ring) {
  515. if (ring->buf_pool) {
  516. if (ring->buf_pool->rx_skb)
  517. devm_kfree(dev, ring->buf_pool->rx_skb);
  518. xgene_enet_free_desc_ring(ring->buf_pool);
  519. }
  520. xgene_enet_free_desc_ring(ring);
  521. }
  522. }
  523. static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
  524. struct xgene_enet_desc_ring *ring)
  525. {
  526. if ((pdata->enet_id == XGENE_ENET2) &&
  527. (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
  528. return true;
  529. }
  530. return false;
  531. }
  532. static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
  533. struct xgene_enet_desc_ring *ring)
  534. {
  535. u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
  536. return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
  537. }
  538. static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
  539. struct net_device *ndev, u32 ring_num,
  540. enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
  541. {
  542. struct xgene_enet_desc_ring *ring;
  543. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  544. struct device *dev = ndev_to_dev(ndev);
  545. int size;
  546. size = xgene_enet_get_ring_size(dev, cfgsize);
  547. if (size < 0)
  548. return NULL;
  549. ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
  550. GFP_KERNEL);
  551. if (!ring)
  552. return NULL;
  553. ring->ndev = ndev;
  554. ring->num = ring_num;
  555. ring->cfgsize = cfgsize;
  556. ring->id = ring_id;
  557. ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma,
  558. GFP_KERNEL);
  559. if (!ring->desc_addr) {
  560. devm_kfree(dev, ring);
  561. return NULL;
  562. }
  563. ring->size = size;
  564. if (is_irq_mbox_required(pdata, ring)) {
  565. ring->irq_mbox_addr = dma_zalloc_coherent(dev, INTR_MBOX_SIZE,
  566. &ring->irq_mbox_dma, GFP_KERNEL);
  567. if (!ring->irq_mbox_addr) {
  568. dma_free_coherent(dev, size, ring->desc_addr,
  569. ring->dma);
  570. devm_kfree(dev, ring);
  571. return NULL;
  572. }
  573. }
  574. ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
  575. ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
  576. ring = pdata->ring_ops->setup(ring);
  577. netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
  578. ring->num, ring->size, ring->id, ring->slots);
  579. return ring;
  580. }
  581. static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
  582. {
  583. return (owner << 6) | (bufnum & GENMASK(5, 0));
  584. }
  585. static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
  586. {
  587. enum xgene_ring_owner owner;
  588. if (p->enet_id == XGENE_ENET1) {
  589. switch (p->phy_mode) {
  590. case PHY_INTERFACE_MODE_SGMII:
  591. owner = RING_OWNER_ETH0;
  592. break;
  593. default:
  594. owner = (!p->port_id) ? RING_OWNER_ETH0 :
  595. RING_OWNER_ETH1;
  596. break;
  597. }
  598. } else {
  599. owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
  600. }
  601. return owner;
  602. }
  603. static int xgene_enet_create_desc_rings(struct net_device *ndev)
  604. {
  605. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  606. struct device *dev = ndev_to_dev(ndev);
  607. struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
  608. struct xgene_enet_desc_ring *buf_pool = NULL;
  609. enum xgene_ring_owner owner;
  610. u8 cpu_bufnum = pdata->cpu_bufnum;
  611. u8 eth_bufnum = pdata->eth_bufnum;
  612. u8 bp_bufnum = pdata->bp_bufnum;
  613. u16 ring_num = pdata->ring_num;
  614. u16 ring_id;
  615. int ret;
  616. /* allocate rx descriptor ring */
  617. owner = xgene_derive_ring_owner(pdata);
  618. ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
  619. rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
  620. RING_CFGSIZE_16KB, ring_id);
  621. if (!rx_ring) {
  622. ret = -ENOMEM;
  623. goto err;
  624. }
  625. /* allocate buffer pool for receiving packets */
  626. owner = xgene_derive_ring_owner(pdata);
  627. ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
  628. buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
  629. RING_CFGSIZE_2KB, ring_id);
  630. if (!buf_pool) {
  631. ret = -ENOMEM;
  632. goto err;
  633. }
  634. rx_ring->nbufpool = NUM_BUFPOOL;
  635. rx_ring->buf_pool = buf_pool;
  636. rx_ring->irq = pdata->rx_irq;
  637. if (!pdata->cq_cnt) {
  638. snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
  639. ndev->name);
  640. } else {
  641. snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx", ndev->name);
  642. }
  643. buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
  644. sizeof(struct sk_buff *), GFP_KERNEL);
  645. if (!buf_pool->rx_skb) {
  646. ret = -ENOMEM;
  647. goto err;
  648. }
  649. buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
  650. rx_ring->buf_pool = buf_pool;
  651. pdata->rx_ring = rx_ring;
  652. /* allocate tx descriptor ring */
  653. owner = xgene_derive_ring_owner(pdata);
  654. ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
  655. tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
  656. RING_CFGSIZE_16KB, ring_id);
  657. if (!tx_ring) {
  658. ret = -ENOMEM;
  659. goto err;
  660. }
  661. pdata->tx_ring = tx_ring;
  662. if (!pdata->cq_cnt) {
  663. cp_ring = pdata->rx_ring;
  664. } else {
  665. /* allocate tx completion descriptor ring */
  666. ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
  667. cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
  668. RING_CFGSIZE_16KB,
  669. ring_id);
  670. if (!cp_ring) {
  671. ret = -ENOMEM;
  672. goto err;
  673. }
  674. cp_ring->irq = pdata->txc_irq;
  675. snprintf(cp_ring->irq_name, IRQ_ID_SIZE, "%s-txc", ndev->name);
  676. }
  677. cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
  678. sizeof(struct sk_buff *), GFP_KERNEL);
  679. if (!cp_ring->cp_skb) {
  680. ret = -ENOMEM;
  681. goto err;
  682. }
  683. pdata->tx_ring->cp_ring = cp_ring;
  684. pdata->tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
  685. pdata->tx_qcnt_hi = pdata->tx_ring->slots / 2;
  686. pdata->cp_qcnt_hi = pdata->rx_ring->slots / 2;
  687. pdata->cp_qcnt_low = pdata->cp_qcnt_hi / 2;
  688. return 0;
  689. err:
  690. xgene_enet_free_desc_rings(pdata);
  691. return ret;
  692. }
  693. static struct rtnl_link_stats64 *xgene_enet_get_stats64(
  694. struct net_device *ndev,
  695. struct rtnl_link_stats64 *storage)
  696. {
  697. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  698. struct rtnl_link_stats64 *stats = &pdata->stats;
  699. stats->rx_errors += stats->rx_length_errors +
  700. stats->rx_crc_errors +
  701. stats->rx_frame_errors +
  702. stats->rx_fifo_errors;
  703. memcpy(storage, &pdata->stats, sizeof(struct rtnl_link_stats64));
  704. return storage;
  705. }
  706. static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
  707. {
  708. struct xgene_enet_pdata *pdata = netdev_priv(ndev);
  709. int ret;
  710. ret = eth_mac_addr(ndev, addr);
  711. if (ret)
  712. return ret;
  713. pdata->mac_ops->set_mac_addr(pdata);
  714. return ret;
  715. }
  716. static const struct net_device_ops xgene_ndev_ops = {
  717. .ndo_open = xgene_enet_open,
  718. .ndo_stop = xgene_enet_close,
  719. .ndo_start_xmit = xgene_enet_start_xmit,
  720. .ndo_tx_timeout = xgene_enet_timeout,
  721. .ndo_get_stats64 = xgene_enet_get_stats64,
  722. .ndo_change_mtu = eth_change_mtu,
  723. .ndo_set_mac_address = xgene_enet_set_mac_address,
  724. };
  725. #ifdef CONFIG_ACPI
  726. static int xgene_get_port_id_acpi(struct device *dev,
  727. struct xgene_enet_pdata *pdata)
  728. {
  729. acpi_status status;
  730. u64 temp;
  731. status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
  732. if (ACPI_FAILURE(status)) {
  733. pdata->port_id = 0;
  734. } else {
  735. pdata->port_id = temp;
  736. }
  737. return 0;
  738. }
  739. #endif
  740. static int xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
  741. {
  742. u32 id = 0;
  743. int ret;
  744. ret = of_property_read_u32(dev->of_node, "port-id", &id);
  745. if (ret) {
  746. pdata->port_id = 0;
  747. ret = 0;
  748. } else {
  749. pdata->port_id = id & BIT(0);
  750. }
  751. return ret;
  752. }
  753. static int xgene_get_mac_address(struct device *dev,
  754. unsigned char *addr)
  755. {
  756. int ret;
  757. ret = device_property_read_u8_array(dev, "local-mac-address", addr, 6);
  758. if (ret)
  759. ret = device_property_read_u8_array(dev, "mac-address",
  760. addr, 6);
  761. if (ret)
  762. return -ENODEV;
  763. return ETH_ALEN;
  764. }
  765. static int xgene_get_phy_mode(struct device *dev)
  766. {
  767. int i, ret;
  768. char *modestr;
  769. ret = device_property_read_string(dev, "phy-connection-type",
  770. (const char **)&modestr);
  771. if (ret)
  772. ret = device_property_read_string(dev, "phy-mode",
  773. (const char **)&modestr);
  774. if (ret)
  775. return -ENODEV;
  776. for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) {
  777. if (!strcasecmp(modestr, phy_modes(i)))
  778. return i;
  779. }
  780. return -ENODEV;
  781. }
  782. static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
  783. {
  784. struct platform_device *pdev;
  785. struct net_device *ndev;
  786. struct device *dev;
  787. struct resource *res;
  788. void __iomem *base_addr;
  789. u32 offset;
  790. int ret = 0;
  791. pdev = pdata->pdev;
  792. dev = &pdev->dev;
  793. ndev = pdata->ndev;
  794. res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
  795. if (!res) {
  796. dev_err(dev, "Resource enet_csr not defined\n");
  797. return -ENODEV;
  798. }
  799. pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
  800. if (!pdata->base_addr) {
  801. dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
  802. return -ENOMEM;
  803. }
  804. res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
  805. if (!res) {
  806. dev_err(dev, "Resource ring_csr not defined\n");
  807. return -ENODEV;
  808. }
  809. pdata->ring_csr_addr = devm_ioremap(dev, res->start,
  810. resource_size(res));
  811. if (!pdata->ring_csr_addr) {
  812. dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
  813. return -ENOMEM;
  814. }
  815. res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
  816. if (!res) {
  817. dev_err(dev, "Resource ring_cmd not defined\n");
  818. return -ENODEV;
  819. }
  820. pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
  821. resource_size(res));
  822. if (!pdata->ring_cmd_addr) {
  823. dev_err(dev, "Unable to retrieve ENET Ring command region\n");
  824. return -ENOMEM;
  825. }
  826. if (dev->of_node)
  827. ret = xgene_get_port_id_dt(dev, pdata);
  828. #ifdef CONFIG_ACPI
  829. else
  830. ret = xgene_get_port_id_acpi(dev, pdata);
  831. #endif
  832. if (ret)
  833. return ret;
  834. if (xgene_get_mac_address(dev, ndev->dev_addr) != ETH_ALEN)
  835. eth_hw_addr_random(ndev);
  836. memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
  837. pdata->phy_mode = xgene_get_phy_mode(dev);
  838. if (pdata->phy_mode < 0) {
  839. dev_err(dev, "Unable to get phy-connection-type\n");
  840. return pdata->phy_mode;
  841. }
  842. if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
  843. pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
  844. pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
  845. dev_err(dev, "Incorrect phy-connection-type specified\n");
  846. return -ENODEV;
  847. }
  848. ret = platform_get_irq(pdev, 0);
  849. if (ret <= 0) {
  850. dev_err(dev, "Unable to get ENET Rx IRQ\n");
  851. ret = ret ? : -ENXIO;
  852. return ret;
  853. }
  854. pdata->rx_irq = ret;
  855. if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII) {
  856. ret = platform_get_irq(pdev, 1);
  857. if (ret <= 0) {
  858. pdata->cq_cnt = 0;
  859. dev_info(dev, "Unable to get Tx completion IRQ,"
  860. "using Rx IRQ instead\n");
  861. } else {
  862. pdata->cq_cnt = XGENE_MAX_TXC_RINGS;
  863. pdata->txc_irq = ret;
  864. }
  865. }
  866. pdata->clk = devm_clk_get(&pdev->dev, NULL);
  867. if (IS_ERR(pdata->clk)) {
  868. /* Firmware may have set up the clock already. */
  869. dev_info(dev, "clocks have been setup already\n");
  870. }
  871. if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
  872. base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
  873. else
  874. base_addr = pdata->base_addr;
  875. pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
  876. pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
  877. pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
  878. if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
  879. pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
  880. pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
  881. offset = (pdata->enet_id == XGENE_ENET1) ?
  882. BLOCK_ETH_MAC_CSR_OFFSET :
  883. X2_BLOCK_ETH_MAC_CSR_OFFSET;
  884. pdata->mcx_mac_csr_addr = base_addr + offset;
  885. } else {
  886. pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
  887. pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
  888. }
  889. pdata->rx_buff_cnt = NUM_PKT_BUF;
  890. return 0;
  891. }
  892. static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
  893. {
  894. struct net_device *ndev = pdata->ndev;
  895. struct xgene_enet_desc_ring *buf_pool;
  896. u16 dst_ring_num;
  897. int ret;
  898. ret = pdata->port_ops->reset(pdata);
  899. if (ret)
  900. return ret;
  901. ret = xgene_enet_create_desc_rings(ndev);
  902. if (ret) {
  903. netdev_err(ndev, "Error in ring configuration\n");
  904. return ret;
  905. }
  906. /* setup buffer pool */
  907. buf_pool = pdata->rx_ring->buf_pool;
  908. xgene_enet_init_bufpool(buf_pool);
  909. ret = xgene_enet_refill_bufpool(buf_pool, pdata->rx_buff_cnt);
  910. if (ret) {
  911. xgene_enet_delete_desc_rings(pdata);
  912. return ret;
  913. }
  914. dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring);
  915. pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id);
  916. pdata->mac_ops->init(pdata);
  917. return ret;
  918. }
  919. static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
  920. {
  921. switch (pdata->phy_mode) {
  922. case PHY_INTERFACE_MODE_RGMII:
  923. pdata->mac_ops = &xgene_gmac_ops;
  924. pdata->port_ops = &xgene_gport_ops;
  925. pdata->rm = RM3;
  926. break;
  927. case PHY_INTERFACE_MODE_SGMII:
  928. pdata->mac_ops = &xgene_sgmac_ops;
  929. pdata->port_ops = &xgene_sgport_ops;
  930. pdata->rm = RM1;
  931. break;
  932. default:
  933. pdata->mac_ops = &xgene_xgmac_ops;
  934. pdata->port_ops = &xgene_xgport_ops;
  935. pdata->rm = RM0;
  936. break;
  937. }
  938. if (pdata->enet_id == XGENE_ENET1) {
  939. switch (pdata->port_id) {
  940. case 0:
  941. pdata->cpu_bufnum = START_CPU_BUFNUM_0;
  942. pdata->eth_bufnum = START_ETH_BUFNUM_0;
  943. pdata->bp_bufnum = START_BP_BUFNUM_0;
  944. pdata->ring_num = START_RING_NUM_0;
  945. break;
  946. case 1:
  947. pdata->cpu_bufnum = START_CPU_BUFNUM_1;
  948. pdata->eth_bufnum = START_ETH_BUFNUM_1;
  949. pdata->bp_bufnum = START_BP_BUFNUM_1;
  950. pdata->ring_num = START_RING_NUM_1;
  951. break;
  952. default:
  953. break;
  954. }
  955. pdata->ring_ops = &xgene_ring1_ops;
  956. } else {
  957. switch (pdata->port_id) {
  958. case 0:
  959. pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
  960. pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
  961. pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
  962. pdata->ring_num = X2_START_RING_NUM_0;
  963. break;
  964. case 1:
  965. pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
  966. pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
  967. pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
  968. pdata->ring_num = X2_START_RING_NUM_1;
  969. break;
  970. default:
  971. break;
  972. }
  973. pdata->rm = RM0;
  974. pdata->ring_ops = &xgene_ring2_ops;
  975. }
  976. }
  977. static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
  978. {
  979. struct napi_struct *napi;
  980. napi = &pdata->rx_ring->napi;
  981. netif_napi_add(pdata->ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT);
  982. if (pdata->cq_cnt) {
  983. napi = &pdata->tx_ring->cp_ring->napi;
  984. netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
  985. NAPI_POLL_WEIGHT);
  986. }
  987. }
  988. static void xgene_enet_napi_del(struct xgene_enet_pdata *pdata)
  989. {
  990. struct napi_struct *napi;
  991. napi = &pdata->rx_ring->napi;
  992. netif_napi_del(napi);
  993. if (pdata->cq_cnt) {
  994. napi = &pdata->tx_ring->cp_ring->napi;
  995. netif_napi_del(napi);
  996. }
  997. }
  998. static int xgene_enet_probe(struct platform_device *pdev)
  999. {
  1000. struct net_device *ndev;
  1001. struct xgene_enet_pdata *pdata;
  1002. struct device *dev = &pdev->dev;
  1003. struct xgene_mac_ops *mac_ops;
  1004. const struct of_device_id *of_id;
  1005. int ret;
  1006. ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata));
  1007. if (!ndev)
  1008. return -ENOMEM;
  1009. pdata = netdev_priv(ndev);
  1010. pdata->pdev = pdev;
  1011. pdata->ndev = ndev;
  1012. SET_NETDEV_DEV(ndev, dev);
  1013. platform_set_drvdata(pdev, pdata);
  1014. ndev->netdev_ops = &xgene_ndev_ops;
  1015. xgene_enet_set_ethtool_ops(ndev);
  1016. ndev->features |= NETIF_F_IP_CSUM |
  1017. NETIF_F_GSO |
  1018. NETIF_F_GRO;
  1019. of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
  1020. if (of_id) {
  1021. pdata->enet_id = (enum xgene_enet_id)of_id->data;
  1022. }
  1023. #ifdef CONFIG_ACPI
  1024. else {
  1025. const struct acpi_device_id *acpi_id;
  1026. acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev);
  1027. if (acpi_id)
  1028. pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data;
  1029. }
  1030. #endif
  1031. if (!pdata->enet_id) {
  1032. free_netdev(ndev);
  1033. return -ENODEV;
  1034. }
  1035. ret = xgene_enet_get_resources(pdata);
  1036. if (ret)
  1037. goto err;
  1038. xgene_enet_setup_ops(pdata);
  1039. ret = register_netdev(ndev);
  1040. if (ret) {
  1041. netdev_err(ndev, "Failed to register netdev\n");
  1042. goto err;
  1043. }
  1044. ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
  1045. if (ret) {
  1046. netdev_err(ndev, "No usable DMA configuration\n");
  1047. goto err;
  1048. }
  1049. ret = xgene_enet_init_hw(pdata);
  1050. if (ret)
  1051. goto err;
  1052. xgene_enet_napi_add(pdata);
  1053. mac_ops = pdata->mac_ops;
  1054. if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
  1055. ret = xgene_enet_mdio_config(pdata);
  1056. else
  1057. INIT_DELAYED_WORK(&pdata->link_work, mac_ops->link_state);
  1058. return ret;
  1059. err:
  1060. unregister_netdev(ndev);
  1061. free_netdev(ndev);
  1062. return ret;
  1063. }
  1064. static int xgene_enet_remove(struct platform_device *pdev)
  1065. {
  1066. struct xgene_enet_pdata *pdata;
  1067. struct xgene_mac_ops *mac_ops;
  1068. struct net_device *ndev;
  1069. pdata = platform_get_drvdata(pdev);
  1070. mac_ops = pdata->mac_ops;
  1071. ndev = pdata->ndev;
  1072. mac_ops->rx_disable(pdata);
  1073. mac_ops->tx_disable(pdata);
  1074. xgene_enet_napi_del(pdata);
  1075. xgene_enet_mdio_remove(pdata);
  1076. xgene_enet_delete_desc_rings(pdata);
  1077. unregister_netdev(ndev);
  1078. pdata->port_ops->shutdown(pdata);
  1079. free_netdev(ndev);
  1080. return 0;
  1081. }
  1082. #ifdef CONFIG_ACPI
  1083. static const struct acpi_device_id xgene_enet_acpi_match[] = {
  1084. { "APMC0D05", XGENE_ENET1},
  1085. { "APMC0D30", XGENE_ENET1},
  1086. { "APMC0D31", XGENE_ENET1},
  1087. { "APMC0D26", XGENE_ENET2},
  1088. { "APMC0D25", XGENE_ENET2},
  1089. { }
  1090. };
  1091. MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
  1092. #endif
  1093. #ifdef CONFIG_OF
  1094. static const struct of_device_id xgene_enet_of_match[] = {
  1095. {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
  1096. {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
  1097. {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
  1098. {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
  1099. {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
  1100. {},
  1101. };
  1102. MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
  1103. #endif
  1104. static struct platform_driver xgene_enet_driver = {
  1105. .driver = {
  1106. .name = "xgene-enet",
  1107. .of_match_table = of_match_ptr(xgene_enet_of_match),
  1108. .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
  1109. },
  1110. .probe = xgene_enet_probe,
  1111. .remove = xgene_enet_remove,
  1112. };
  1113. module_platform_driver(xgene_enet_driver);
  1114. MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
  1115. MODULE_VERSION(XGENE_DRV_VERSION);
  1116. MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
  1117. MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
  1118. MODULE_LICENSE("GPL");