mvsdio.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877
  1. /*
  2. * Marvell MMC/SD/SDIO driver
  3. *
  4. * Authors: Maen Suleiman, Nicolas Pitre
  5. * Copyright (C) 2008-2009 Marvell Ltd.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/mbus.h>
  16. #include <linux/delay.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/scatterlist.h>
  20. #include <linux/irq.h>
  21. #include <linux/clk.h>
  22. #include <linux/gpio.h>
  23. #include <linux/of_gpio.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/mmc/host.h>
  26. #include <linux/mmc/slot-gpio.h>
  27. #include <asm/sizes.h>
  28. #include <asm/unaligned.h>
  29. #include <linux/platform_data/mmc-mvsdio.h>
  30. #include "mvsdio.h"
  31. #define DRIVER_NAME "mvsdio"
  32. static int maxfreq;
  33. static int nodma;
  34. struct mvsd_host {
  35. void __iomem *base;
  36. struct mmc_request *mrq;
  37. spinlock_t lock;
  38. unsigned int xfer_mode;
  39. unsigned int intr_en;
  40. unsigned int ctrl;
  41. unsigned int pio_size;
  42. void *pio_ptr;
  43. unsigned int sg_frags;
  44. unsigned int ns_per_clk;
  45. unsigned int clock;
  46. unsigned int base_clock;
  47. struct timer_list timer;
  48. struct mmc_host *mmc;
  49. struct device *dev;
  50. struct clk *clk;
  51. };
  52. #define mvsd_write(offs, val) writel(val, iobase + (offs))
  53. #define mvsd_read(offs) readl(iobase + (offs))
  54. static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
  55. {
  56. void __iomem *iobase = host->base;
  57. unsigned int tmout;
  58. int tmout_index;
  59. /*
  60. * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
  61. * register is sometimes not set before a while when some
  62. * "unusual" data block sizes are used (such as with the SWITCH
  63. * command), even despite the fact that the XFER_DONE interrupt
  64. * was raised. And if another data transfer starts before
  65. * this bit comes to good sense (which eventually happens by
  66. * itself) then the new transfer simply fails with a timeout.
  67. */
  68. if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
  69. unsigned long t = jiffies + HZ;
  70. unsigned int hw_state, count = 0;
  71. do {
  72. hw_state = mvsd_read(MVSD_HW_STATE);
  73. if (time_after(jiffies, t)) {
  74. dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
  75. break;
  76. }
  77. count++;
  78. } while (!(hw_state & (1 << 13)));
  79. dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
  80. "(hw=0x%04x, count=%d, jiffies=%ld)\n",
  81. hw_state, count, jiffies - (t - HZ));
  82. }
  83. /* If timeout=0 then maximum timeout index is used. */
  84. tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
  85. tmout += data->timeout_clks;
  86. tmout_index = fls(tmout - 1) - 12;
  87. if (tmout_index < 0)
  88. tmout_index = 0;
  89. if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
  90. tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
  91. dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
  92. (data->flags & MMC_DATA_READ) ? "read" : "write",
  93. (u32)sg_virt(data->sg), data->blocks, data->blksz,
  94. tmout, tmout_index);
  95. host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
  96. host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
  97. mvsd_write(MVSD_HOST_CTRL, host->ctrl);
  98. mvsd_write(MVSD_BLK_COUNT, data->blocks);
  99. mvsd_write(MVSD_BLK_SIZE, data->blksz);
  100. if (nodma || (data->blksz | data->sg->offset) & 3 ||
  101. ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) {
  102. /*
  103. * We cannot do DMA on a buffer which offset or size
  104. * is not aligned on a 4-byte boundary.
  105. *
  106. * It also appears the host to card DMA can corrupt
  107. * data when the buffer is not aligned on a 64 byte
  108. * boundary.
  109. */
  110. host->pio_size = data->blocks * data->blksz;
  111. host->pio_ptr = sg_virt(data->sg);
  112. if (!nodma)
  113. dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n",
  114. host->pio_ptr, host->pio_size);
  115. return 1;
  116. } else {
  117. dma_addr_t phys_addr;
  118. int dma_dir = (data->flags & MMC_DATA_READ) ?
  119. DMA_FROM_DEVICE : DMA_TO_DEVICE;
  120. host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
  121. data->sg_len, dma_dir);
  122. phys_addr = sg_dma_address(data->sg);
  123. mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
  124. mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
  125. return 0;
  126. }
  127. }
  128. static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  129. {
  130. struct mvsd_host *host = mmc_priv(mmc);
  131. void __iomem *iobase = host->base;
  132. struct mmc_command *cmd = mrq->cmd;
  133. u32 cmdreg = 0, xfer = 0, intr = 0;
  134. unsigned long flags;
  135. BUG_ON(host->mrq != NULL);
  136. host->mrq = mrq;
  137. dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
  138. cmd->opcode, mvsd_read(MVSD_HW_STATE));
  139. cmdreg = MVSD_CMD_INDEX(cmd->opcode);
  140. if (cmd->flags & MMC_RSP_BUSY)
  141. cmdreg |= MVSD_CMD_RSP_48BUSY;
  142. else if (cmd->flags & MMC_RSP_136)
  143. cmdreg |= MVSD_CMD_RSP_136;
  144. else if (cmd->flags & MMC_RSP_PRESENT)
  145. cmdreg |= MVSD_CMD_RSP_48;
  146. else
  147. cmdreg |= MVSD_CMD_RSP_NONE;
  148. if (cmd->flags & MMC_RSP_CRC)
  149. cmdreg |= MVSD_CMD_CHECK_CMDCRC;
  150. if (cmd->flags & MMC_RSP_OPCODE)
  151. cmdreg |= MVSD_CMD_INDX_CHECK;
  152. if (cmd->flags & MMC_RSP_PRESENT) {
  153. cmdreg |= MVSD_UNEXPECTED_RESP;
  154. intr |= MVSD_NOR_UNEXP_RSP;
  155. }
  156. if (mrq->data) {
  157. struct mmc_data *data = mrq->data;
  158. int pio;
  159. cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
  160. xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
  161. if (data->flags & MMC_DATA_READ)
  162. xfer |= MVSD_XFER_MODE_TO_HOST;
  163. pio = mvsd_setup_data(host, data);
  164. if (pio) {
  165. xfer |= MVSD_XFER_MODE_PIO;
  166. /* PIO section of mvsd_irq has comments on those bits */
  167. if (data->flags & MMC_DATA_WRITE)
  168. intr |= MVSD_NOR_TX_AVAIL;
  169. else if (host->pio_size > 32)
  170. intr |= MVSD_NOR_RX_FIFO_8W;
  171. else
  172. intr |= MVSD_NOR_RX_READY;
  173. }
  174. if (data->stop) {
  175. struct mmc_command *stop = data->stop;
  176. u32 cmd12reg = 0;
  177. mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
  178. mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
  179. if (stop->flags & MMC_RSP_BUSY)
  180. cmd12reg |= MVSD_AUTOCMD12_BUSY;
  181. if (stop->flags & MMC_RSP_OPCODE)
  182. cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
  183. cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
  184. mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
  185. xfer |= MVSD_XFER_MODE_AUTO_CMD12;
  186. intr |= MVSD_NOR_AUTOCMD12_DONE;
  187. } else {
  188. intr |= MVSD_NOR_XFER_DONE;
  189. }
  190. } else {
  191. intr |= MVSD_NOR_CMD_DONE;
  192. }
  193. mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
  194. mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
  195. spin_lock_irqsave(&host->lock, flags);
  196. host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
  197. host->xfer_mode |= xfer;
  198. mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
  199. mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
  200. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  201. mvsd_write(MVSD_CMD, cmdreg);
  202. host->intr_en &= MVSD_NOR_CARD_INT;
  203. host->intr_en |= intr | MVSD_NOR_ERROR;
  204. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  205. mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
  206. mod_timer(&host->timer, jiffies + 5 * HZ);
  207. spin_unlock_irqrestore(&host->lock, flags);
  208. }
  209. static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
  210. u32 err_status)
  211. {
  212. void __iomem *iobase = host->base;
  213. if (cmd->flags & MMC_RSP_136) {
  214. unsigned int response[8], i;
  215. for (i = 0; i < 8; i++)
  216. response[i] = mvsd_read(MVSD_RSP(i));
  217. cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
  218. ((response[1] & 0xffff) << 6) |
  219. ((response[2] & 0xfc00) >> 10);
  220. cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
  221. ((response[3] & 0xffff) << 6) |
  222. ((response[4] & 0xfc00) >> 10);
  223. cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
  224. ((response[5] & 0xffff) << 6) |
  225. ((response[6] & 0xfc00) >> 10);
  226. cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
  227. ((response[7] & 0x3fff) << 8);
  228. } else if (cmd->flags & MMC_RSP_PRESENT) {
  229. unsigned int response[3], i;
  230. for (i = 0; i < 3; i++)
  231. response[i] = mvsd_read(MVSD_RSP(i));
  232. cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
  233. ((response[1] & 0xffff) << (14 - 8)) |
  234. ((response[0] & 0x03ff) << (30 - 8));
  235. cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
  236. cmd->resp[2] = 0;
  237. cmd->resp[3] = 0;
  238. }
  239. if (err_status & MVSD_ERR_CMD_TIMEOUT) {
  240. cmd->error = -ETIMEDOUT;
  241. } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
  242. MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
  243. cmd->error = -EILSEQ;
  244. }
  245. err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
  246. MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
  247. MVSD_ERR_CMD_STARTBIT);
  248. return err_status;
  249. }
  250. static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
  251. u32 err_status)
  252. {
  253. void __iomem *iobase = host->base;
  254. if (host->pio_ptr) {
  255. host->pio_ptr = NULL;
  256. host->pio_size = 0;
  257. } else {
  258. dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
  259. (data->flags & MMC_DATA_READ) ?
  260. DMA_FROM_DEVICE : DMA_TO_DEVICE);
  261. }
  262. if (err_status & MVSD_ERR_DATA_TIMEOUT)
  263. data->error = -ETIMEDOUT;
  264. else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
  265. data->error = -EILSEQ;
  266. else if (err_status & MVSD_ERR_XFER_SIZE)
  267. data->error = -EBADE;
  268. err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
  269. MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
  270. dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
  271. mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
  272. data->bytes_xfered =
  273. (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
  274. /* We can't be sure about the last block when errors are detected */
  275. if (data->bytes_xfered && data->error)
  276. data->bytes_xfered -= data->blksz;
  277. /* Handle Auto cmd 12 response */
  278. if (data->stop) {
  279. unsigned int response[3], i;
  280. for (i = 0; i < 3; i++)
  281. response[i] = mvsd_read(MVSD_AUTO_RSP(i));
  282. data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
  283. ((response[1] & 0xffff) << (14 - 8)) |
  284. ((response[0] & 0x03ff) << (30 - 8));
  285. data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
  286. data->stop->resp[2] = 0;
  287. data->stop->resp[3] = 0;
  288. if (err_status & MVSD_ERR_AUTOCMD12) {
  289. u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
  290. dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
  291. if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
  292. data->stop->error = -ENOEXEC;
  293. else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
  294. data->stop->error = -ETIMEDOUT;
  295. else if (err_cmd12)
  296. data->stop->error = -EILSEQ;
  297. err_status &= ~MVSD_ERR_AUTOCMD12;
  298. }
  299. }
  300. return err_status;
  301. }
  302. static irqreturn_t mvsd_irq(int irq, void *dev)
  303. {
  304. struct mvsd_host *host = dev;
  305. void __iomem *iobase = host->base;
  306. u32 intr_status, intr_done_mask;
  307. int irq_handled = 0;
  308. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  309. dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
  310. intr_status, mvsd_read(MVSD_NOR_INTR_EN),
  311. mvsd_read(MVSD_HW_STATE));
  312. /*
  313. * It looks like, SDIO IP can issue one late, spurious irq
  314. * although all irqs should be disabled. To work around this,
  315. * bail out early, if we didn't expect any irqs to occur.
  316. */
  317. if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) {
  318. dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n",
  319. mvsd_read(MVSD_NOR_INTR_STATUS),
  320. mvsd_read(MVSD_NOR_INTR_EN),
  321. mvsd_read(MVSD_ERR_INTR_STATUS),
  322. mvsd_read(MVSD_ERR_INTR_EN));
  323. return IRQ_HANDLED;
  324. }
  325. spin_lock(&host->lock);
  326. /* PIO handling, if needed. Messy business... */
  327. if (host->pio_size &&
  328. (intr_status & host->intr_en &
  329. (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
  330. u16 *p = host->pio_ptr;
  331. int s = host->pio_size;
  332. while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
  333. readsw(iobase + MVSD_FIFO, p, 16);
  334. p += 16;
  335. s -= 32;
  336. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  337. }
  338. /*
  339. * Normally we'd use < 32 here, but the RX_FIFO_8W bit
  340. * doesn't appear to assert when there is exactly 32 bytes
  341. * (8 words) left to fetch in a transfer.
  342. */
  343. if (s <= 32) {
  344. while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
  345. put_unaligned(mvsd_read(MVSD_FIFO), p++);
  346. put_unaligned(mvsd_read(MVSD_FIFO), p++);
  347. s -= 4;
  348. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  349. }
  350. if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
  351. u16 val[2] = {0, 0};
  352. val[0] = mvsd_read(MVSD_FIFO);
  353. val[1] = mvsd_read(MVSD_FIFO);
  354. memcpy(p, ((void *)&val) + 4 - s, s);
  355. s = 0;
  356. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  357. }
  358. if (s == 0) {
  359. host->intr_en &=
  360. ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
  361. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  362. } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
  363. host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
  364. host->intr_en |= MVSD_NOR_RX_READY;
  365. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  366. }
  367. }
  368. dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
  369. s, intr_status, mvsd_read(MVSD_HW_STATE));
  370. host->pio_ptr = p;
  371. host->pio_size = s;
  372. irq_handled = 1;
  373. } else if (host->pio_size &&
  374. (intr_status & host->intr_en &
  375. (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
  376. u16 *p = host->pio_ptr;
  377. int s = host->pio_size;
  378. /*
  379. * The TX_FIFO_8W bit is unreliable. When set, bursting
  380. * 16 halfwords all at once in the FIFO drops data. Actually
  381. * TX_AVAIL does go off after only one word is pushed even if
  382. * TX_FIFO_8W remains set.
  383. */
  384. while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
  385. mvsd_write(MVSD_FIFO, get_unaligned(p++));
  386. mvsd_write(MVSD_FIFO, get_unaligned(p++));
  387. s -= 4;
  388. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  389. }
  390. if (s < 4) {
  391. if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
  392. u16 val[2] = {0, 0};
  393. memcpy(((void *)&val) + 4 - s, p, s);
  394. mvsd_write(MVSD_FIFO, val[0]);
  395. mvsd_write(MVSD_FIFO, val[1]);
  396. s = 0;
  397. intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
  398. }
  399. if (s == 0) {
  400. host->intr_en &=
  401. ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
  402. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  403. }
  404. }
  405. dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
  406. s, intr_status, mvsd_read(MVSD_HW_STATE));
  407. host->pio_ptr = p;
  408. host->pio_size = s;
  409. irq_handled = 1;
  410. }
  411. mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
  412. intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
  413. MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
  414. if (intr_status & host->intr_en & ~intr_done_mask) {
  415. struct mmc_request *mrq = host->mrq;
  416. struct mmc_command *cmd = mrq->cmd;
  417. u32 err_status = 0;
  418. del_timer(&host->timer);
  419. host->mrq = NULL;
  420. host->intr_en &= MVSD_NOR_CARD_INT;
  421. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  422. mvsd_write(MVSD_ERR_INTR_EN, 0);
  423. spin_unlock(&host->lock);
  424. if (intr_status & MVSD_NOR_UNEXP_RSP) {
  425. cmd->error = -EPROTO;
  426. } else if (intr_status & MVSD_NOR_ERROR) {
  427. err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
  428. dev_dbg(host->dev, "err 0x%04x\n", err_status);
  429. }
  430. err_status = mvsd_finish_cmd(host, cmd, err_status);
  431. if (mrq->data)
  432. err_status = mvsd_finish_data(host, mrq->data, err_status);
  433. if (err_status) {
  434. dev_err(host->dev, "unhandled error status %#04x\n",
  435. err_status);
  436. cmd->error = -ENOMSG;
  437. }
  438. mmc_request_done(host->mmc, mrq);
  439. irq_handled = 1;
  440. } else
  441. spin_unlock(&host->lock);
  442. if (intr_status & MVSD_NOR_CARD_INT) {
  443. mmc_signal_sdio_irq(host->mmc);
  444. irq_handled = 1;
  445. }
  446. if (irq_handled)
  447. return IRQ_HANDLED;
  448. dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
  449. intr_status, host->intr_en, host->pio_size);
  450. return IRQ_NONE;
  451. }
  452. static void mvsd_timeout_timer(unsigned long data)
  453. {
  454. struct mvsd_host *host = (struct mvsd_host *)data;
  455. void __iomem *iobase = host->base;
  456. struct mmc_request *mrq;
  457. unsigned long flags;
  458. spin_lock_irqsave(&host->lock, flags);
  459. mrq = host->mrq;
  460. if (mrq) {
  461. dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
  462. dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
  463. mvsd_read(MVSD_HW_STATE),
  464. mvsd_read(MVSD_NOR_INTR_STATUS),
  465. mvsd_read(MVSD_NOR_INTR_EN));
  466. host->mrq = NULL;
  467. mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
  468. host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
  469. mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
  470. host->intr_en &= MVSD_NOR_CARD_INT;
  471. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  472. mvsd_write(MVSD_ERR_INTR_EN, 0);
  473. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  474. mrq->cmd->error = -ETIMEDOUT;
  475. mvsd_finish_cmd(host, mrq->cmd, 0);
  476. if (mrq->data) {
  477. mrq->data->error = -ETIMEDOUT;
  478. mvsd_finish_data(host, mrq->data, 0);
  479. }
  480. }
  481. spin_unlock_irqrestore(&host->lock, flags);
  482. if (mrq)
  483. mmc_request_done(host->mmc, mrq);
  484. }
  485. static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
  486. {
  487. struct mvsd_host *host = mmc_priv(mmc);
  488. void __iomem *iobase = host->base;
  489. unsigned long flags;
  490. spin_lock_irqsave(&host->lock, flags);
  491. if (enable) {
  492. host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
  493. host->intr_en |= MVSD_NOR_CARD_INT;
  494. } else {
  495. host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
  496. host->intr_en &= ~MVSD_NOR_CARD_INT;
  497. }
  498. mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
  499. mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
  500. spin_unlock_irqrestore(&host->lock, flags);
  501. }
  502. static void mvsd_power_up(struct mvsd_host *host)
  503. {
  504. void __iomem *iobase = host->base;
  505. dev_dbg(host->dev, "power up\n");
  506. mvsd_write(MVSD_NOR_INTR_EN, 0);
  507. mvsd_write(MVSD_ERR_INTR_EN, 0);
  508. mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
  509. mvsd_write(MVSD_XFER_MODE, 0);
  510. mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
  511. mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
  512. mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
  513. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  514. }
  515. static void mvsd_power_down(struct mvsd_host *host)
  516. {
  517. void __iomem *iobase = host->base;
  518. dev_dbg(host->dev, "power down\n");
  519. mvsd_write(MVSD_NOR_INTR_EN, 0);
  520. mvsd_write(MVSD_ERR_INTR_EN, 0);
  521. mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
  522. mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
  523. mvsd_write(MVSD_NOR_STATUS_EN, 0);
  524. mvsd_write(MVSD_ERR_STATUS_EN, 0);
  525. mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
  526. mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
  527. }
  528. static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  529. {
  530. struct mvsd_host *host = mmc_priv(mmc);
  531. void __iomem *iobase = host->base;
  532. u32 ctrl_reg = 0;
  533. if (ios->power_mode == MMC_POWER_UP)
  534. mvsd_power_up(host);
  535. if (ios->clock == 0) {
  536. mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
  537. mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
  538. host->clock = 0;
  539. dev_dbg(host->dev, "clock off\n");
  540. } else if (ios->clock != host->clock) {
  541. u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
  542. if (m > MVSD_BASE_DIV_MAX)
  543. m = MVSD_BASE_DIV_MAX;
  544. mvsd_write(MVSD_CLK_DIV, m);
  545. host->clock = ios->clock;
  546. host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
  547. dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
  548. ios->clock, host->base_clock / (m+1), m);
  549. }
  550. /* default transfer mode */
  551. ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
  552. ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
  553. /* default to maximum timeout */
  554. ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
  555. ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
  556. if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
  557. ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
  558. if (ios->bus_width == MMC_BUS_WIDTH_4)
  559. ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
  560. /*
  561. * The HI_SPEED_EN bit is causing trouble with many (but not all)
  562. * high speed SD, SDHC and SDIO cards. Not enabling that bit
  563. * makes all cards work. So let's just ignore that bit for now
  564. * and revisit this issue if problems for not enabling this bit
  565. * are ever reported.
  566. */
  567. #if 0
  568. if (ios->timing == MMC_TIMING_MMC_HS ||
  569. ios->timing == MMC_TIMING_SD_HS)
  570. ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
  571. #endif
  572. host->ctrl = ctrl_reg;
  573. mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
  574. dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
  575. (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
  576. "push-pull" : "open-drain",
  577. (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
  578. "4bit-width" : "1bit-width",
  579. (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
  580. "high-speed" : "");
  581. if (ios->power_mode == MMC_POWER_OFF)
  582. mvsd_power_down(host);
  583. }
  584. static const struct mmc_host_ops mvsd_ops = {
  585. .request = mvsd_request,
  586. .get_ro = mmc_gpio_get_ro,
  587. .set_ios = mvsd_set_ios,
  588. .enable_sdio_irq = mvsd_enable_sdio_irq,
  589. };
  590. static void
  591. mv_conf_mbus_windows(struct mvsd_host *host,
  592. const struct mbus_dram_target_info *dram)
  593. {
  594. void __iomem *iobase = host->base;
  595. int i;
  596. for (i = 0; i < 4; i++) {
  597. writel(0, iobase + MVSD_WINDOW_CTRL(i));
  598. writel(0, iobase + MVSD_WINDOW_BASE(i));
  599. }
  600. for (i = 0; i < dram->num_cs; i++) {
  601. const struct mbus_dram_window *cs = dram->cs + i;
  602. writel(((cs->size - 1) & 0xffff0000) |
  603. (cs->mbus_attr << 8) |
  604. (dram->mbus_dram_target_id << 4) | 1,
  605. iobase + MVSD_WINDOW_CTRL(i));
  606. writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
  607. }
  608. }
  609. static int mvsd_probe(struct platform_device *pdev)
  610. {
  611. struct device_node *np = pdev->dev.of_node;
  612. struct mmc_host *mmc = NULL;
  613. struct mvsd_host *host = NULL;
  614. const struct mbus_dram_target_info *dram;
  615. struct resource *r;
  616. int ret, irq;
  617. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  618. irq = platform_get_irq(pdev, 0);
  619. if (!r || irq < 0)
  620. return -ENXIO;
  621. mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
  622. if (!mmc) {
  623. ret = -ENOMEM;
  624. goto out;
  625. }
  626. host = mmc_priv(mmc);
  627. host->mmc = mmc;
  628. host->dev = &pdev->dev;
  629. /*
  630. * Some non-DT platforms do not pass a clock, and the clock
  631. * frequency is passed through platform_data. On DT platforms,
  632. * a clock must always be passed, even if there is no gatable
  633. * clock associated to the SDIO interface (it can simply be a
  634. * fixed rate clock).
  635. */
  636. host->clk = devm_clk_get(&pdev->dev, NULL);
  637. if (!IS_ERR(host->clk))
  638. clk_prepare_enable(host->clk);
  639. mmc->ops = &mvsd_ops;
  640. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  641. mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
  642. mmc->f_max = MVSD_CLOCKRATE_MAX;
  643. mmc->max_blk_size = 2048;
  644. mmc->max_blk_count = 65535;
  645. mmc->max_segs = 1;
  646. mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
  647. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  648. if (np) {
  649. if (IS_ERR(host->clk)) {
  650. dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
  651. ret = -EINVAL;
  652. goto out;
  653. }
  654. host->base_clock = clk_get_rate(host->clk) / 2;
  655. ret = mmc_of_parse(mmc);
  656. if (ret < 0)
  657. goto out;
  658. } else {
  659. const struct mvsdio_platform_data *mvsd_data;
  660. mvsd_data = pdev->dev.platform_data;
  661. if (!mvsd_data) {
  662. ret = -ENXIO;
  663. goto out;
  664. }
  665. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
  666. MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
  667. host->base_clock = mvsd_data->clock / 2;
  668. /* GPIO 0 regarded as invalid for backward compatibility */
  669. if (mvsd_data->gpio_card_detect &&
  670. gpio_is_valid(mvsd_data->gpio_card_detect)) {
  671. ret = mmc_gpio_request_cd(mmc,
  672. mvsd_data->gpio_card_detect,
  673. 0);
  674. if (ret)
  675. goto out;
  676. } else {
  677. mmc->caps |= MMC_CAP_NEEDS_POLL;
  678. }
  679. if (mvsd_data->gpio_write_protect &&
  680. gpio_is_valid(mvsd_data->gpio_write_protect))
  681. mmc_gpio_request_ro(mmc, mvsd_data->gpio_write_protect);
  682. }
  683. if (maxfreq)
  684. mmc->f_max = maxfreq;
  685. spin_lock_init(&host->lock);
  686. host->base = devm_ioremap_resource(&pdev->dev, r);
  687. if (IS_ERR(host->base)) {
  688. ret = PTR_ERR(host->base);
  689. goto out;
  690. }
  691. /* (Re-)program MBUS remapping windows if we are asked to. */
  692. dram = mv_mbus_dram_info();
  693. if (dram)
  694. mv_conf_mbus_windows(host, dram);
  695. mvsd_power_down(host);
  696. ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
  697. if (ret) {
  698. dev_err(&pdev->dev, "cannot assign irq %d\n", irq);
  699. goto out;
  700. }
  701. setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
  702. platform_set_drvdata(pdev, mmc);
  703. ret = mmc_add_host(mmc);
  704. if (ret)
  705. goto out;
  706. if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
  707. dev_dbg(&pdev->dev, "using GPIO for card detection\n");
  708. else
  709. dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n");
  710. return 0;
  711. out:
  712. if (mmc) {
  713. if (!IS_ERR(host->clk))
  714. clk_disable_unprepare(host->clk);
  715. mmc_free_host(mmc);
  716. }
  717. return ret;
  718. }
  719. static int mvsd_remove(struct platform_device *pdev)
  720. {
  721. struct mmc_host *mmc = platform_get_drvdata(pdev);
  722. struct mvsd_host *host = mmc_priv(mmc);
  723. mmc_remove_host(mmc);
  724. del_timer_sync(&host->timer);
  725. mvsd_power_down(host);
  726. if (!IS_ERR(host->clk))
  727. clk_disable_unprepare(host->clk);
  728. mmc_free_host(mmc);
  729. return 0;
  730. }
  731. static const struct of_device_id mvsdio_dt_ids[] = {
  732. { .compatible = "marvell,orion-sdio" },
  733. { /* sentinel */ }
  734. };
  735. MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
  736. static struct platform_driver mvsd_driver = {
  737. .probe = mvsd_probe,
  738. .remove = mvsd_remove,
  739. .driver = {
  740. .name = DRIVER_NAME,
  741. .of_match_table = mvsdio_dt_ids,
  742. },
  743. };
  744. module_platform_driver(mvsd_driver);
  745. /* maximum card clock frequency (default 50MHz) */
  746. module_param(maxfreq, int, 0);
  747. /* force PIO transfers all the time */
  748. module_param(nodma, int, 0);
  749. MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
  750. MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
  751. MODULE_LICENSE("GPL");
  752. MODULE_ALIAS("platform:mvsdio");