arizona-core.c 32 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/regmap.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/regulator/machine.h>
  25. #include <linux/slab.h>
  26. #include <linux/mfd/arizona/core.h>
  27. #include <linux/mfd/arizona/registers.h>
  28. #include "arizona.h"
  29. static const char *wm5102_core_supplies[] = {
  30. "AVDD",
  31. "DBVDD1",
  32. };
  33. int arizona_clk32k_enable(struct arizona *arizona)
  34. {
  35. int ret = 0;
  36. mutex_lock(&arizona->clk_lock);
  37. arizona->clk32k_ref++;
  38. if (arizona->clk32k_ref == 1) {
  39. switch (arizona->pdata.clk32k_src) {
  40. case ARIZONA_32KZ_MCLK1:
  41. ret = pm_runtime_get_sync(arizona->dev);
  42. if (ret != 0)
  43. goto out;
  44. break;
  45. }
  46. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  47. ARIZONA_CLK_32K_ENA,
  48. ARIZONA_CLK_32K_ENA);
  49. }
  50. out:
  51. if (ret != 0)
  52. arizona->clk32k_ref--;
  53. mutex_unlock(&arizona->clk_lock);
  54. return ret;
  55. }
  56. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  57. int arizona_clk32k_disable(struct arizona *arizona)
  58. {
  59. int ret = 0;
  60. mutex_lock(&arizona->clk_lock);
  61. BUG_ON(arizona->clk32k_ref <= 0);
  62. arizona->clk32k_ref--;
  63. if (arizona->clk32k_ref == 0) {
  64. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  65. ARIZONA_CLK_32K_ENA, 0);
  66. switch (arizona->pdata.clk32k_src) {
  67. case ARIZONA_32KZ_MCLK1:
  68. pm_runtime_put_sync(arizona->dev);
  69. break;
  70. }
  71. }
  72. mutex_unlock(&arizona->clk_lock);
  73. return ret;
  74. }
  75. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  76. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  77. {
  78. struct arizona *arizona = data;
  79. dev_err(arizona->dev, "CLKGEN error\n");
  80. return IRQ_HANDLED;
  81. }
  82. static irqreturn_t arizona_underclocked(int irq, void *data)
  83. {
  84. struct arizona *arizona = data;
  85. unsigned int val;
  86. int ret;
  87. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  88. &val);
  89. if (ret != 0) {
  90. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  91. ret);
  92. return IRQ_NONE;
  93. }
  94. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  95. dev_err(arizona->dev, "AIF3 underclocked\n");
  96. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  97. dev_err(arizona->dev, "AIF2 underclocked\n");
  98. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  99. dev_err(arizona->dev, "AIF1 underclocked\n");
  100. if (val & ARIZONA_ISRC3_UNDERCLOCKED_STS)
  101. dev_err(arizona->dev, "ISRC3 underclocked\n");
  102. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  103. dev_err(arizona->dev, "ISRC2 underclocked\n");
  104. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  105. dev_err(arizona->dev, "ISRC1 underclocked\n");
  106. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  107. dev_err(arizona->dev, "FX underclocked\n");
  108. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  109. dev_err(arizona->dev, "ASRC underclocked\n");
  110. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  111. dev_err(arizona->dev, "DAC underclocked\n");
  112. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  113. dev_err(arizona->dev, "ADC underclocked\n");
  114. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  115. dev_err(arizona->dev, "Mixer dropped sample\n");
  116. return IRQ_HANDLED;
  117. }
  118. static irqreturn_t arizona_overclocked(int irq, void *data)
  119. {
  120. struct arizona *arizona = data;
  121. unsigned int val[2];
  122. int ret;
  123. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  124. &val[0], 2);
  125. if (ret != 0) {
  126. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  127. ret);
  128. return IRQ_NONE;
  129. }
  130. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  131. dev_err(arizona->dev, "PWM overclocked\n");
  132. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  133. dev_err(arizona->dev, "FX core overclocked\n");
  134. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  135. dev_err(arizona->dev, "DAC SYS overclocked\n");
  136. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  137. dev_err(arizona->dev, "DAC WARP overclocked\n");
  138. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  139. dev_err(arizona->dev, "ADC overclocked\n");
  140. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  141. dev_err(arizona->dev, "Mixer overclocked\n");
  142. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  143. dev_err(arizona->dev, "AIF3 overclocked\n");
  144. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  145. dev_err(arizona->dev, "AIF2 overclocked\n");
  146. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  147. dev_err(arizona->dev, "AIF1 overclocked\n");
  148. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  149. dev_err(arizona->dev, "Pad control overclocked\n");
  150. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  151. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  152. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  153. dev_err(arizona->dev, "Slimbus async overclocked\n");
  154. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  155. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  156. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  157. dev_err(arizona->dev, "ASRC async system overclocked\n");
  158. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  160. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  162. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  164. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  165. dev_err(arizona->dev, "DSP1 overclocked\n");
  166. if (val[1] & ARIZONA_ISRC3_OVERCLOCKED_STS)
  167. dev_err(arizona->dev, "ISRC3 overclocked\n");
  168. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  169. dev_err(arizona->dev, "ISRC2 overclocked\n");
  170. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  171. dev_err(arizona->dev, "ISRC1 overclocked\n");
  172. return IRQ_HANDLED;
  173. }
  174. static int arizona_poll_reg(struct arizona *arizona,
  175. int timeout, unsigned int reg,
  176. unsigned int mask, unsigned int target)
  177. {
  178. unsigned int val = 0;
  179. int ret, i;
  180. for (i = 0; i < timeout; i++) {
  181. ret = regmap_read(arizona->regmap, reg, &val);
  182. if (ret != 0) {
  183. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  184. reg, ret);
  185. continue;
  186. }
  187. if ((val & mask) == target)
  188. return 0;
  189. msleep(1);
  190. }
  191. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  192. return -ETIMEDOUT;
  193. }
  194. static int arizona_wait_for_boot(struct arizona *arizona)
  195. {
  196. int ret;
  197. /*
  198. * We can't use an interrupt as we need to runtime resume to do so,
  199. * we won't race with the interrupt handler as it'll be blocked on
  200. * runtime resume.
  201. */
  202. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  203. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  204. if (!ret)
  205. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  206. ARIZONA_BOOT_DONE_STS);
  207. pm_runtime_mark_last_busy(arizona->dev);
  208. return ret;
  209. }
  210. static inline void arizona_enable_reset(struct arizona *arizona)
  211. {
  212. if (arizona->pdata.reset)
  213. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  214. }
  215. static void arizona_disable_reset(struct arizona *arizona)
  216. {
  217. if (arizona->pdata.reset) {
  218. switch (arizona->type) {
  219. case WM5110:
  220. case WM8280:
  221. /* Meet requirements for minimum reset duration */
  222. msleep(5);
  223. break;
  224. default:
  225. break;
  226. }
  227. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  228. msleep(1);
  229. }
  230. }
  231. struct arizona_sysclk_state {
  232. unsigned int fll;
  233. unsigned int sysclk;
  234. };
  235. static int arizona_enable_freerun_sysclk(struct arizona *arizona,
  236. struct arizona_sysclk_state *state)
  237. {
  238. int ret, err;
  239. /* Cache existing FLL and SYSCLK settings */
  240. ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &state->fll);
  241. if (ret) {
  242. dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
  243. ret);
  244. return ret;
  245. }
  246. ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
  247. &state->sysclk);
  248. if (ret) {
  249. dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
  250. ret);
  251. return ret;
  252. }
  253. /* Start up SYSCLK using the FLL in free running mode */
  254. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
  255. ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
  256. if (ret) {
  257. dev_err(arizona->dev,
  258. "Failed to start FLL in freerunning mode: %d\n",
  259. ret);
  260. return ret;
  261. }
  262. ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
  263. ARIZONA_FLL1_CLOCK_OK_STS,
  264. ARIZONA_FLL1_CLOCK_OK_STS);
  265. if (ret) {
  266. ret = -ETIMEDOUT;
  267. goto err_fll;
  268. }
  269. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
  270. if (ret) {
  271. dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
  272. goto err_fll;
  273. }
  274. return 0;
  275. err_fll:
  276. err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
  277. if (err)
  278. dev_err(arizona->dev,
  279. "Failed to re-apply old FLL settings: %d\n", err);
  280. return ret;
  281. }
  282. static int arizona_disable_freerun_sysclk(struct arizona *arizona,
  283. struct arizona_sysclk_state *state)
  284. {
  285. int ret;
  286. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1,
  287. state->sysclk);
  288. if (ret) {
  289. dev_err(arizona->dev,
  290. "Failed to re-apply old SYSCLK settings: %d\n", ret);
  291. return ret;
  292. }
  293. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, state->fll);
  294. if (ret) {
  295. dev_err(arizona->dev,
  296. "Failed to re-apply old FLL settings: %d\n", ret);
  297. return ret;
  298. }
  299. return 0;
  300. }
  301. static int wm5102_apply_hardware_patch(struct arizona *arizona)
  302. {
  303. struct arizona_sysclk_state state;
  304. int err, ret;
  305. ret = arizona_enable_freerun_sysclk(arizona, &state);
  306. if (ret)
  307. return ret;
  308. /* Start the write sequencer and wait for it to finish */
  309. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  310. ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
  311. if (ret) {
  312. dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
  313. ret);
  314. goto err;
  315. }
  316. ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
  317. ARIZONA_WSEQ_BUSY, 0);
  318. if (ret) {
  319. regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  320. ARIZONA_WSEQ_ABORT);
  321. ret = -ETIMEDOUT;
  322. }
  323. err:
  324. err = arizona_disable_freerun_sysclk(arizona, &state);
  325. return ret ?: err;
  326. }
  327. /*
  328. * Register patch to some of the CODECs internal write sequences
  329. * to ensure a clean exit from the low power sleep state.
  330. */
  331. static const struct reg_default wm5110_sleep_patch[] = {
  332. { 0x337A, 0xC100 },
  333. { 0x337B, 0x0041 },
  334. { 0x3300, 0xA210 },
  335. { 0x3301, 0x050C },
  336. };
  337. static int wm5110_apply_sleep_patch(struct arizona *arizona)
  338. {
  339. struct arizona_sysclk_state state;
  340. int err, ret;
  341. ret = arizona_enable_freerun_sysclk(arizona, &state);
  342. if (ret)
  343. return ret;
  344. ret = regmap_multi_reg_write_bypassed(arizona->regmap,
  345. wm5110_sleep_patch,
  346. ARRAY_SIZE(wm5110_sleep_patch));
  347. err = arizona_disable_freerun_sysclk(arizona, &state);
  348. return ret ?: err;
  349. }
  350. static int wm5102_clear_write_sequencer(struct arizona *arizona)
  351. {
  352. int ret;
  353. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_3,
  354. 0x0);
  355. if (ret) {
  356. dev_err(arizona->dev,
  357. "Failed to clear write sequencer state: %d\n", ret);
  358. return ret;
  359. }
  360. arizona_enable_reset(arizona);
  361. regulator_disable(arizona->dcvdd);
  362. msleep(20);
  363. ret = regulator_enable(arizona->dcvdd);
  364. if (ret) {
  365. dev_err(arizona->dev, "Failed to re-enable DCVDD: %d\n", ret);
  366. return ret;
  367. }
  368. arizona_disable_reset(arizona);
  369. return 0;
  370. }
  371. #ifdef CONFIG_PM
  372. static int arizona_runtime_resume(struct device *dev)
  373. {
  374. struct arizona *arizona = dev_get_drvdata(dev);
  375. int ret;
  376. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  377. if (arizona->has_fully_powered_off) {
  378. dev_dbg(arizona->dev, "Re-enabling core supplies\n");
  379. ret = regulator_bulk_enable(arizona->num_core_supplies,
  380. arizona->core_supplies);
  381. if (ret) {
  382. dev_err(dev, "Failed to enable core supplies: %d\n",
  383. ret);
  384. return ret;
  385. }
  386. }
  387. ret = regulator_enable(arizona->dcvdd);
  388. if (ret != 0) {
  389. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  390. if (arizona->has_fully_powered_off)
  391. regulator_bulk_disable(arizona->num_core_supplies,
  392. arizona->core_supplies);
  393. return ret;
  394. }
  395. if (arizona->has_fully_powered_off) {
  396. arizona_disable_reset(arizona);
  397. enable_irq(arizona->irq);
  398. arizona->has_fully_powered_off = false;
  399. }
  400. regcache_cache_only(arizona->regmap, false);
  401. switch (arizona->type) {
  402. case WM5102:
  403. if (arizona->external_dcvdd) {
  404. ret = regmap_update_bits(arizona->regmap,
  405. ARIZONA_ISOLATION_CONTROL,
  406. ARIZONA_ISOLATE_DCVDD1, 0);
  407. if (ret != 0) {
  408. dev_err(arizona->dev,
  409. "Failed to connect DCVDD: %d\n", ret);
  410. goto err;
  411. }
  412. }
  413. ret = wm5102_patch(arizona);
  414. if (ret != 0) {
  415. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  416. ret);
  417. goto err;
  418. }
  419. ret = wm5102_apply_hardware_patch(arizona);
  420. if (ret) {
  421. dev_err(arizona->dev,
  422. "Failed to apply hardware patch: %d\n",
  423. ret);
  424. goto err;
  425. }
  426. break;
  427. case WM5110:
  428. case WM8280:
  429. ret = arizona_wait_for_boot(arizona);
  430. if (ret)
  431. goto err;
  432. if (arizona->external_dcvdd) {
  433. ret = regmap_update_bits(arizona->regmap,
  434. ARIZONA_ISOLATION_CONTROL,
  435. ARIZONA_ISOLATE_DCVDD1, 0);
  436. if (ret) {
  437. dev_err(arizona->dev,
  438. "Failed to connect DCVDD: %d\n", ret);
  439. goto err;
  440. }
  441. } else {
  442. /*
  443. * As this is only called for the internal regulator
  444. * (where we know voltage ranges available) it is ok
  445. * to request an exact range.
  446. */
  447. ret = regulator_set_voltage(arizona->dcvdd,
  448. 1200000, 1200000);
  449. if (ret < 0) {
  450. dev_err(arizona->dev,
  451. "Failed to set resume voltage: %d\n",
  452. ret);
  453. goto err;
  454. }
  455. }
  456. ret = wm5110_apply_sleep_patch(arizona);
  457. if (ret) {
  458. dev_err(arizona->dev,
  459. "Failed to re-apply sleep patch: %d\n",
  460. ret);
  461. goto err;
  462. }
  463. break;
  464. default:
  465. ret = arizona_wait_for_boot(arizona);
  466. if (ret != 0) {
  467. goto err;
  468. }
  469. if (arizona->external_dcvdd) {
  470. ret = regmap_update_bits(arizona->regmap,
  471. ARIZONA_ISOLATION_CONTROL,
  472. ARIZONA_ISOLATE_DCVDD1, 0);
  473. if (ret != 0) {
  474. dev_err(arizona->dev,
  475. "Failed to connect DCVDD: %d\n", ret);
  476. goto err;
  477. }
  478. }
  479. break;
  480. }
  481. ret = regcache_sync(arizona->regmap);
  482. if (ret != 0) {
  483. dev_err(arizona->dev, "Failed to restore register cache\n");
  484. goto err;
  485. }
  486. return 0;
  487. err:
  488. regcache_cache_only(arizona->regmap, true);
  489. regulator_disable(arizona->dcvdd);
  490. return ret;
  491. }
  492. static int arizona_runtime_suspend(struct device *dev)
  493. {
  494. struct arizona *arizona = dev_get_drvdata(dev);
  495. unsigned int val;
  496. int ret;
  497. dev_dbg(arizona->dev, "Entering AoD mode\n");
  498. ret = regmap_read(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, &val);
  499. if (ret) {
  500. dev_err(dev, "Failed to check jack det status: %d\n", ret);
  501. return ret;
  502. }
  503. if (arizona->external_dcvdd) {
  504. ret = regmap_update_bits(arizona->regmap,
  505. ARIZONA_ISOLATION_CONTROL,
  506. ARIZONA_ISOLATE_DCVDD1,
  507. ARIZONA_ISOLATE_DCVDD1);
  508. if (ret != 0) {
  509. dev_err(arizona->dev, "Failed to isolate DCVDD: %d\n",
  510. ret);
  511. return ret;
  512. }
  513. }
  514. switch (arizona->type) {
  515. case WM5110:
  516. case WM8280:
  517. if (arizona->external_dcvdd)
  518. break;
  519. /*
  520. * As this is only called for the internal regulator
  521. * (where we know voltage ranges available) it is ok
  522. * to request an exact range.
  523. */
  524. ret = regulator_set_voltage(arizona->dcvdd, 1175000, 1175000);
  525. if (ret < 0) {
  526. dev_err(arizona->dev,
  527. "Failed to set suspend voltage: %d\n", ret);
  528. return ret;
  529. }
  530. break;
  531. case WM5102:
  532. if (!(val & ARIZONA_JD1_ENA)) {
  533. ret = regmap_write(arizona->regmap,
  534. ARIZONA_WRITE_SEQUENCER_CTRL_3, 0x0);
  535. if (ret) {
  536. dev_err(arizona->dev,
  537. "Failed to clear write sequencer: %d\n",
  538. ret);
  539. return ret;
  540. }
  541. }
  542. break;
  543. default:
  544. break;
  545. }
  546. regcache_cache_only(arizona->regmap, true);
  547. regcache_mark_dirty(arizona->regmap);
  548. regulator_disable(arizona->dcvdd);
  549. /* Allow us to completely power down if no jack detection */
  550. if (!(val & ARIZONA_JD1_ENA)) {
  551. dev_dbg(arizona->dev, "Fully powering off\n");
  552. arizona->has_fully_powered_off = true;
  553. disable_irq(arizona->irq);
  554. arizona_enable_reset(arizona);
  555. regulator_bulk_disable(arizona->num_core_supplies,
  556. arizona->core_supplies);
  557. }
  558. return 0;
  559. }
  560. #endif
  561. #ifdef CONFIG_PM_SLEEP
  562. static int arizona_suspend(struct device *dev)
  563. {
  564. struct arizona *arizona = dev_get_drvdata(dev);
  565. dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
  566. disable_irq(arizona->irq);
  567. return 0;
  568. }
  569. static int arizona_suspend_late(struct device *dev)
  570. {
  571. struct arizona *arizona = dev_get_drvdata(dev);
  572. dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
  573. enable_irq(arizona->irq);
  574. return 0;
  575. }
  576. static int arizona_resume_noirq(struct device *dev)
  577. {
  578. struct arizona *arizona = dev_get_drvdata(dev);
  579. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  580. disable_irq(arizona->irq);
  581. return 0;
  582. }
  583. static int arizona_resume(struct device *dev)
  584. {
  585. struct arizona *arizona = dev_get_drvdata(dev);
  586. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  587. enable_irq(arizona->irq);
  588. return 0;
  589. }
  590. #endif
  591. const struct dev_pm_ops arizona_pm_ops = {
  592. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  593. arizona_runtime_resume,
  594. NULL)
  595. SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
  596. #ifdef CONFIG_PM_SLEEP
  597. .suspend_late = arizona_suspend_late,
  598. .resume_noirq = arizona_resume_noirq,
  599. #endif
  600. };
  601. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  602. #ifdef CONFIG_OF
  603. unsigned long arizona_of_get_type(struct device *dev)
  604. {
  605. const struct of_device_id *id = of_match_device(arizona_of_match, dev);
  606. if (id)
  607. return (unsigned long)id->data;
  608. else
  609. return 0;
  610. }
  611. EXPORT_SYMBOL_GPL(arizona_of_get_type);
  612. int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop,
  613. bool mandatory)
  614. {
  615. int gpio;
  616. gpio = of_get_named_gpio(arizona->dev->of_node, prop, 0);
  617. if (gpio < 0) {
  618. if (mandatory)
  619. dev_err(arizona->dev,
  620. "Mandatory DT gpio %s missing/malformed: %d\n",
  621. prop, gpio);
  622. gpio = 0;
  623. }
  624. return gpio;
  625. }
  626. EXPORT_SYMBOL_GPL(arizona_of_get_named_gpio);
  627. static int arizona_of_get_core_pdata(struct arizona *arizona)
  628. {
  629. struct arizona_pdata *pdata = &arizona->pdata;
  630. struct property *prop;
  631. const __be32 *cur;
  632. u32 val;
  633. int ret, i;
  634. int count = 0;
  635. pdata->reset = arizona_of_get_named_gpio(arizona, "wlf,reset", true);
  636. ret = of_property_read_u32_array(arizona->dev->of_node,
  637. "wlf,gpio-defaults",
  638. arizona->pdata.gpio_defaults,
  639. ARRAY_SIZE(arizona->pdata.gpio_defaults));
  640. if (ret >= 0) {
  641. /*
  642. * All values are literal except out of range values
  643. * which are chip default, translate into platform
  644. * data which uses 0 as chip default and out of range
  645. * as zero.
  646. */
  647. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  648. if (arizona->pdata.gpio_defaults[i] > 0xffff)
  649. arizona->pdata.gpio_defaults[i] = 0;
  650. else if (arizona->pdata.gpio_defaults[i] == 0)
  651. arizona->pdata.gpio_defaults[i] = 0x10000;
  652. }
  653. } else {
  654. dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n",
  655. ret);
  656. }
  657. of_property_for_each_u32(arizona->dev->of_node, "wlf,inmode", prop,
  658. cur, val) {
  659. if (count == ARRAY_SIZE(arizona->pdata.inmode))
  660. break;
  661. arizona->pdata.inmode[count] = val;
  662. count++;
  663. }
  664. count = 0;
  665. of_property_for_each_u32(arizona->dev->of_node, "wlf,dmic-ref", prop,
  666. cur, val) {
  667. if (count == ARRAY_SIZE(arizona->pdata.dmic_ref))
  668. break;
  669. arizona->pdata.dmic_ref[count] = val;
  670. count++;
  671. }
  672. return 0;
  673. }
  674. const struct of_device_id arizona_of_match[] = {
  675. { .compatible = "wlf,wm5102", .data = (void *)WM5102 },
  676. { .compatible = "wlf,wm5110", .data = (void *)WM5110 },
  677. { .compatible = "wlf,wm8280", .data = (void *)WM8280 },
  678. { .compatible = "wlf,wm8997", .data = (void *)WM8997 },
  679. {},
  680. };
  681. EXPORT_SYMBOL_GPL(arizona_of_match);
  682. #else
  683. static inline int arizona_of_get_core_pdata(struct arizona *arizona)
  684. {
  685. return 0;
  686. }
  687. #endif
  688. static const struct mfd_cell early_devs[] = {
  689. { .name = "arizona-ldo1" },
  690. };
  691. static const char *wm5102_supplies[] = {
  692. "MICVDD",
  693. "DBVDD2",
  694. "DBVDD3",
  695. "CPVDD",
  696. "SPKVDDL",
  697. "SPKVDDR",
  698. };
  699. static const struct mfd_cell wm5102_devs[] = {
  700. { .name = "arizona-micsupp" },
  701. {
  702. .name = "arizona-extcon",
  703. .parent_supplies = wm5102_supplies,
  704. .num_parent_supplies = 1, /* We only need MICVDD */
  705. },
  706. { .name = "arizona-gpio" },
  707. { .name = "arizona-haptics" },
  708. { .name = "arizona-pwm" },
  709. {
  710. .name = "wm5102-codec",
  711. .parent_supplies = wm5102_supplies,
  712. .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
  713. },
  714. };
  715. static const struct mfd_cell wm5110_devs[] = {
  716. { .name = "arizona-micsupp" },
  717. {
  718. .name = "arizona-extcon",
  719. .parent_supplies = wm5102_supplies,
  720. .num_parent_supplies = 1, /* We only need MICVDD */
  721. },
  722. { .name = "arizona-gpio" },
  723. { .name = "arizona-haptics" },
  724. { .name = "arizona-pwm" },
  725. {
  726. .name = "wm5110-codec",
  727. .parent_supplies = wm5102_supplies,
  728. .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
  729. },
  730. };
  731. static const char *wm8997_supplies[] = {
  732. "MICVDD",
  733. "DBVDD2",
  734. "CPVDD",
  735. "SPKVDD",
  736. };
  737. static const struct mfd_cell wm8997_devs[] = {
  738. { .name = "arizona-micsupp" },
  739. {
  740. .name = "arizona-extcon",
  741. .parent_supplies = wm8997_supplies,
  742. .num_parent_supplies = 1, /* We only need MICVDD */
  743. },
  744. { .name = "arizona-gpio" },
  745. { .name = "arizona-haptics" },
  746. { .name = "arizona-pwm" },
  747. {
  748. .name = "wm8997-codec",
  749. .parent_supplies = wm8997_supplies,
  750. .num_parent_supplies = ARRAY_SIZE(wm8997_supplies),
  751. },
  752. };
  753. int arizona_dev_init(struct arizona *arizona)
  754. {
  755. struct device *dev = arizona->dev;
  756. const char *type_name;
  757. unsigned int reg, val;
  758. int (*apply_patch)(struct arizona *) = NULL;
  759. int ret, i;
  760. dev_set_drvdata(arizona->dev, arizona);
  761. mutex_init(&arizona->clk_lock);
  762. if (dev_get_platdata(arizona->dev))
  763. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  764. sizeof(arizona->pdata));
  765. else
  766. arizona_of_get_core_pdata(arizona);
  767. regcache_cache_only(arizona->regmap, true);
  768. switch (arizona->type) {
  769. case WM5102:
  770. case WM5110:
  771. case WM8280:
  772. case WM8997:
  773. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  774. arizona->core_supplies[i].supply
  775. = wm5102_core_supplies[i];
  776. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  777. break;
  778. default:
  779. dev_err(arizona->dev, "Unknown device type %d\n",
  780. arizona->type);
  781. return -EINVAL;
  782. }
  783. /* Mark DCVDD as external, LDO1 driver will clear if internal */
  784. arizona->external_dcvdd = true;
  785. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  786. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  787. if (ret != 0) {
  788. dev_err(dev, "Failed to add early children: %d\n", ret);
  789. return ret;
  790. }
  791. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  792. arizona->core_supplies);
  793. if (ret != 0) {
  794. dev_err(dev, "Failed to request core supplies: %d\n",
  795. ret);
  796. goto err_early;
  797. }
  798. /**
  799. * Don't use devres here because the only device we have to get
  800. * against is the MFD device and DCVDD will likely be supplied by
  801. * one of its children. Meaning that the regulator will be
  802. * destroyed by the time devres calls regulator put.
  803. */
  804. arizona->dcvdd = regulator_get(arizona->dev, "DCVDD");
  805. if (IS_ERR(arizona->dcvdd)) {
  806. ret = PTR_ERR(arizona->dcvdd);
  807. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  808. goto err_early;
  809. }
  810. if (arizona->pdata.reset) {
  811. /* Start out with /RESET low to put the chip into reset */
  812. ret = devm_gpio_request_one(arizona->dev, arizona->pdata.reset,
  813. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  814. "arizona /RESET");
  815. if (ret != 0) {
  816. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  817. goto err_dcvdd;
  818. }
  819. }
  820. ret = regulator_bulk_enable(arizona->num_core_supplies,
  821. arizona->core_supplies);
  822. if (ret != 0) {
  823. dev_err(dev, "Failed to enable core supplies: %d\n",
  824. ret);
  825. goto err_dcvdd;
  826. }
  827. ret = regulator_enable(arizona->dcvdd);
  828. if (ret != 0) {
  829. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  830. goto err_enable;
  831. }
  832. arizona_disable_reset(arizona);
  833. regcache_cache_only(arizona->regmap, false);
  834. /* Verify that this is a chip we know about */
  835. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  836. if (ret != 0) {
  837. dev_err(dev, "Failed to read ID register: %d\n", ret);
  838. goto err_reset;
  839. }
  840. switch (reg) {
  841. case 0x5102:
  842. case 0x5110:
  843. case 0x8997:
  844. break;
  845. default:
  846. dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
  847. goto err_reset;
  848. }
  849. /* If we have a /RESET GPIO we'll already be reset */
  850. if (!arizona->pdata.reset) {
  851. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  852. if (ret != 0) {
  853. dev_err(dev, "Failed to reset device: %d\n", ret);
  854. goto err_reset;
  855. }
  856. msleep(1);
  857. }
  858. /* Ensure device startup is complete */
  859. switch (arizona->type) {
  860. case WM5102:
  861. ret = regmap_read(arizona->regmap,
  862. ARIZONA_WRITE_SEQUENCER_CTRL_3, &val);
  863. if (ret) {
  864. dev_err(dev,
  865. "Failed to check write sequencer state: %d\n",
  866. ret);
  867. } else if (val & 0x01) {
  868. ret = wm5102_clear_write_sequencer(arizona);
  869. if (ret)
  870. return ret;
  871. }
  872. break;
  873. default:
  874. break;
  875. }
  876. ret = arizona_wait_for_boot(arizona);
  877. if (ret) {
  878. dev_err(arizona->dev, "Device failed initial boot: %d\n", ret);
  879. goto err_reset;
  880. }
  881. /* Read the device ID information & do device specific stuff */
  882. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  883. if (ret != 0) {
  884. dev_err(dev, "Failed to read ID register: %d\n", ret);
  885. goto err_reset;
  886. }
  887. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  888. &arizona->rev);
  889. if (ret != 0) {
  890. dev_err(dev, "Failed to read revision register: %d\n", ret);
  891. goto err_reset;
  892. }
  893. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  894. switch (reg) {
  895. #ifdef CONFIG_MFD_WM5102
  896. case 0x5102:
  897. type_name = "WM5102";
  898. if (arizona->type != WM5102) {
  899. dev_err(arizona->dev, "WM5102 registered as %d\n",
  900. arizona->type);
  901. arizona->type = WM5102;
  902. }
  903. apply_patch = wm5102_patch;
  904. arizona->rev &= 0x7;
  905. break;
  906. #endif
  907. #ifdef CONFIG_MFD_WM5110
  908. case 0x5110:
  909. switch (arizona->type) {
  910. case WM5110:
  911. type_name = "WM5110";
  912. break;
  913. case WM8280:
  914. type_name = "WM8280";
  915. break;
  916. default:
  917. type_name = "WM5110";
  918. dev_err(arizona->dev, "WM5110 registered as %d\n",
  919. arizona->type);
  920. arizona->type = WM5110;
  921. break;
  922. }
  923. apply_patch = wm5110_patch;
  924. break;
  925. #endif
  926. #ifdef CONFIG_MFD_WM8997
  927. case 0x8997:
  928. type_name = "WM8997";
  929. if (arizona->type != WM8997) {
  930. dev_err(arizona->dev, "WM8997 registered as %d\n",
  931. arizona->type);
  932. arizona->type = WM8997;
  933. }
  934. apply_patch = wm8997_patch;
  935. break;
  936. #endif
  937. default:
  938. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  939. goto err_reset;
  940. }
  941. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  942. if (apply_patch) {
  943. ret = apply_patch(arizona);
  944. if (ret != 0) {
  945. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  946. ret);
  947. goto err_reset;
  948. }
  949. switch (arizona->type) {
  950. case WM5102:
  951. ret = wm5102_apply_hardware_patch(arizona);
  952. if (ret) {
  953. dev_err(arizona->dev,
  954. "Failed to apply hardware patch: %d\n",
  955. ret);
  956. goto err_reset;
  957. }
  958. break;
  959. case WM5110:
  960. case WM8280:
  961. ret = wm5110_apply_sleep_patch(arizona);
  962. if (ret) {
  963. dev_err(arizona->dev,
  964. "Failed to apply sleep patch: %d\n",
  965. ret);
  966. goto err_reset;
  967. }
  968. break;
  969. default:
  970. break;
  971. }
  972. }
  973. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  974. if (!arizona->pdata.gpio_defaults[i])
  975. continue;
  976. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  977. arizona->pdata.gpio_defaults[i]);
  978. }
  979. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  980. pm_runtime_use_autosuspend(arizona->dev);
  981. pm_runtime_enable(arizona->dev);
  982. /* Chip default */
  983. if (!arizona->pdata.clk32k_src)
  984. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  985. switch (arizona->pdata.clk32k_src) {
  986. case ARIZONA_32KZ_MCLK1:
  987. case ARIZONA_32KZ_MCLK2:
  988. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  989. ARIZONA_CLK_32K_SRC_MASK,
  990. arizona->pdata.clk32k_src - 1);
  991. arizona_clk32k_enable(arizona);
  992. break;
  993. case ARIZONA_32KZ_NONE:
  994. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  995. ARIZONA_CLK_32K_SRC_MASK, 2);
  996. break;
  997. default:
  998. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  999. arizona->pdata.clk32k_src);
  1000. ret = -EINVAL;
  1001. goto err_reset;
  1002. }
  1003. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  1004. if (!arizona->pdata.micbias[i].mV &&
  1005. !arizona->pdata.micbias[i].bypass)
  1006. continue;
  1007. /* Apply default for bypass mode */
  1008. if (!arizona->pdata.micbias[i].mV)
  1009. arizona->pdata.micbias[i].mV = 2800;
  1010. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  1011. val <<= ARIZONA_MICB1_LVL_SHIFT;
  1012. if (arizona->pdata.micbias[i].ext_cap)
  1013. val |= ARIZONA_MICB1_EXT_CAP;
  1014. if (arizona->pdata.micbias[i].discharge)
  1015. val |= ARIZONA_MICB1_DISCH;
  1016. if (arizona->pdata.micbias[i].soft_start)
  1017. val |= ARIZONA_MICB1_RATE;
  1018. if (arizona->pdata.micbias[i].bypass)
  1019. val |= ARIZONA_MICB1_BYPASS;
  1020. regmap_update_bits(arizona->regmap,
  1021. ARIZONA_MIC_BIAS_CTRL_1 + i,
  1022. ARIZONA_MICB1_LVL_MASK |
  1023. ARIZONA_MICB1_EXT_CAP |
  1024. ARIZONA_MICB1_DISCH |
  1025. ARIZONA_MICB1_BYPASS |
  1026. ARIZONA_MICB1_RATE, val);
  1027. }
  1028. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  1029. /* Default for both is 0 so noop with defaults */
  1030. val = arizona->pdata.dmic_ref[i]
  1031. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  1032. if (arizona->pdata.inmode[i] & ARIZONA_INMODE_DMIC)
  1033. val |= 1 << ARIZONA_IN1_MODE_SHIFT;
  1034. if (arizona->pdata.inmode[i] & ARIZONA_INMODE_SE)
  1035. val |= 1 << ARIZONA_IN1_SINGLE_ENDED_SHIFT;
  1036. regmap_update_bits(arizona->regmap,
  1037. ARIZONA_IN1L_CONTROL + (i * 8),
  1038. ARIZONA_IN1_DMIC_SUP_MASK |
  1039. ARIZONA_IN1_MODE_MASK |
  1040. ARIZONA_IN1_SINGLE_ENDED_MASK, val);
  1041. }
  1042. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  1043. /* Default is 0 so noop with defaults */
  1044. if (arizona->pdata.out_mono[i])
  1045. val = ARIZONA_OUT1_MONO;
  1046. else
  1047. val = 0;
  1048. regmap_update_bits(arizona->regmap,
  1049. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  1050. ARIZONA_OUT1_MONO, val);
  1051. }
  1052. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  1053. if (arizona->pdata.spk_mute[i])
  1054. regmap_update_bits(arizona->regmap,
  1055. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  1056. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  1057. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  1058. arizona->pdata.spk_mute[i]);
  1059. if (arizona->pdata.spk_fmt[i])
  1060. regmap_update_bits(arizona->regmap,
  1061. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  1062. ARIZONA_SPK1_FMT_MASK,
  1063. arizona->pdata.spk_fmt[i]);
  1064. }
  1065. /* Set up for interrupts */
  1066. ret = arizona_irq_init(arizona);
  1067. if (ret != 0)
  1068. goto err_reset;
  1069. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  1070. arizona_clkgen_err, arizona);
  1071. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  1072. arizona_overclocked, arizona);
  1073. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  1074. arizona_underclocked, arizona);
  1075. switch (arizona->type) {
  1076. case WM5102:
  1077. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  1078. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  1079. break;
  1080. case WM5110:
  1081. case WM8280:
  1082. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  1083. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  1084. break;
  1085. case WM8997:
  1086. ret = mfd_add_devices(arizona->dev, -1, wm8997_devs,
  1087. ARRAY_SIZE(wm8997_devs), NULL, 0, NULL);
  1088. break;
  1089. }
  1090. if (ret != 0) {
  1091. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  1092. goto err_irq;
  1093. }
  1094. #ifdef CONFIG_PM
  1095. regulator_disable(arizona->dcvdd);
  1096. #endif
  1097. return 0;
  1098. err_irq:
  1099. arizona_irq_exit(arizona);
  1100. err_reset:
  1101. arizona_enable_reset(arizona);
  1102. regulator_disable(arizona->dcvdd);
  1103. err_enable:
  1104. regulator_bulk_disable(arizona->num_core_supplies,
  1105. arizona->core_supplies);
  1106. err_dcvdd:
  1107. regulator_put(arizona->dcvdd);
  1108. err_early:
  1109. mfd_remove_devices(dev);
  1110. return ret;
  1111. }
  1112. EXPORT_SYMBOL_GPL(arizona_dev_init);
  1113. int arizona_dev_exit(struct arizona *arizona)
  1114. {
  1115. pm_runtime_disable(arizona->dev);
  1116. regulator_disable(arizona->dcvdd);
  1117. regulator_put(arizona->dcvdd);
  1118. mfd_remove_devices(arizona->dev);
  1119. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  1120. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  1121. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  1122. arizona_irq_exit(arizona);
  1123. arizona_enable_reset(arizona);
  1124. regulator_bulk_disable(arizona->num_core_supplies,
  1125. arizona->core_supplies);
  1126. return 0;
  1127. }
  1128. EXPORT_SYMBOL_GPL(arizona_dev_exit);