omap-iommu.h 5.6 KB

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  1. /*
  2. * omap iommu: main structures
  3. *
  4. * Copyright (C) 2008-2009 Nokia Corporation
  5. *
  6. * Written by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef _OMAP_IOMMU_H
  13. #define _OMAP_IOMMU_H
  14. struct iotlb_entry {
  15. u32 da;
  16. u32 pa;
  17. u32 pgsz, prsvd, valid;
  18. union {
  19. u16 ap;
  20. struct {
  21. u32 endian, elsz, mixed;
  22. };
  23. };
  24. };
  25. struct omap_iommu {
  26. const char *name;
  27. void __iomem *regbase;
  28. struct device *dev;
  29. struct iommu_domain *domain;
  30. struct dentry *debug_dir;
  31. spinlock_t iommu_lock; /* global for this whole object */
  32. /*
  33. * We don't change iopgd for a situation like pgd for a task,
  34. * but share it globally for each iommu.
  35. */
  36. u32 *iopgd;
  37. spinlock_t page_table_lock; /* protect iopgd */
  38. int nr_tlb_entries;
  39. void *ctx; /* iommu context: registres saved area */
  40. int has_bus_err_back;
  41. };
  42. struct cr_regs {
  43. union {
  44. struct {
  45. u16 cam_l;
  46. u16 cam_h;
  47. };
  48. u32 cam;
  49. };
  50. union {
  51. struct {
  52. u16 ram_l;
  53. u16 ram_h;
  54. };
  55. u32 ram;
  56. };
  57. };
  58. /**
  59. * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
  60. * @dev: iommu client device
  61. */
  62. static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
  63. {
  64. struct omap_iommu_arch_data *arch_data = dev->archdata.iommu;
  65. return arch_data->iommu_dev;
  66. }
  67. /*
  68. * MMU Register offsets
  69. */
  70. #define MMU_REVISION 0x00
  71. #define MMU_IRQSTATUS 0x18
  72. #define MMU_IRQENABLE 0x1c
  73. #define MMU_WALKING_ST 0x40
  74. #define MMU_CNTL 0x44
  75. #define MMU_FAULT_AD 0x48
  76. #define MMU_TTB 0x4c
  77. #define MMU_LOCK 0x50
  78. #define MMU_LD_TLB 0x54
  79. #define MMU_CAM 0x58
  80. #define MMU_RAM 0x5c
  81. #define MMU_GFLUSH 0x60
  82. #define MMU_FLUSH_ENTRY 0x64
  83. #define MMU_READ_CAM 0x68
  84. #define MMU_READ_RAM 0x6c
  85. #define MMU_EMU_FAULT_AD 0x70
  86. #define MMU_GP_REG 0x88
  87. #define MMU_REG_SIZE 256
  88. /*
  89. * MMU Register bit definitions
  90. */
  91. /* IRQSTATUS & IRQENABLE */
  92. #define MMU_IRQ_MULTIHITFAULT (1 << 4)
  93. #define MMU_IRQ_TABLEWALKFAULT (1 << 3)
  94. #define MMU_IRQ_EMUMISS (1 << 2)
  95. #define MMU_IRQ_TRANSLATIONFAULT (1 << 1)
  96. #define MMU_IRQ_TLBMISS (1 << 0)
  97. #define __MMU_IRQ_FAULT \
  98. (MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
  99. #define MMU_IRQ_MASK \
  100. (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
  101. #define MMU_IRQ_TWL_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
  102. #define MMU_IRQ_TLB_MISS_MASK (__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
  103. /* MMU_CNTL */
  104. #define MMU_CNTL_SHIFT 1
  105. #define MMU_CNTL_MASK (7 << MMU_CNTL_SHIFT)
  106. #define MMU_CNTL_EML_TLB (1 << 3)
  107. #define MMU_CNTL_TWL_EN (1 << 2)
  108. #define MMU_CNTL_MMU_EN (1 << 1)
  109. /* CAM */
  110. #define MMU_CAM_VATAG_SHIFT 12
  111. #define MMU_CAM_VATAG_MASK \
  112. ((~0UL >> MMU_CAM_VATAG_SHIFT) << MMU_CAM_VATAG_SHIFT)
  113. #define MMU_CAM_P (1 << 3)
  114. #define MMU_CAM_V (1 << 2)
  115. #define MMU_CAM_PGSZ_MASK 3
  116. #define MMU_CAM_PGSZ_1M (0 << 0)
  117. #define MMU_CAM_PGSZ_64K (1 << 0)
  118. #define MMU_CAM_PGSZ_4K (2 << 0)
  119. #define MMU_CAM_PGSZ_16M (3 << 0)
  120. /* RAM */
  121. #define MMU_RAM_PADDR_SHIFT 12
  122. #define MMU_RAM_PADDR_MASK \
  123. ((~0UL >> MMU_RAM_PADDR_SHIFT) << MMU_RAM_PADDR_SHIFT)
  124. #define MMU_RAM_ENDIAN_SHIFT 9
  125. #define MMU_RAM_ENDIAN_MASK (1 << MMU_RAM_ENDIAN_SHIFT)
  126. #define MMU_RAM_ENDIAN_LITTLE (0 << MMU_RAM_ENDIAN_SHIFT)
  127. #define MMU_RAM_ENDIAN_BIG (1 << MMU_RAM_ENDIAN_SHIFT)
  128. #define MMU_RAM_ELSZ_SHIFT 7
  129. #define MMU_RAM_ELSZ_MASK (3 << MMU_RAM_ELSZ_SHIFT)
  130. #define MMU_RAM_ELSZ_8 (0 << MMU_RAM_ELSZ_SHIFT)
  131. #define MMU_RAM_ELSZ_16 (1 << MMU_RAM_ELSZ_SHIFT)
  132. #define MMU_RAM_ELSZ_32 (2 << MMU_RAM_ELSZ_SHIFT)
  133. #define MMU_RAM_ELSZ_NONE (3 << MMU_RAM_ELSZ_SHIFT)
  134. #define MMU_RAM_MIXED_SHIFT 6
  135. #define MMU_RAM_MIXED_MASK (1 << MMU_RAM_MIXED_SHIFT)
  136. #define MMU_RAM_MIXED MMU_RAM_MIXED_MASK
  137. #define MMU_GP_REG_BUS_ERR_BACK_EN 0x1
  138. #define get_cam_va_mask(pgsz) \
  139. (((pgsz) == MMU_CAM_PGSZ_16M) ? 0xff000000 : \
  140. ((pgsz) == MMU_CAM_PGSZ_1M) ? 0xfff00000 : \
  141. ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
  142. ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
  143. /*
  144. * utilities for super page(16MB, 1MB, 64KB and 4KB)
  145. */
  146. #define iopgsz_max(bytes) \
  147. (((bytes) >= SZ_16M) ? SZ_16M : \
  148. ((bytes) >= SZ_1M) ? SZ_1M : \
  149. ((bytes) >= SZ_64K) ? SZ_64K : \
  150. ((bytes) >= SZ_4K) ? SZ_4K : 0)
  151. #define bytes_to_iopgsz(bytes) \
  152. (((bytes) == SZ_16M) ? MMU_CAM_PGSZ_16M : \
  153. ((bytes) == SZ_1M) ? MMU_CAM_PGSZ_1M : \
  154. ((bytes) == SZ_64K) ? MMU_CAM_PGSZ_64K : \
  155. ((bytes) == SZ_4K) ? MMU_CAM_PGSZ_4K : -1)
  156. #define iopgsz_to_bytes(iopgsz) \
  157. (((iopgsz) == MMU_CAM_PGSZ_16M) ? SZ_16M : \
  158. ((iopgsz) == MMU_CAM_PGSZ_1M) ? SZ_1M : \
  159. ((iopgsz) == MMU_CAM_PGSZ_64K) ? SZ_64K : \
  160. ((iopgsz) == MMU_CAM_PGSZ_4K) ? SZ_4K : 0)
  161. #define iopgsz_ok(bytes) (bytes_to_iopgsz(bytes) >= 0)
  162. /*
  163. * global functions
  164. */
  165. #ifdef CONFIG_OMAP_IOMMU_DEBUG
  166. extern ssize_t
  167. omap_iommu_dump_ctx(struct omap_iommu *obj, char *buf, ssize_t len);
  168. extern size_t
  169. omap_dump_tlb_entries(struct omap_iommu *obj, char *buf, ssize_t len);
  170. void omap_iommu_debugfs_init(void);
  171. void omap_iommu_debugfs_exit(void);
  172. void omap_iommu_debugfs_add(struct omap_iommu *obj);
  173. void omap_iommu_debugfs_remove(struct omap_iommu *obj);
  174. #else
  175. static inline void omap_iommu_debugfs_init(void) { }
  176. static inline void omap_iommu_debugfs_exit(void) { }
  177. static inline void omap_iommu_debugfs_add(struct omap_iommu *obj) { }
  178. static inline void omap_iommu_debugfs_remove(struct omap_iommu *obj) { }
  179. #endif
  180. /*
  181. * register accessors
  182. */
  183. static inline u32 iommu_read_reg(struct omap_iommu *obj, size_t offs)
  184. {
  185. return __raw_readl(obj->regbase + offs);
  186. }
  187. static inline void iommu_write_reg(struct omap_iommu *obj, u32 val, size_t offs)
  188. {
  189. __raw_writel(val, obj->regbase + offs);
  190. }
  191. #endif /* _OMAP_IOMMU_H */