qib_user_sdma.c 36 KB

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  1. /*
  2. * Copyright (c) 2007, 2008, 2009 QLogic Corporation. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/mm.h>
  33. #include <linux/types.h>
  34. #include <linux/device.h>
  35. #include <linux/dmapool.h>
  36. #include <linux/slab.h>
  37. #include <linux/list.h>
  38. #include <linux/highmem.h>
  39. #include <linux/io.h>
  40. #include <linux/uio.h>
  41. #include <linux/rbtree.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/delay.h>
  44. #include "qib.h"
  45. #include "qib_user_sdma.h"
  46. /* minimum size of header */
  47. #define QIB_USER_SDMA_MIN_HEADER_LENGTH 64
  48. /* expected size of headers (for dma_pool) */
  49. #define QIB_USER_SDMA_EXP_HEADER_LENGTH 64
  50. /* attempt to drain the queue for 5secs */
  51. #define QIB_USER_SDMA_DRAIN_TIMEOUT 250
  52. /*
  53. * track how many times a process open this driver.
  54. */
  55. static struct rb_root qib_user_sdma_rb_root = RB_ROOT;
  56. struct qib_user_sdma_rb_node {
  57. struct rb_node node;
  58. int refcount;
  59. pid_t pid;
  60. };
  61. struct qib_user_sdma_pkt {
  62. struct list_head list; /* list element */
  63. u8 tiddma; /* if this is NEW tid-sdma */
  64. u8 largepkt; /* this is large pkt from kmalloc */
  65. u16 frag_size; /* frag size used by PSM */
  66. u16 index; /* last header index or push index */
  67. u16 naddr; /* dimension of addr (1..3) ... */
  68. u16 addrlimit; /* addr array size */
  69. u16 tidsmidx; /* current tidsm index */
  70. u16 tidsmcount; /* tidsm array item count */
  71. u16 payload_size; /* payload size so far for header */
  72. u32 bytes_togo; /* bytes for processing */
  73. u32 counter; /* sdma pkts queued counter for this entry */
  74. struct qib_tid_session_member *tidsm; /* tid session member array */
  75. struct qib_user_sdma_queue *pq; /* which pq this pkt belongs to */
  76. u64 added; /* global descq number of entries */
  77. struct {
  78. u16 offset; /* offset for kvaddr, addr */
  79. u16 length; /* length in page */
  80. u16 first_desc; /* first desc */
  81. u16 last_desc; /* last desc */
  82. u16 put_page; /* should we put_page? */
  83. u16 dma_mapped; /* is page dma_mapped? */
  84. u16 dma_length; /* for dma_unmap_page() */
  85. u16 padding;
  86. struct page *page; /* may be NULL (coherent mem) */
  87. void *kvaddr; /* FIXME: only for pio hack */
  88. dma_addr_t addr;
  89. } addr[4]; /* max pages, any more and we coalesce */
  90. };
  91. struct qib_user_sdma_queue {
  92. /*
  93. * pkts sent to dma engine are queued on this
  94. * list head. the type of the elements of this
  95. * list are struct qib_user_sdma_pkt...
  96. */
  97. struct list_head sent;
  98. /*
  99. * Because above list will be accessed by both process and
  100. * signal handler, we need a spinlock for it.
  101. */
  102. spinlock_t sent_lock ____cacheline_aligned_in_smp;
  103. /* headers with expected length are allocated from here... */
  104. char header_cache_name[64];
  105. struct dma_pool *header_cache;
  106. /* packets are allocated from the slab cache... */
  107. char pkt_slab_name[64];
  108. struct kmem_cache *pkt_slab;
  109. /* as packets go on the queued queue, they are counted... */
  110. u32 counter;
  111. u32 sent_counter;
  112. /* pending packets, not sending yet */
  113. u32 num_pending;
  114. /* sending packets, not complete yet */
  115. u32 num_sending;
  116. /* global descq number of entry of last sending packet */
  117. u64 added;
  118. /* dma page table */
  119. struct rb_root dma_pages_root;
  120. struct qib_user_sdma_rb_node *sdma_rb_node;
  121. /* protect everything above... */
  122. struct mutex lock;
  123. };
  124. static struct qib_user_sdma_rb_node *
  125. qib_user_sdma_rb_search(struct rb_root *root, pid_t pid)
  126. {
  127. struct qib_user_sdma_rb_node *sdma_rb_node;
  128. struct rb_node *node = root->rb_node;
  129. while (node) {
  130. sdma_rb_node = container_of(node,
  131. struct qib_user_sdma_rb_node, node);
  132. if (pid < sdma_rb_node->pid)
  133. node = node->rb_left;
  134. else if (pid > sdma_rb_node->pid)
  135. node = node->rb_right;
  136. else
  137. return sdma_rb_node;
  138. }
  139. return NULL;
  140. }
  141. static int
  142. qib_user_sdma_rb_insert(struct rb_root *root, struct qib_user_sdma_rb_node *new)
  143. {
  144. struct rb_node **node = &(root->rb_node);
  145. struct rb_node *parent = NULL;
  146. struct qib_user_sdma_rb_node *got;
  147. while (*node) {
  148. got = container_of(*node, struct qib_user_sdma_rb_node, node);
  149. parent = *node;
  150. if (new->pid < got->pid)
  151. node = &((*node)->rb_left);
  152. else if (new->pid > got->pid)
  153. node = &((*node)->rb_right);
  154. else
  155. return 0;
  156. }
  157. rb_link_node(&new->node, parent, node);
  158. rb_insert_color(&new->node, root);
  159. return 1;
  160. }
  161. struct qib_user_sdma_queue *
  162. qib_user_sdma_queue_create(struct device *dev, int unit, int ctxt, int sctxt)
  163. {
  164. struct qib_user_sdma_queue *pq =
  165. kmalloc(sizeof(struct qib_user_sdma_queue), GFP_KERNEL);
  166. struct qib_user_sdma_rb_node *sdma_rb_node;
  167. if (!pq)
  168. goto done;
  169. pq->counter = 0;
  170. pq->sent_counter = 0;
  171. pq->num_pending = 0;
  172. pq->num_sending = 0;
  173. pq->added = 0;
  174. pq->sdma_rb_node = NULL;
  175. INIT_LIST_HEAD(&pq->sent);
  176. spin_lock_init(&pq->sent_lock);
  177. mutex_init(&pq->lock);
  178. snprintf(pq->pkt_slab_name, sizeof(pq->pkt_slab_name),
  179. "qib-user-sdma-pkts-%u-%02u.%02u", unit, ctxt, sctxt);
  180. pq->pkt_slab = kmem_cache_create(pq->pkt_slab_name,
  181. sizeof(struct qib_user_sdma_pkt),
  182. 0, 0, NULL);
  183. if (!pq->pkt_slab)
  184. goto err_kfree;
  185. snprintf(pq->header_cache_name, sizeof(pq->header_cache_name),
  186. "qib-user-sdma-headers-%u-%02u.%02u", unit, ctxt, sctxt);
  187. pq->header_cache = dma_pool_create(pq->header_cache_name,
  188. dev,
  189. QIB_USER_SDMA_EXP_HEADER_LENGTH,
  190. 4, 0);
  191. if (!pq->header_cache)
  192. goto err_slab;
  193. pq->dma_pages_root = RB_ROOT;
  194. sdma_rb_node = qib_user_sdma_rb_search(&qib_user_sdma_rb_root,
  195. current->pid);
  196. if (sdma_rb_node) {
  197. sdma_rb_node->refcount++;
  198. } else {
  199. int ret;
  200. sdma_rb_node = kmalloc(sizeof(
  201. struct qib_user_sdma_rb_node), GFP_KERNEL);
  202. if (!sdma_rb_node)
  203. goto err_rb;
  204. sdma_rb_node->refcount = 1;
  205. sdma_rb_node->pid = current->pid;
  206. ret = qib_user_sdma_rb_insert(&qib_user_sdma_rb_root,
  207. sdma_rb_node);
  208. BUG_ON(ret == 0);
  209. }
  210. pq->sdma_rb_node = sdma_rb_node;
  211. goto done;
  212. err_rb:
  213. dma_pool_destroy(pq->header_cache);
  214. err_slab:
  215. kmem_cache_destroy(pq->pkt_slab);
  216. err_kfree:
  217. kfree(pq);
  218. pq = NULL;
  219. done:
  220. return pq;
  221. }
  222. static void qib_user_sdma_init_frag(struct qib_user_sdma_pkt *pkt,
  223. int i, u16 offset, u16 len,
  224. u16 first_desc, u16 last_desc,
  225. u16 put_page, u16 dma_mapped,
  226. struct page *page, void *kvaddr,
  227. dma_addr_t dma_addr, u16 dma_length)
  228. {
  229. pkt->addr[i].offset = offset;
  230. pkt->addr[i].length = len;
  231. pkt->addr[i].first_desc = first_desc;
  232. pkt->addr[i].last_desc = last_desc;
  233. pkt->addr[i].put_page = put_page;
  234. pkt->addr[i].dma_mapped = dma_mapped;
  235. pkt->addr[i].page = page;
  236. pkt->addr[i].kvaddr = kvaddr;
  237. pkt->addr[i].addr = dma_addr;
  238. pkt->addr[i].dma_length = dma_length;
  239. }
  240. static void *qib_user_sdma_alloc_header(struct qib_user_sdma_queue *pq,
  241. size_t len, dma_addr_t *dma_addr)
  242. {
  243. void *hdr;
  244. if (len == QIB_USER_SDMA_EXP_HEADER_LENGTH)
  245. hdr = dma_pool_alloc(pq->header_cache, GFP_KERNEL,
  246. dma_addr);
  247. else
  248. hdr = NULL;
  249. if (!hdr) {
  250. hdr = kmalloc(len, GFP_KERNEL);
  251. if (!hdr)
  252. return NULL;
  253. *dma_addr = 0;
  254. }
  255. return hdr;
  256. }
  257. static int qib_user_sdma_page_to_frags(const struct qib_devdata *dd,
  258. struct qib_user_sdma_queue *pq,
  259. struct qib_user_sdma_pkt *pkt,
  260. struct page *page, u16 put,
  261. u16 offset, u16 len, void *kvaddr)
  262. {
  263. __le16 *pbc16;
  264. void *pbcvaddr;
  265. struct qib_message_header *hdr;
  266. u16 newlen, pbclen, lastdesc, dma_mapped;
  267. u32 vcto;
  268. union qib_seqnum seqnum;
  269. dma_addr_t pbcdaddr;
  270. dma_addr_t dma_addr =
  271. dma_map_page(&dd->pcidev->dev,
  272. page, offset, len, DMA_TO_DEVICE);
  273. int ret = 0;
  274. if (dma_mapping_error(&dd->pcidev->dev, dma_addr)) {
  275. /*
  276. * dma mapping error, pkt has not managed
  277. * this page yet, return the page here so
  278. * the caller can ignore this page.
  279. */
  280. if (put) {
  281. put_page(page);
  282. } else {
  283. /* coalesce case */
  284. kunmap(page);
  285. __free_page(page);
  286. }
  287. ret = -ENOMEM;
  288. goto done;
  289. }
  290. offset = 0;
  291. dma_mapped = 1;
  292. next_fragment:
  293. /*
  294. * In tid-sdma, the transfer length is restricted by
  295. * receiver side current tid page length.
  296. */
  297. if (pkt->tiddma && len > pkt->tidsm[pkt->tidsmidx].length)
  298. newlen = pkt->tidsm[pkt->tidsmidx].length;
  299. else
  300. newlen = len;
  301. /*
  302. * Then the transfer length is restricted by MTU.
  303. * the last descriptor flag is determined by:
  304. * 1. the current packet is at frag size length.
  305. * 2. the current tid page is done if tid-sdma.
  306. * 3. there is no more byte togo if sdma.
  307. */
  308. lastdesc = 0;
  309. if ((pkt->payload_size + newlen) >= pkt->frag_size) {
  310. newlen = pkt->frag_size - pkt->payload_size;
  311. lastdesc = 1;
  312. } else if (pkt->tiddma) {
  313. if (newlen == pkt->tidsm[pkt->tidsmidx].length)
  314. lastdesc = 1;
  315. } else {
  316. if (newlen == pkt->bytes_togo)
  317. lastdesc = 1;
  318. }
  319. /* fill the next fragment in this page */
  320. qib_user_sdma_init_frag(pkt, pkt->naddr, /* index */
  321. offset, newlen, /* offset, len */
  322. 0, lastdesc, /* first last desc */
  323. put, dma_mapped, /* put page, dma mapped */
  324. page, kvaddr, /* struct page, virt addr */
  325. dma_addr, len); /* dma addr, dma length */
  326. pkt->bytes_togo -= newlen;
  327. pkt->payload_size += newlen;
  328. pkt->naddr++;
  329. if (pkt->naddr == pkt->addrlimit) {
  330. ret = -EFAULT;
  331. goto done;
  332. }
  333. /* If there is no more byte togo. (lastdesc==1) */
  334. if (pkt->bytes_togo == 0) {
  335. /* The packet is done, header is not dma mapped yet.
  336. * it should be from kmalloc */
  337. if (!pkt->addr[pkt->index].addr) {
  338. pkt->addr[pkt->index].addr =
  339. dma_map_single(&dd->pcidev->dev,
  340. pkt->addr[pkt->index].kvaddr,
  341. pkt->addr[pkt->index].dma_length,
  342. DMA_TO_DEVICE);
  343. if (dma_mapping_error(&dd->pcidev->dev,
  344. pkt->addr[pkt->index].addr)) {
  345. ret = -ENOMEM;
  346. goto done;
  347. }
  348. pkt->addr[pkt->index].dma_mapped = 1;
  349. }
  350. goto done;
  351. }
  352. /* If tid-sdma, advance tid info. */
  353. if (pkt->tiddma) {
  354. pkt->tidsm[pkt->tidsmidx].length -= newlen;
  355. if (pkt->tidsm[pkt->tidsmidx].length) {
  356. pkt->tidsm[pkt->tidsmidx].offset += newlen;
  357. } else {
  358. pkt->tidsmidx++;
  359. if (pkt->tidsmidx == pkt->tidsmcount) {
  360. ret = -EFAULT;
  361. goto done;
  362. }
  363. }
  364. }
  365. /*
  366. * If this is NOT the last descriptor. (newlen==len)
  367. * the current packet is not done yet, but the current
  368. * send side page is done.
  369. */
  370. if (lastdesc == 0)
  371. goto done;
  372. /*
  373. * If running this driver under PSM with message size
  374. * fitting into one transfer unit, it is not possible
  375. * to pass this line. otherwise, it is a buggggg.
  376. */
  377. /*
  378. * Since the current packet is done, and there are more
  379. * bytes togo, we need to create a new sdma header, copying
  380. * from previous sdma header and modify both.
  381. */
  382. pbclen = pkt->addr[pkt->index].length;
  383. pbcvaddr = qib_user_sdma_alloc_header(pq, pbclen, &pbcdaddr);
  384. if (!pbcvaddr) {
  385. ret = -ENOMEM;
  386. goto done;
  387. }
  388. /* Copy the previous sdma header to new sdma header */
  389. pbc16 = (__le16 *)pkt->addr[pkt->index].kvaddr;
  390. memcpy(pbcvaddr, pbc16, pbclen);
  391. /* Modify the previous sdma header */
  392. hdr = (struct qib_message_header *)&pbc16[4];
  393. /* New pbc length */
  394. pbc16[0] = cpu_to_le16(le16_to_cpu(pbc16[0])-(pkt->bytes_togo>>2));
  395. /* New packet length */
  396. hdr->lrh[2] = cpu_to_be16(le16_to_cpu(pbc16[0]));
  397. if (pkt->tiddma) {
  398. /* turn on the header suppression */
  399. hdr->iph.pkt_flags =
  400. cpu_to_le16(le16_to_cpu(hdr->iph.pkt_flags)|0x2);
  401. /* turn off ACK_REQ: 0x04 and EXPECTED_DONE: 0x20 */
  402. hdr->flags &= ~(0x04|0x20);
  403. } else {
  404. /* turn off extra bytes: 20-21 bits */
  405. hdr->bth[0] = cpu_to_be32(be32_to_cpu(hdr->bth[0])&0xFFCFFFFF);
  406. /* turn off ACK_REQ: 0x04 */
  407. hdr->flags &= ~(0x04);
  408. }
  409. /* New kdeth checksum */
  410. vcto = le32_to_cpu(hdr->iph.ver_ctxt_tid_offset);
  411. hdr->iph.chksum = cpu_to_le16(QIB_LRH_BTH +
  412. be16_to_cpu(hdr->lrh[2]) -
  413. ((vcto>>16)&0xFFFF) - (vcto&0xFFFF) -
  414. le16_to_cpu(hdr->iph.pkt_flags));
  415. /* The packet is done, header is not dma mapped yet.
  416. * it should be from kmalloc */
  417. if (!pkt->addr[pkt->index].addr) {
  418. pkt->addr[pkt->index].addr =
  419. dma_map_single(&dd->pcidev->dev,
  420. pkt->addr[pkt->index].kvaddr,
  421. pkt->addr[pkt->index].dma_length,
  422. DMA_TO_DEVICE);
  423. if (dma_mapping_error(&dd->pcidev->dev,
  424. pkt->addr[pkt->index].addr)) {
  425. ret = -ENOMEM;
  426. goto done;
  427. }
  428. pkt->addr[pkt->index].dma_mapped = 1;
  429. }
  430. /* Modify the new sdma header */
  431. pbc16 = (__le16 *)pbcvaddr;
  432. hdr = (struct qib_message_header *)&pbc16[4];
  433. /* New pbc length */
  434. pbc16[0] = cpu_to_le16(le16_to_cpu(pbc16[0])-(pkt->payload_size>>2));
  435. /* New packet length */
  436. hdr->lrh[2] = cpu_to_be16(le16_to_cpu(pbc16[0]));
  437. if (pkt->tiddma) {
  438. /* Set new tid and offset for new sdma header */
  439. hdr->iph.ver_ctxt_tid_offset = cpu_to_le32(
  440. (le32_to_cpu(hdr->iph.ver_ctxt_tid_offset)&0xFF000000) +
  441. (pkt->tidsm[pkt->tidsmidx].tid<<QLOGIC_IB_I_TID_SHIFT) +
  442. (pkt->tidsm[pkt->tidsmidx].offset>>2));
  443. } else {
  444. /* Middle protocol new packet offset */
  445. hdr->uwords[2] += pkt->payload_size;
  446. }
  447. /* New kdeth checksum */
  448. vcto = le32_to_cpu(hdr->iph.ver_ctxt_tid_offset);
  449. hdr->iph.chksum = cpu_to_le16(QIB_LRH_BTH +
  450. be16_to_cpu(hdr->lrh[2]) -
  451. ((vcto>>16)&0xFFFF) - (vcto&0xFFFF) -
  452. le16_to_cpu(hdr->iph.pkt_flags));
  453. /* Next sequence number in new sdma header */
  454. seqnum.val = be32_to_cpu(hdr->bth[2]);
  455. if (pkt->tiddma)
  456. seqnum.seq++;
  457. else
  458. seqnum.pkt++;
  459. hdr->bth[2] = cpu_to_be32(seqnum.val);
  460. /* Init new sdma header. */
  461. qib_user_sdma_init_frag(pkt, pkt->naddr, /* index */
  462. 0, pbclen, /* offset, len */
  463. 1, 0, /* first last desc */
  464. 0, 0, /* put page, dma mapped */
  465. NULL, pbcvaddr, /* struct page, virt addr */
  466. pbcdaddr, pbclen); /* dma addr, dma length */
  467. pkt->index = pkt->naddr;
  468. pkt->payload_size = 0;
  469. pkt->naddr++;
  470. if (pkt->naddr == pkt->addrlimit) {
  471. ret = -EFAULT;
  472. goto done;
  473. }
  474. /* Prepare for next fragment in this page */
  475. if (newlen != len) {
  476. if (dma_mapped) {
  477. put = 0;
  478. dma_mapped = 0;
  479. page = NULL;
  480. kvaddr = NULL;
  481. }
  482. len -= newlen;
  483. offset += newlen;
  484. goto next_fragment;
  485. }
  486. done:
  487. return ret;
  488. }
  489. /* we've too many pages in the iovec, coalesce to a single page */
  490. static int qib_user_sdma_coalesce(const struct qib_devdata *dd,
  491. struct qib_user_sdma_queue *pq,
  492. struct qib_user_sdma_pkt *pkt,
  493. const struct iovec *iov,
  494. unsigned long niov)
  495. {
  496. int ret = 0;
  497. struct page *page = alloc_page(GFP_KERNEL);
  498. void *mpage_save;
  499. char *mpage;
  500. int i;
  501. int len = 0;
  502. if (!page) {
  503. ret = -ENOMEM;
  504. goto done;
  505. }
  506. mpage = kmap(page);
  507. mpage_save = mpage;
  508. for (i = 0; i < niov; i++) {
  509. int cfur;
  510. cfur = copy_from_user(mpage,
  511. iov[i].iov_base, iov[i].iov_len);
  512. if (cfur) {
  513. ret = -EFAULT;
  514. goto free_unmap;
  515. }
  516. mpage += iov[i].iov_len;
  517. len += iov[i].iov_len;
  518. }
  519. ret = qib_user_sdma_page_to_frags(dd, pq, pkt,
  520. page, 0, 0, len, mpage_save);
  521. goto done;
  522. free_unmap:
  523. kunmap(page);
  524. __free_page(page);
  525. done:
  526. return ret;
  527. }
  528. /*
  529. * How many pages in this iovec element?
  530. */
  531. static int qib_user_sdma_num_pages(const struct iovec *iov)
  532. {
  533. const unsigned long addr = (unsigned long) iov->iov_base;
  534. const unsigned long len = iov->iov_len;
  535. const unsigned long spage = addr & PAGE_MASK;
  536. const unsigned long epage = (addr + len - 1) & PAGE_MASK;
  537. return 1 + ((epage - spage) >> PAGE_SHIFT);
  538. }
  539. static void qib_user_sdma_free_pkt_frag(struct device *dev,
  540. struct qib_user_sdma_queue *pq,
  541. struct qib_user_sdma_pkt *pkt,
  542. int frag)
  543. {
  544. const int i = frag;
  545. if (pkt->addr[i].page) {
  546. /* only user data has page */
  547. if (pkt->addr[i].dma_mapped)
  548. dma_unmap_page(dev,
  549. pkt->addr[i].addr,
  550. pkt->addr[i].dma_length,
  551. DMA_TO_DEVICE);
  552. if (pkt->addr[i].kvaddr)
  553. kunmap(pkt->addr[i].page);
  554. if (pkt->addr[i].put_page)
  555. put_page(pkt->addr[i].page);
  556. else
  557. __free_page(pkt->addr[i].page);
  558. } else if (pkt->addr[i].kvaddr) {
  559. /* for headers */
  560. if (pkt->addr[i].dma_mapped) {
  561. /* from kmalloc & dma mapped */
  562. dma_unmap_single(dev,
  563. pkt->addr[i].addr,
  564. pkt->addr[i].dma_length,
  565. DMA_TO_DEVICE);
  566. kfree(pkt->addr[i].kvaddr);
  567. } else if (pkt->addr[i].addr) {
  568. /* free coherent mem from cache... */
  569. dma_pool_free(pq->header_cache,
  570. pkt->addr[i].kvaddr, pkt->addr[i].addr);
  571. } else {
  572. /* from kmalloc but not dma mapped */
  573. kfree(pkt->addr[i].kvaddr);
  574. }
  575. }
  576. }
  577. /* return number of pages pinned... */
  578. static int qib_user_sdma_pin_pages(const struct qib_devdata *dd,
  579. struct qib_user_sdma_queue *pq,
  580. struct qib_user_sdma_pkt *pkt,
  581. unsigned long addr, int tlen, int npages)
  582. {
  583. struct page *pages[8];
  584. int i, j;
  585. int ret = 0;
  586. while (npages) {
  587. if (npages > 8)
  588. j = 8;
  589. else
  590. j = npages;
  591. ret = get_user_pages_fast(addr, j, 0, pages);
  592. if (ret != j) {
  593. i = 0;
  594. j = ret;
  595. ret = -ENOMEM;
  596. goto free_pages;
  597. }
  598. for (i = 0; i < j; i++) {
  599. /* map the pages... */
  600. unsigned long fofs = addr & ~PAGE_MASK;
  601. int flen = ((fofs + tlen) > PAGE_SIZE) ?
  602. (PAGE_SIZE - fofs) : tlen;
  603. ret = qib_user_sdma_page_to_frags(dd, pq, pkt,
  604. pages[i], 1, fofs, flen, NULL);
  605. if (ret < 0) {
  606. /* current page has beed taken
  607. * care of inside above call.
  608. */
  609. i++;
  610. goto free_pages;
  611. }
  612. addr += flen;
  613. tlen -= flen;
  614. }
  615. npages -= j;
  616. }
  617. goto done;
  618. /* if error, return all pages not managed by pkt */
  619. free_pages:
  620. while (i < j)
  621. put_page(pages[i++]);
  622. done:
  623. return ret;
  624. }
  625. static int qib_user_sdma_pin_pkt(const struct qib_devdata *dd,
  626. struct qib_user_sdma_queue *pq,
  627. struct qib_user_sdma_pkt *pkt,
  628. const struct iovec *iov,
  629. unsigned long niov)
  630. {
  631. int ret = 0;
  632. unsigned long idx;
  633. for (idx = 0; idx < niov; idx++) {
  634. const int npages = qib_user_sdma_num_pages(iov + idx);
  635. const unsigned long addr = (unsigned long) iov[idx].iov_base;
  636. ret = qib_user_sdma_pin_pages(dd, pq, pkt, addr,
  637. iov[idx].iov_len, npages);
  638. if (ret < 0)
  639. goto free_pkt;
  640. }
  641. goto done;
  642. free_pkt:
  643. /* we need to ignore the first entry here */
  644. for (idx = 1; idx < pkt->naddr; idx++)
  645. qib_user_sdma_free_pkt_frag(&dd->pcidev->dev, pq, pkt, idx);
  646. /* need to dma unmap the first entry, this is to restore to
  647. * the original state so that caller can free the memory in
  648. * error condition. Caller does not know if dma mapped or not*/
  649. if (pkt->addr[0].dma_mapped) {
  650. dma_unmap_single(&dd->pcidev->dev,
  651. pkt->addr[0].addr,
  652. pkt->addr[0].dma_length,
  653. DMA_TO_DEVICE);
  654. pkt->addr[0].addr = 0;
  655. pkt->addr[0].dma_mapped = 0;
  656. }
  657. done:
  658. return ret;
  659. }
  660. static int qib_user_sdma_init_payload(const struct qib_devdata *dd,
  661. struct qib_user_sdma_queue *pq,
  662. struct qib_user_sdma_pkt *pkt,
  663. const struct iovec *iov,
  664. unsigned long niov, int npages)
  665. {
  666. int ret = 0;
  667. if (pkt->frag_size == pkt->bytes_togo &&
  668. npages >= ARRAY_SIZE(pkt->addr))
  669. ret = qib_user_sdma_coalesce(dd, pq, pkt, iov, niov);
  670. else
  671. ret = qib_user_sdma_pin_pkt(dd, pq, pkt, iov, niov);
  672. return ret;
  673. }
  674. /* free a packet list -- return counter value of last packet */
  675. static void qib_user_sdma_free_pkt_list(struct device *dev,
  676. struct qib_user_sdma_queue *pq,
  677. struct list_head *list)
  678. {
  679. struct qib_user_sdma_pkt *pkt, *pkt_next;
  680. list_for_each_entry_safe(pkt, pkt_next, list, list) {
  681. int i;
  682. for (i = 0; i < pkt->naddr; i++)
  683. qib_user_sdma_free_pkt_frag(dev, pq, pkt, i);
  684. if (pkt->largepkt)
  685. kfree(pkt);
  686. else
  687. kmem_cache_free(pq->pkt_slab, pkt);
  688. }
  689. INIT_LIST_HEAD(list);
  690. }
  691. /*
  692. * copy headers, coalesce etc -- pq->lock must be held
  693. *
  694. * we queue all the packets to list, returning the
  695. * number of bytes total. list must be empty initially,
  696. * as, if there is an error we clean it...
  697. */
  698. static int qib_user_sdma_queue_pkts(const struct qib_devdata *dd,
  699. struct qib_pportdata *ppd,
  700. struct qib_user_sdma_queue *pq,
  701. const struct iovec *iov,
  702. unsigned long niov,
  703. struct list_head *list,
  704. int *maxpkts, int *ndesc)
  705. {
  706. unsigned long idx = 0;
  707. int ret = 0;
  708. int npkts = 0;
  709. __le32 *pbc;
  710. dma_addr_t dma_addr;
  711. struct qib_user_sdma_pkt *pkt = NULL;
  712. size_t len;
  713. size_t nw;
  714. u32 counter = pq->counter;
  715. u16 frag_size;
  716. while (idx < niov && npkts < *maxpkts) {
  717. const unsigned long addr = (unsigned long) iov[idx].iov_base;
  718. const unsigned long idx_save = idx;
  719. unsigned pktnw;
  720. unsigned pktnwc;
  721. int nfrags = 0;
  722. int npages = 0;
  723. int bytes_togo = 0;
  724. int tiddma = 0;
  725. int cfur;
  726. len = iov[idx].iov_len;
  727. nw = len >> 2;
  728. if (len < QIB_USER_SDMA_MIN_HEADER_LENGTH ||
  729. len > PAGE_SIZE || len & 3 || addr & 3) {
  730. ret = -EINVAL;
  731. goto free_list;
  732. }
  733. pbc = qib_user_sdma_alloc_header(pq, len, &dma_addr);
  734. if (!pbc) {
  735. ret = -ENOMEM;
  736. goto free_list;
  737. }
  738. cfur = copy_from_user(pbc, iov[idx].iov_base, len);
  739. if (cfur) {
  740. ret = -EFAULT;
  741. goto free_pbc;
  742. }
  743. /*
  744. * This assignment is a bit strange. it's because the
  745. * the pbc counts the number of 32 bit words in the full
  746. * packet _except_ the first word of the pbc itself...
  747. */
  748. pktnwc = nw - 1;
  749. /*
  750. * pktnw computation yields the number of 32 bit words
  751. * that the caller has indicated in the PBC. note that
  752. * this is one less than the total number of words that
  753. * goes to the send DMA engine as the first 32 bit word
  754. * of the PBC itself is not counted. Armed with this count,
  755. * we can verify that the packet is consistent with the
  756. * iovec lengths.
  757. */
  758. pktnw = le32_to_cpu(*pbc) & 0xFFFF;
  759. if (pktnw < pktnwc) {
  760. ret = -EINVAL;
  761. goto free_pbc;
  762. }
  763. idx++;
  764. while (pktnwc < pktnw && idx < niov) {
  765. const size_t slen = iov[idx].iov_len;
  766. const unsigned long faddr =
  767. (unsigned long) iov[idx].iov_base;
  768. if (slen & 3 || faddr & 3 || !slen) {
  769. ret = -EINVAL;
  770. goto free_pbc;
  771. }
  772. npages += qib_user_sdma_num_pages(&iov[idx]);
  773. bytes_togo += slen;
  774. pktnwc += slen >> 2;
  775. idx++;
  776. nfrags++;
  777. }
  778. if (pktnwc != pktnw) {
  779. ret = -EINVAL;
  780. goto free_pbc;
  781. }
  782. frag_size = ((le32_to_cpu(*pbc))>>16) & 0xFFFF;
  783. if (((frag_size ? frag_size : bytes_togo) + len) >
  784. ppd->ibmaxlen) {
  785. ret = -EINVAL;
  786. goto free_pbc;
  787. }
  788. if (frag_size) {
  789. int pktsize, tidsmsize, n;
  790. n = npages*((2*PAGE_SIZE/frag_size)+1);
  791. pktsize = sizeof(*pkt) + sizeof(pkt->addr[0])*n;
  792. /*
  793. * Determine if this is tid-sdma or just sdma.
  794. */
  795. tiddma = (((le32_to_cpu(pbc[7])>>
  796. QLOGIC_IB_I_TID_SHIFT)&
  797. QLOGIC_IB_I_TID_MASK) !=
  798. QLOGIC_IB_I_TID_MASK);
  799. if (tiddma)
  800. tidsmsize = iov[idx].iov_len;
  801. else
  802. tidsmsize = 0;
  803. pkt = kmalloc(pktsize+tidsmsize, GFP_KERNEL);
  804. if (!pkt) {
  805. ret = -ENOMEM;
  806. goto free_pbc;
  807. }
  808. pkt->largepkt = 1;
  809. pkt->frag_size = frag_size;
  810. pkt->addrlimit = n + ARRAY_SIZE(pkt->addr);
  811. if (tiddma) {
  812. char *tidsm = (char *)pkt + pktsize;
  813. cfur = copy_from_user(tidsm,
  814. iov[idx].iov_base, tidsmsize);
  815. if (cfur) {
  816. ret = -EFAULT;
  817. goto free_pkt;
  818. }
  819. pkt->tidsm =
  820. (struct qib_tid_session_member *)tidsm;
  821. pkt->tidsmcount = tidsmsize/
  822. sizeof(struct qib_tid_session_member);
  823. pkt->tidsmidx = 0;
  824. idx++;
  825. }
  826. /*
  827. * pbc 'fill1' field is borrowed to pass frag size,
  828. * we need to clear it after picking frag size, the
  829. * hardware requires this field to be zero.
  830. */
  831. *pbc = cpu_to_le32(le32_to_cpu(*pbc) & 0x0000FFFF);
  832. } else {
  833. pkt = kmem_cache_alloc(pq->pkt_slab, GFP_KERNEL);
  834. if (!pkt) {
  835. ret = -ENOMEM;
  836. goto free_pbc;
  837. }
  838. pkt->largepkt = 0;
  839. pkt->frag_size = bytes_togo;
  840. pkt->addrlimit = ARRAY_SIZE(pkt->addr);
  841. }
  842. pkt->bytes_togo = bytes_togo;
  843. pkt->payload_size = 0;
  844. pkt->counter = counter;
  845. pkt->tiddma = tiddma;
  846. /* setup the first header */
  847. qib_user_sdma_init_frag(pkt, 0, /* index */
  848. 0, len, /* offset, len */
  849. 1, 0, /* first last desc */
  850. 0, 0, /* put page, dma mapped */
  851. NULL, pbc, /* struct page, virt addr */
  852. dma_addr, len); /* dma addr, dma length */
  853. pkt->index = 0;
  854. pkt->naddr = 1;
  855. if (nfrags) {
  856. ret = qib_user_sdma_init_payload(dd, pq, pkt,
  857. iov + idx_save + 1,
  858. nfrags, npages);
  859. if (ret < 0)
  860. goto free_pkt;
  861. } else {
  862. /* since there is no payload, mark the
  863. * header as the last desc. */
  864. pkt->addr[0].last_desc = 1;
  865. if (dma_addr == 0) {
  866. /*
  867. * the header is not dma mapped yet.
  868. * it should be from kmalloc.
  869. */
  870. dma_addr = dma_map_single(&dd->pcidev->dev,
  871. pbc, len, DMA_TO_DEVICE);
  872. if (dma_mapping_error(&dd->pcidev->dev,
  873. dma_addr)) {
  874. ret = -ENOMEM;
  875. goto free_pkt;
  876. }
  877. pkt->addr[0].addr = dma_addr;
  878. pkt->addr[0].dma_mapped = 1;
  879. }
  880. }
  881. counter++;
  882. npkts++;
  883. pkt->pq = pq;
  884. pkt->index = 0; /* reset index for push on hw */
  885. *ndesc += pkt->naddr;
  886. list_add_tail(&pkt->list, list);
  887. }
  888. *maxpkts = npkts;
  889. ret = idx;
  890. goto done;
  891. free_pkt:
  892. if (pkt->largepkt)
  893. kfree(pkt);
  894. else
  895. kmem_cache_free(pq->pkt_slab, pkt);
  896. free_pbc:
  897. if (dma_addr)
  898. dma_pool_free(pq->header_cache, pbc, dma_addr);
  899. else
  900. kfree(pbc);
  901. free_list:
  902. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, list);
  903. done:
  904. return ret;
  905. }
  906. static void qib_user_sdma_set_complete_counter(struct qib_user_sdma_queue *pq,
  907. u32 c)
  908. {
  909. pq->sent_counter = c;
  910. }
  911. /* try to clean out queue -- needs pq->lock */
  912. static int qib_user_sdma_queue_clean(struct qib_pportdata *ppd,
  913. struct qib_user_sdma_queue *pq)
  914. {
  915. struct qib_devdata *dd = ppd->dd;
  916. struct list_head free_list;
  917. struct qib_user_sdma_pkt *pkt;
  918. struct qib_user_sdma_pkt *pkt_prev;
  919. unsigned long flags;
  920. int ret = 0;
  921. if (!pq->num_sending)
  922. return 0;
  923. INIT_LIST_HEAD(&free_list);
  924. /*
  925. * We need this spin lock here because interrupt handler
  926. * might modify this list in qib_user_sdma_send_desc(), also
  927. * we can not get interrupted, otherwise it is a deadlock.
  928. */
  929. spin_lock_irqsave(&pq->sent_lock, flags);
  930. list_for_each_entry_safe(pkt, pkt_prev, &pq->sent, list) {
  931. s64 descd = ppd->sdma_descq_removed - pkt->added;
  932. if (descd < 0)
  933. break;
  934. list_move_tail(&pkt->list, &free_list);
  935. /* one more packet cleaned */
  936. ret++;
  937. pq->num_sending--;
  938. }
  939. spin_unlock_irqrestore(&pq->sent_lock, flags);
  940. if (!list_empty(&free_list)) {
  941. u32 counter;
  942. pkt = list_entry(free_list.prev,
  943. struct qib_user_sdma_pkt, list);
  944. counter = pkt->counter;
  945. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, &free_list);
  946. qib_user_sdma_set_complete_counter(pq, counter);
  947. }
  948. return ret;
  949. }
  950. void qib_user_sdma_queue_destroy(struct qib_user_sdma_queue *pq)
  951. {
  952. if (!pq)
  953. return;
  954. pq->sdma_rb_node->refcount--;
  955. if (pq->sdma_rb_node->refcount == 0) {
  956. rb_erase(&pq->sdma_rb_node->node, &qib_user_sdma_rb_root);
  957. kfree(pq->sdma_rb_node);
  958. }
  959. dma_pool_destroy(pq->header_cache);
  960. kmem_cache_destroy(pq->pkt_slab);
  961. kfree(pq);
  962. }
  963. /* clean descriptor queue, returns > 0 if some elements cleaned */
  964. static int qib_user_sdma_hwqueue_clean(struct qib_pportdata *ppd)
  965. {
  966. int ret;
  967. unsigned long flags;
  968. spin_lock_irqsave(&ppd->sdma_lock, flags);
  969. ret = qib_sdma_make_progress(ppd);
  970. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  971. return ret;
  972. }
  973. /* we're in close, drain packets so that we can cleanup successfully... */
  974. void qib_user_sdma_queue_drain(struct qib_pportdata *ppd,
  975. struct qib_user_sdma_queue *pq)
  976. {
  977. struct qib_devdata *dd = ppd->dd;
  978. unsigned long flags;
  979. int i;
  980. if (!pq)
  981. return;
  982. for (i = 0; i < QIB_USER_SDMA_DRAIN_TIMEOUT; i++) {
  983. mutex_lock(&pq->lock);
  984. if (!pq->num_pending && !pq->num_sending) {
  985. mutex_unlock(&pq->lock);
  986. break;
  987. }
  988. qib_user_sdma_hwqueue_clean(ppd);
  989. qib_user_sdma_queue_clean(ppd, pq);
  990. mutex_unlock(&pq->lock);
  991. msleep(20);
  992. }
  993. if (pq->num_pending || pq->num_sending) {
  994. struct qib_user_sdma_pkt *pkt;
  995. struct qib_user_sdma_pkt *pkt_prev;
  996. struct list_head free_list;
  997. mutex_lock(&pq->lock);
  998. spin_lock_irqsave(&ppd->sdma_lock, flags);
  999. /*
  1000. * Since we hold sdma_lock, it is safe without sent_lock.
  1001. */
  1002. if (pq->num_pending) {
  1003. list_for_each_entry_safe(pkt, pkt_prev,
  1004. &ppd->sdma_userpending, list) {
  1005. if (pkt->pq == pq) {
  1006. list_move_tail(&pkt->list, &pq->sent);
  1007. pq->num_pending--;
  1008. pq->num_sending++;
  1009. }
  1010. }
  1011. }
  1012. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1013. qib_dev_err(dd, "user sdma lists not empty: forcing!\n");
  1014. INIT_LIST_HEAD(&free_list);
  1015. list_splice_init(&pq->sent, &free_list);
  1016. pq->num_sending = 0;
  1017. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, &free_list);
  1018. mutex_unlock(&pq->lock);
  1019. }
  1020. }
  1021. static inline __le64 qib_sdma_make_desc0(u8 gen,
  1022. u64 addr, u64 dwlen, u64 dwoffset)
  1023. {
  1024. return cpu_to_le64(/* SDmaPhyAddr[31:0] */
  1025. ((addr & 0xfffffffcULL) << 32) |
  1026. /* SDmaGeneration[1:0] */
  1027. ((gen & 3ULL) << 30) |
  1028. /* SDmaDwordCount[10:0] */
  1029. ((dwlen & 0x7ffULL) << 16) |
  1030. /* SDmaBufOffset[12:2] */
  1031. (dwoffset & 0x7ffULL));
  1032. }
  1033. static inline __le64 qib_sdma_make_first_desc0(__le64 descq)
  1034. {
  1035. return descq | cpu_to_le64(1ULL << 12);
  1036. }
  1037. static inline __le64 qib_sdma_make_last_desc0(__le64 descq)
  1038. {
  1039. /* last */ /* dma head */
  1040. return descq | cpu_to_le64(1ULL << 11 | 1ULL << 13);
  1041. }
  1042. static inline __le64 qib_sdma_make_desc1(u64 addr)
  1043. {
  1044. /* SDmaPhyAddr[47:32] */
  1045. return cpu_to_le64(addr >> 32);
  1046. }
  1047. static void qib_user_sdma_send_frag(struct qib_pportdata *ppd,
  1048. struct qib_user_sdma_pkt *pkt, int idx,
  1049. unsigned ofs, u16 tail, u8 gen)
  1050. {
  1051. const u64 addr = (u64) pkt->addr[idx].addr +
  1052. (u64) pkt->addr[idx].offset;
  1053. const u64 dwlen = (u64) pkt->addr[idx].length / 4;
  1054. __le64 *descqp;
  1055. __le64 descq0;
  1056. descqp = &ppd->sdma_descq[tail].qw[0];
  1057. descq0 = qib_sdma_make_desc0(gen, addr, dwlen, ofs);
  1058. if (pkt->addr[idx].first_desc)
  1059. descq0 = qib_sdma_make_first_desc0(descq0);
  1060. if (pkt->addr[idx].last_desc) {
  1061. descq0 = qib_sdma_make_last_desc0(descq0);
  1062. if (ppd->sdma_intrequest) {
  1063. descq0 |= cpu_to_le64(1ULL << 15);
  1064. ppd->sdma_intrequest = 0;
  1065. }
  1066. }
  1067. descqp[0] = descq0;
  1068. descqp[1] = qib_sdma_make_desc1(addr);
  1069. }
  1070. void qib_user_sdma_send_desc(struct qib_pportdata *ppd,
  1071. struct list_head *pktlist)
  1072. {
  1073. struct qib_devdata *dd = ppd->dd;
  1074. u16 nfree, nsent;
  1075. u16 tail, tail_c;
  1076. u8 gen, gen_c;
  1077. nfree = qib_sdma_descq_freecnt(ppd);
  1078. if (!nfree)
  1079. return;
  1080. retry:
  1081. nsent = 0;
  1082. tail_c = tail = ppd->sdma_descq_tail;
  1083. gen_c = gen = ppd->sdma_generation;
  1084. while (!list_empty(pktlist)) {
  1085. struct qib_user_sdma_pkt *pkt =
  1086. list_entry(pktlist->next, struct qib_user_sdma_pkt,
  1087. list);
  1088. int i, j, c = 0;
  1089. unsigned ofs = 0;
  1090. u16 dtail = tail;
  1091. for (i = pkt->index; i < pkt->naddr && nfree; i++) {
  1092. qib_user_sdma_send_frag(ppd, pkt, i, ofs, tail, gen);
  1093. ofs += pkt->addr[i].length >> 2;
  1094. if (++tail == ppd->sdma_descq_cnt) {
  1095. tail = 0;
  1096. ++gen;
  1097. ppd->sdma_intrequest = 1;
  1098. } else if (tail == (ppd->sdma_descq_cnt>>1)) {
  1099. ppd->sdma_intrequest = 1;
  1100. }
  1101. nfree--;
  1102. if (pkt->addr[i].last_desc == 0)
  1103. continue;
  1104. /*
  1105. * If the packet is >= 2KB mtu equivalent, we
  1106. * have to use the large buffers, and have to
  1107. * mark each descriptor as part of a large
  1108. * buffer packet.
  1109. */
  1110. if (ofs > dd->piosize2kmax_dwords) {
  1111. for (j = pkt->index; j <= i; j++) {
  1112. ppd->sdma_descq[dtail].qw[0] |=
  1113. cpu_to_le64(1ULL << 14);
  1114. if (++dtail == ppd->sdma_descq_cnt)
  1115. dtail = 0;
  1116. }
  1117. }
  1118. c += i + 1 - pkt->index;
  1119. pkt->index = i + 1; /* index for next first */
  1120. tail_c = dtail = tail;
  1121. gen_c = gen;
  1122. ofs = 0; /* reset for next packet */
  1123. }
  1124. ppd->sdma_descq_added += c;
  1125. nsent += c;
  1126. if (pkt->index == pkt->naddr) {
  1127. pkt->added = ppd->sdma_descq_added;
  1128. pkt->pq->added = pkt->added;
  1129. pkt->pq->num_pending--;
  1130. spin_lock(&pkt->pq->sent_lock);
  1131. pkt->pq->num_sending++;
  1132. list_move_tail(&pkt->list, &pkt->pq->sent);
  1133. spin_unlock(&pkt->pq->sent_lock);
  1134. }
  1135. if (!nfree || (nsent<<2) > ppd->sdma_descq_cnt)
  1136. break;
  1137. }
  1138. /* advance the tail on the chip if necessary */
  1139. if (ppd->sdma_descq_tail != tail_c) {
  1140. ppd->sdma_generation = gen_c;
  1141. dd->f_sdma_update_tail(ppd, tail_c);
  1142. }
  1143. if (nfree && !list_empty(pktlist))
  1144. goto retry;
  1145. }
  1146. /* pq->lock must be held, get packets on the wire... */
  1147. static int qib_user_sdma_push_pkts(struct qib_pportdata *ppd,
  1148. struct qib_user_sdma_queue *pq,
  1149. struct list_head *pktlist, int count)
  1150. {
  1151. unsigned long flags;
  1152. if (unlikely(!(ppd->lflags & QIBL_LINKACTIVE)))
  1153. return -ECOMM;
  1154. /* non-blocking mode */
  1155. if (pq->sdma_rb_node->refcount > 1) {
  1156. spin_lock_irqsave(&ppd->sdma_lock, flags);
  1157. if (unlikely(!__qib_sdma_running(ppd))) {
  1158. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1159. return -ECOMM;
  1160. }
  1161. pq->num_pending += count;
  1162. list_splice_tail_init(pktlist, &ppd->sdma_userpending);
  1163. qib_user_sdma_send_desc(ppd, &ppd->sdma_userpending);
  1164. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1165. return 0;
  1166. }
  1167. /* In this case, descriptors from this process are not
  1168. * linked to ppd pending queue, interrupt handler
  1169. * won't update this process, it is OK to directly
  1170. * modify without sdma lock.
  1171. */
  1172. pq->num_pending += count;
  1173. /*
  1174. * Blocking mode for single rail process, we must
  1175. * release/regain sdma_lock to give other process
  1176. * chance to make progress. This is important for
  1177. * performance.
  1178. */
  1179. do {
  1180. spin_lock_irqsave(&ppd->sdma_lock, flags);
  1181. if (unlikely(!__qib_sdma_running(ppd))) {
  1182. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1183. return -ECOMM;
  1184. }
  1185. qib_user_sdma_send_desc(ppd, pktlist);
  1186. if (!list_empty(pktlist))
  1187. qib_sdma_make_progress(ppd);
  1188. spin_unlock_irqrestore(&ppd->sdma_lock, flags);
  1189. } while (!list_empty(pktlist));
  1190. return 0;
  1191. }
  1192. int qib_user_sdma_writev(struct qib_ctxtdata *rcd,
  1193. struct qib_user_sdma_queue *pq,
  1194. const struct iovec *iov,
  1195. unsigned long dim)
  1196. {
  1197. struct qib_devdata *dd = rcd->dd;
  1198. struct qib_pportdata *ppd = rcd->ppd;
  1199. int ret = 0;
  1200. struct list_head list;
  1201. int npkts = 0;
  1202. INIT_LIST_HEAD(&list);
  1203. mutex_lock(&pq->lock);
  1204. /* why not -ECOMM like qib_user_sdma_push_pkts() below? */
  1205. if (!qib_sdma_running(ppd))
  1206. goto done_unlock;
  1207. /* if I have packets not complete yet */
  1208. if (pq->added > ppd->sdma_descq_removed)
  1209. qib_user_sdma_hwqueue_clean(ppd);
  1210. /* if I have complete packets to be freed */
  1211. if (pq->num_sending)
  1212. qib_user_sdma_queue_clean(ppd, pq);
  1213. while (dim) {
  1214. int mxp = 1;
  1215. int ndesc = 0;
  1216. ret = qib_user_sdma_queue_pkts(dd, ppd, pq,
  1217. iov, dim, &list, &mxp, &ndesc);
  1218. if (ret < 0)
  1219. goto done_unlock;
  1220. else {
  1221. dim -= ret;
  1222. iov += ret;
  1223. }
  1224. /* force packets onto the sdma hw queue... */
  1225. if (!list_empty(&list)) {
  1226. /*
  1227. * Lazily clean hw queue.
  1228. */
  1229. if (qib_sdma_descq_freecnt(ppd) < ndesc) {
  1230. qib_user_sdma_hwqueue_clean(ppd);
  1231. if (pq->num_sending)
  1232. qib_user_sdma_queue_clean(ppd, pq);
  1233. }
  1234. ret = qib_user_sdma_push_pkts(ppd, pq, &list, mxp);
  1235. if (ret < 0)
  1236. goto done_unlock;
  1237. else {
  1238. npkts += mxp;
  1239. pq->counter += mxp;
  1240. }
  1241. }
  1242. }
  1243. done_unlock:
  1244. if (!list_empty(&list))
  1245. qib_user_sdma_free_pkt_list(&dd->pcidev->dev, pq, &list);
  1246. mutex_unlock(&pq->lock);
  1247. return (ret < 0) ? ret : npkts;
  1248. }
  1249. int qib_user_sdma_make_progress(struct qib_pportdata *ppd,
  1250. struct qib_user_sdma_queue *pq)
  1251. {
  1252. int ret = 0;
  1253. mutex_lock(&pq->lock);
  1254. qib_user_sdma_hwqueue_clean(ppd);
  1255. ret = qib_user_sdma_queue_clean(ppd, pq);
  1256. mutex_unlock(&pq->lock);
  1257. return ret;
  1258. }
  1259. u32 qib_user_sdma_complete_counter(const struct qib_user_sdma_queue *pq)
  1260. {
  1261. return pq ? pq->sent_counter : 0;
  1262. }
  1263. u32 qib_user_sdma_inflight_counter(struct qib_user_sdma_queue *pq)
  1264. {
  1265. return pq ? pq->counter : 0;
  1266. }