qib_uc.c 14 KB

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  1. /*
  2. * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
  3. * All rights reserved.
  4. * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include "qib.h"
  35. /* cut down ridiculously long IB macro names */
  36. #define OP(x) IB_OPCODE_UC_##x
  37. /**
  38. * qib_make_uc_req - construct a request packet (SEND, RDMA write)
  39. * @qp: a pointer to the QP
  40. *
  41. * Return 1 if constructed; otherwise, return 0.
  42. */
  43. int qib_make_uc_req(struct qib_qp *qp)
  44. {
  45. struct qib_other_headers *ohdr;
  46. struct qib_swqe *wqe;
  47. unsigned long flags;
  48. u32 hwords;
  49. u32 bth0;
  50. u32 len;
  51. u32 pmtu = qp->pmtu;
  52. int ret = 0;
  53. spin_lock_irqsave(&qp->s_lock, flags);
  54. if (!(ib_qib_state_ops[qp->state] & QIB_PROCESS_SEND_OK)) {
  55. if (!(ib_qib_state_ops[qp->state] & QIB_FLUSH_SEND))
  56. goto bail;
  57. /* We are in the error state, flush the work request. */
  58. if (qp->s_last == qp->s_head)
  59. goto bail;
  60. /* If DMAs are in progress, we can't flush immediately. */
  61. if (atomic_read(&qp->s_dma_busy)) {
  62. qp->s_flags |= QIB_S_WAIT_DMA;
  63. goto bail;
  64. }
  65. wqe = get_swqe_ptr(qp, qp->s_last);
  66. qib_send_complete(qp, wqe, IB_WC_WR_FLUSH_ERR);
  67. goto done;
  68. }
  69. ohdr = &qp->s_hdr->u.oth;
  70. if (qp->remote_ah_attr.ah_flags & IB_AH_GRH)
  71. ohdr = &qp->s_hdr->u.l.oth;
  72. /* header size in 32-bit words LRH+BTH = (8+12)/4. */
  73. hwords = 5;
  74. bth0 = 0;
  75. /* Get the next send request. */
  76. wqe = get_swqe_ptr(qp, qp->s_cur);
  77. qp->s_wqe = NULL;
  78. switch (qp->s_state) {
  79. default:
  80. if (!(ib_qib_state_ops[qp->state] &
  81. QIB_PROCESS_NEXT_SEND_OK))
  82. goto bail;
  83. /* Check if send work queue is empty. */
  84. if (qp->s_cur == qp->s_head)
  85. goto bail;
  86. /*
  87. * Start a new request.
  88. */
  89. wqe->psn = qp->s_next_psn;
  90. qp->s_psn = qp->s_next_psn;
  91. qp->s_sge.sge = wqe->sg_list[0];
  92. qp->s_sge.sg_list = wqe->sg_list + 1;
  93. qp->s_sge.num_sge = wqe->wr.num_sge;
  94. qp->s_sge.total_len = wqe->length;
  95. len = wqe->length;
  96. qp->s_len = len;
  97. switch (wqe->wr.opcode) {
  98. case IB_WR_SEND:
  99. case IB_WR_SEND_WITH_IMM:
  100. if (len > pmtu) {
  101. qp->s_state = OP(SEND_FIRST);
  102. len = pmtu;
  103. break;
  104. }
  105. if (wqe->wr.opcode == IB_WR_SEND)
  106. qp->s_state = OP(SEND_ONLY);
  107. else {
  108. qp->s_state =
  109. OP(SEND_ONLY_WITH_IMMEDIATE);
  110. /* Immediate data comes after the BTH */
  111. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  112. hwords += 1;
  113. }
  114. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  115. bth0 |= IB_BTH_SOLICITED;
  116. qp->s_wqe = wqe;
  117. if (++qp->s_cur >= qp->s_size)
  118. qp->s_cur = 0;
  119. break;
  120. case IB_WR_RDMA_WRITE:
  121. case IB_WR_RDMA_WRITE_WITH_IMM:
  122. ohdr->u.rc.reth.vaddr =
  123. cpu_to_be64(wqe->wr.wr.rdma.remote_addr);
  124. ohdr->u.rc.reth.rkey =
  125. cpu_to_be32(wqe->wr.wr.rdma.rkey);
  126. ohdr->u.rc.reth.length = cpu_to_be32(len);
  127. hwords += sizeof(struct ib_reth) / 4;
  128. if (len > pmtu) {
  129. qp->s_state = OP(RDMA_WRITE_FIRST);
  130. len = pmtu;
  131. break;
  132. }
  133. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  134. qp->s_state = OP(RDMA_WRITE_ONLY);
  135. else {
  136. qp->s_state =
  137. OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
  138. /* Immediate data comes after the RETH */
  139. ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
  140. hwords += 1;
  141. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  142. bth0 |= IB_BTH_SOLICITED;
  143. }
  144. qp->s_wqe = wqe;
  145. if (++qp->s_cur >= qp->s_size)
  146. qp->s_cur = 0;
  147. break;
  148. default:
  149. goto bail;
  150. }
  151. break;
  152. case OP(SEND_FIRST):
  153. qp->s_state = OP(SEND_MIDDLE);
  154. /* FALLTHROUGH */
  155. case OP(SEND_MIDDLE):
  156. len = qp->s_len;
  157. if (len > pmtu) {
  158. len = pmtu;
  159. break;
  160. }
  161. if (wqe->wr.opcode == IB_WR_SEND)
  162. qp->s_state = OP(SEND_LAST);
  163. else {
  164. qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
  165. /* Immediate data comes after the BTH */
  166. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  167. hwords += 1;
  168. }
  169. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  170. bth0 |= IB_BTH_SOLICITED;
  171. qp->s_wqe = wqe;
  172. if (++qp->s_cur >= qp->s_size)
  173. qp->s_cur = 0;
  174. break;
  175. case OP(RDMA_WRITE_FIRST):
  176. qp->s_state = OP(RDMA_WRITE_MIDDLE);
  177. /* FALLTHROUGH */
  178. case OP(RDMA_WRITE_MIDDLE):
  179. len = qp->s_len;
  180. if (len > pmtu) {
  181. len = pmtu;
  182. break;
  183. }
  184. if (wqe->wr.opcode == IB_WR_RDMA_WRITE)
  185. qp->s_state = OP(RDMA_WRITE_LAST);
  186. else {
  187. qp->s_state =
  188. OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
  189. /* Immediate data comes after the BTH */
  190. ohdr->u.imm_data = wqe->wr.ex.imm_data;
  191. hwords += 1;
  192. if (wqe->wr.send_flags & IB_SEND_SOLICITED)
  193. bth0 |= IB_BTH_SOLICITED;
  194. }
  195. qp->s_wqe = wqe;
  196. if (++qp->s_cur >= qp->s_size)
  197. qp->s_cur = 0;
  198. break;
  199. }
  200. qp->s_len -= len;
  201. qp->s_hdrwords = hwords;
  202. qp->s_cur_sge = &qp->s_sge;
  203. qp->s_cur_size = len;
  204. qib_make_ruc_header(qp, ohdr, bth0 | (qp->s_state << 24),
  205. qp->s_next_psn++ & QIB_PSN_MASK);
  206. done:
  207. ret = 1;
  208. goto unlock;
  209. bail:
  210. qp->s_flags &= ~QIB_S_BUSY;
  211. unlock:
  212. spin_unlock_irqrestore(&qp->s_lock, flags);
  213. return ret;
  214. }
  215. /**
  216. * qib_uc_rcv - handle an incoming UC packet
  217. * @ibp: the port the packet came in on
  218. * @hdr: the header of the packet
  219. * @has_grh: true if the packet has a GRH
  220. * @data: the packet data
  221. * @tlen: the length of the packet
  222. * @qp: the QP for this packet.
  223. *
  224. * This is called from qib_qp_rcv() to process an incoming UC packet
  225. * for the given QP.
  226. * Called at interrupt level.
  227. */
  228. void qib_uc_rcv(struct qib_ibport *ibp, struct qib_ib_header *hdr,
  229. int has_grh, void *data, u32 tlen, struct qib_qp *qp)
  230. {
  231. struct qib_other_headers *ohdr;
  232. u32 opcode;
  233. u32 hdrsize;
  234. u32 psn;
  235. u32 pad;
  236. struct ib_wc wc;
  237. u32 pmtu = qp->pmtu;
  238. struct ib_reth *reth;
  239. int ret;
  240. /* Check for GRH */
  241. if (!has_grh) {
  242. ohdr = &hdr->u.oth;
  243. hdrsize = 8 + 12; /* LRH + BTH */
  244. } else {
  245. ohdr = &hdr->u.l.oth;
  246. hdrsize = 8 + 40 + 12; /* LRH + GRH + BTH */
  247. }
  248. opcode = be32_to_cpu(ohdr->bth[0]);
  249. if (qib_ruc_check_hdr(ibp, hdr, has_grh, qp, opcode))
  250. return;
  251. psn = be32_to_cpu(ohdr->bth[2]);
  252. opcode >>= 24;
  253. /* Compare the PSN verses the expected PSN. */
  254. if (unlikely(qib_cmp24(psn, qp->r_psn) != 0)) {
  255. /*
  256. * Handle a sequence error.
  257. * Silently drop any current message.
  258. */
  259. qp->r_psn = psn;
  260. inv:
  261. if (qp->r_state == OP(SEND_FIRST) ||
  262. qp->r_state == OP(SEND_MIDDLE)) {
  263. set_bit(QIB_R_REWIND_SGE, &qp->r_aflags);
  264. qp->r_sge.num_sge = 0;
  265. } else
  266. qib_put_ss(&qp->r_sge);
  267. qp->r_state = OP(SEND_LAST);
  268. switch (opcode) {
  269. case OP(SEND_FIRST):
  270. case OP(SEND_ONLY):
  271. case OP(SEND_ONLY_WITH_IMMEDIATE):
  272. goto send_first;
  273. case OP(RDMA_WRITE_FIRST):
  274. case OP(RDMA_WRITE_ONLY):
  275. case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
  276. goto rdma_first;
  277. default:
  278. goto drop;
  279. }
  280. }
  281. /* Check for opcode sequence errors. */
  282. switch (qp->r_state) {
  283. case OP(SEND_FIRST):
  284. case OP(SEND_MIDDLE):
  285. if (opcode == OP(SEND_MIDDLE) ||
  286. opcode == OP(SEND_LAST) ||
  287. opcode == OP(SEND_LAST_WITH_IMMEDIATE))
  288. break;
  289. goto inv;
  290. case OP(RDMA_WRITE_FIRST):
  291. case OP(RDMA_WRITE_MIDDLE):
  292. if (opcode == OP(RDMA_WRITE_MIDDLE) ||
  293. opcode == OP(RDMA_WRITE_LAST) ||
  294. opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
  295. break;
  296. goto inv;
  297. default:
  298. if (opcode == OP(SEND_FIRST) ||
  299. opcode == OP(SEND_ONLY) ||
  300. opcode == OP(SEND_ONLY_WITH_IMMEDIATE) ||
  301. opcode == OP(RDMA_WRITE_FIRST) ||
  302. opcode == OP(RDMA_WRITE_ONLY) ||
  303. opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
  304. break;
  305. goto inv;
  306. }
  307. if (qp->state == IB_QPS_RTR && !(qp->r_flags & QIB_R_COMM_EST)) {
  308. qp->r_flags |= QIB_R_COMM_EST;
  309. if (qp->ibqp.event_handler) {
  310. struct ib_event ev;
  311. ev.device = qp->ibqp.device;
  312. ev.element.qp = &qp->ibqp;
  313. ev.event = IB_EVENT_COMM_EST;
  314. qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
  315. }
  316. }
  317. /* OK, process the packet. */
  318. switch (opcode) {
  319. case OP(SEND_FIRST):
  320. case OP(SEND_ONLY):
  321. case OP(SEND_ONLY_WITH_IMMEDIATE):
  322. send_first:
  323. if (test_and_clear_bit(QIB_R_REWIND_SGE, &qp->r_aflags))
  324. qp->r_sge = qp->s_rdma_read_sge;
  325. else {
  326. ret = qib_get_rwqe(qp, 0);
  327. if (ret < 0)
  328. goto op_err;
  329. if (!ret)
  330. goto drop;
  331. /*
  332. * qp->s_rdma_read_sge will be the owner
  333. * of the mr references.
  334. */
  335. qp->s_rdma_read_sge = qp->r_sge;
  336. }
  337. qp->r_rcv_len = 0;
  338. if (opcode == OP(SEND_ONLY))
  339. goto no_immediate_data;
  340. else if (opcode == OP(SEND_ONLY_WITH_IMMEDIATE))
  341. goto send_last_imm;
  342. /* FALLTHROUGH */
  343. case OP(SEND_MIDDLE):
  344. /* Check for invalid length PMTU or posted rwqe len. */
  345. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  346. goto rewind;
  347. qp->r_rcv_len += pmtu;
  348. if (unlikely(qp->r_rcv_len > qp->r_len))
  349. goto rewind;
  350. qib_copy_sge(&qp->r_sge, data, pmtu, 0);
  351. break;
  352. case OP(SEND_LAST_WITH_IMMEDIATE):
  353. send_last_imm:
  354. wc.ex.imm_data = ohdr->u.imm_data;
  355. hdrsize += 4;
  356. wc.wc_flags = IB_WC_WITH_IMM;
  357. goto send_last;
  358. case OP(SEND_LAST):
  359. no_immediate_data:
  360. wc.ex.imm_data = 0;
  361. wc.wc_flags = 0;
  362. send_last:
  363. /* Get the number of bytes the message was padded by. */
  364. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  365. /* Check for invalid length. */
  366. /* XXX LAST len should be >= 1 */
  367. if (unlikely(tlen < (hdrsize + pad + 4)))
  368. goto rewind;
  369. /* Don't count the CRC. */
  370. tlen -= (hdrsize + pad + 4);
  371. wc.byte_len = tlen + qp->r_rcv_len;
  372. if (unlikely(wc.byte_len > qp->r_len))
  373. goto rewind;
  374. wc.opcode = IB_WC_RECV;
  375. qib_copy_sge(&qp->r_sge, data, tlen, 0);
  376. qib_put_ss(&qp->s_rdma_read_sge);
  377. last_imm:
  378. wc.wr_id = qp->r_wr_id;
  379. wc.status = IB_WC_SUCCESS;
  380. wc.qp = &qp->ibqp;
  381. wc.src_qp = qp->remote_qpn;
  382. wc.slid = qp->remote_ah_attr.dlid;
  383. wc.sl = qp->remote_ah_attr.sl;
  384. /* zero fields that are N/A */
  385. wc.vendor_err = 0;
  386. wc.pkey_index = 0;
  387. wc.dlid_path_bits = 0;
  388. wc.port_num = 0;
  389. /* Signal completion event if the solicited bit is set. */
  390. qib_cq_enter(to_icq(qp->ibqp.recv_cq), &wc,
  391. (ohdr->bth[0] &
  392. cpu_to_be32(IB_BTH_SOLICITED)) != 0);
  393. break;
  394. case OP(RDMA_WRITE_FIRST):
  395. case OP(RDMA_WRITE_ONLY):
  396. case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): /* consume RWQE */
  397. rdma_first:
  398. if (unlikely(!(qp->qp_access_flags &
  399. IB_ACCESS_REMOTE_WRITE))) {
  400. goto drop;
  401. }
  402. reth = &ohdr->u.rc.reth;
  403. hdrsize += sizeof(*reth);
  404. qp->r_len = be32_to_cpu(reth->length);
  405. qp->r_rcv_len = 0;
  406. qp->r_sge.sg_list = NULL;
  407. if (qp->r_len != 0) {
  408. u32 rkey = be32_to_cpu(reth->rkey);
  409. u64 vaddr = be64_to_cpu(reth->vaddr);
  410. int ok;
  411. /* Check rkey */
  412. ok = qib_rkey_ok(qp, &qp->r_sge.sge, qp->r_len,
  413. vaddr, rkey, IB_ACCESS_REMOTE_WRITE);
  414. if (unlikely(!ok))
  415. goto drop;
  416. qp->r_sge.num_sge = 1;
  417. } else {
  418. qp->r_sge.num_sge = 0;
  419. qp->r_sge.sge.mr = NULL;
  420. qp->r_sge.sge.vaddr = NULL;
  421. qp->r_sge.sge.length = 0;
  422. qp->r_sge.sge.sge_length = 0;
  423. }
  424. if (opcode == OP(RDMA_WRITE_ONLY))
  425. goto rdma_last;
  426. else if (opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) {
  427. wc.ex.imm_data = ohdr->u.rc.imm_data;
  428. goto rdma_last_imm;
  429. }
  430. /* FALLTHROUGH */
  431. case OP(RDMA_WRITE_MIDDLE):
  432. /* Check for invalid length PMTU or posted rwqe len. */
  433. if (unlikely(tlen != (hdrsize + pmtu + 4)))
  434. goto drop;
  435. qp->r_rcv_len += pmtu;
  436. if (unlikely(qp->r_rcv_len > qp->r_len))
  437. goto drop;
  438. qib_copy_sge(&qp->r_sge, data, pmtu, 1);
  439. break;
  440. case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
  441. wc.ex.imm_data = ohdr->u.imm_data;
  442. rdma_last_imm:
  443. hdrsize += 4;
  444. wc.wc_flags = IB_WC_WITH_IMM;
  445. /* Get the number of bytes the message was padded by. */
  446. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  447. /* Check for invalid length. */
  448. /* XXX LAST len should be >= 1 */
  449. if (unlikely(tlen < (hdrsize + pad + 4)))
  450. goto drop;
  451. /* Don't count the CRC. */
  452. tlen -= (hdrsize + pad + 4);
  453. if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
  454. goto drop;
  455. if (test_and_clear_bit(QIB_R_REWIND_SGE, &qp->r_aflags))
  456. qib_put_ss(&qp->s_rdma_read_sge);
  457. else {
  458. ret = qib_get_rwqe(qp, 1);
  459. if (ret < 0)
  460. goto op_err;
  461. if (!ret)
  462. goto drop;
  463. }
  464. wc.byte_len = qp->r_len;
  465. wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
  466. qib_copy_sge(&qp->r_sge, data, tlen, 1);
  467. qib_put_ss(&qp->r_sge);
  468. goto last_imm;
  469. case OP(RDMA_WRITE_LAST):
  470. rdma_last:
  471. /* Get the number of bytes the message was padded by. */
  472. pad = (be32_to_cpu(ohdr->bth[0]) >> 20) & 3;
  473. /* Check for invalid length. */
  474. /* XXX LAST len should be >= 1 */
  475. if (unlikely(tlen < (hdrsize + pad + 4)))
  476. goto drop;
  477. /* Don't count the CRC. */
  478. tlen -= (hdrsize + pad + 4);
  479. if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
  480. goto drop;
  481. qib_copy_sge(&qp->r_sge, data, tlen, 1);
  482. qib_put_ss(&qp->r_sge);
  483. break;
  484. default:
  485. /* Drop packet for unknown opcodes. */
  486. goto drop;
  487. }
  488. qp->r_psn++;
  489. qp->r_state = opcode;
  490. return;
  491. rewind:
  492. set_bit(QIB_R_REWIND_SGE, &qp->r_aflags);
  493. qp->r_sge.num_sge = 0;
  494. drop:
  495. ibp->n_pkt_drops++;
  496. return;
  497. op_err:
  498. qib_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
  499. return;
  500. }