main.c 41 KB

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  1. /*
  2. * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <asm-generic/kmap_types.h>
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/errno.h>
  36. #include <linux/pci.h>
  37. #include <linux/dma-mapping.h>
  38. #include <linux/slab.h>
  39. #include <linux/io-mapping.h>
  40. #include <linux/sched.h>
  41. #include <rdma/ib_user_verbs.h>
  42. #include <linux/mlx5/vport.h>
  43. #include <rdma/ib_smi.h>
  44. #include <rdma/ib_umem.h>
  45. #include "user.h"
  46. #include "mlx5_ib.h"
  47. #define DRIVER_NAME "mlx5_ib"
  48. #define DRIVER_VERSION "2.2-1"
  49. #define DRIVER_RELDATE "Feb 2014"
  50. MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  51. MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
  52. MODULE_LICENSE("Dual BSD/GPL");
  53. MODULE_VERSION(DRIVER_VERSION);
  54. static int deprecated_prof_sel = 2;
  55. module_param_named(prof_sel, deprecated_prof_sel, int, 0444);
  56. MODULE_PARM_DESC(prof_sel, "profile selector. Deprecated here. Moved to module mlx5_core");
  57. static char mlx5_version[] =
  58. DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
  59. DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  60. static enum rdma_link_layer
  61. mlx5_ib_port_link_layer(struct ib_device *device)
  62. {
  63. struct mlx5_ib_dev *dev = to_mdev(device);
  64. switch (MLX5_CAP_GEN(dev->mdev, port_type)) {
  65. case MLX5_CAP_PORT_TYPE_IB:
  66. return IB_LINK_LAYER_INFINIBAND;
  67. case MLX5_CAP_PORT_TYPE_ETH:
  68. return IB_LINK_LAYER_ETHERNET;
  69. default:
  70. return IB_LINK_LAYER_UNSPECIFIED;
  71. }
  72. }
  73. static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
  74. {
  75. return !dev->mdev->issi;
  76. }
  77. enum {
  78. MLX5_VPORT_ACCESS_METHOD_MAD,
  79. MLX5_VPORT_ACCESS_METHOD_HCA,
  80. MLX5_VPORT_ACCESS_METHOD_NIC,
  81. };
  82. static int mlx5_get_vport_access_method(struct ib_device *ibdev)
  83. {
  84. if (mlx5_use_mad_ifc(to_mdev(ibdev)))
  85. return MLX5_VPORT_ACCESS_METHOD_MAD;
  86. if (mlx5_ib_port_link_layer(ibdev) ==
  87. IB_LINK_LAYER_ETHERNET)
  88. return MLX5_VPORT_ACCESS_METHOD_NIC;
  89. return MLX5_VPORT_ACCESS_METHOD_HCA;
  90. }
  91. static int mlx5_query_system_image_guid(struct ib_device *ibdev,
  92. __be64 *sys_image_guid)
  93. {
  94. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  95. struct mlx5_core_dev *mdev = dev->mdev;
  96. u64 tmp;
  97. int err;
  98. switch (mlx5_get_vport_access_method(ibdev)) {
  99. case MLX5_VPORT_ACCESS_METHOD_MAD:
  100. return mlx5_query_mad_ifc_system_image_guid(ibdev,
  101. sys_image_guid);
  102. case MLX5_VPORT_ACCESS_METHOD_HCA:
  103. err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
  104. if (!err)
  105. *sys_image_guid = cpu_to_be64(tmp);
  106. return err;
  107. default:
  108. return -EINVAL;
  109. }
  110. }
  111. static int mlx5_query_max_pkeys(struct ib_device *ibdev,
  112. u16 *max_pkeys)
  113. {
  114. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  115. struct mlx5_core_dev *mdev = dev->mdev;
  116. switch (mlx5_get_vport_access_method(ibdev)) {
  117. case MLX5_VPORT_ACCESS_METHOD_MAD:
  118. return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
  119. case MLX5_VPORT_ACCESS_METHOD_HCA:
  120. case MLX5_VPORT_ACCESS_METHOD_NIC:
  121. *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
  122. pkey_table_size));
  123. return 0;
  124. default:
  125. return -EINVAL;
  126. }
  127. }
  128. static int mlx5_query_vendor_id(struct ib_device *ibdev,
  129. u32 *vendor_id)
  130. {
  131. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  132. switch (mlx5_get_vport_access_method(ibdev)) {
  133. case MLX5_VPORT_ACCESS_METHOD_MAD:
  134. return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
  135. case MLX5_VPORT_ACCESS_METHOD_HCA:
  136. case MLX5_VPORT_ACCESS_METHOD_NIC:
  137. return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
  138. default:
  139. return -EINVAL;
  140. }
  141. }
  142. static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
  143. __be64 *node_guid)
  144. {
  145. u64 tmp;
  146. int err;
  147. switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
  148. case MLX5_VPORT_ACCESS_METHOD_MAD:
  149. return mlx5_query_mad_ifc_node_guid(dev, node_guid);
  150. case MLX5_VPORT_ACCESS_METHOD_HCA:
  151. err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
  152. if (!err)
  153. *node_guid = cpu_to_be64(tmp);
  154. return err;
  155. default:
  156. return -EINVAL;
  157. }
  158. }
  159. struct mlx5_reg_node_desc {
  160. u8 desc[64];
  161. };
  162. static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
  163. {
  164. struct mlx5_reg_node_desc in;
  165. if (mlx5_use_mad_ifc(dev))
  166. return mlx5_query_mad_ifc_node_desc(dev, node_desc);
  167. memset(&in, 0, sizeof(in));
  168. return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
  169. sizeof(struct mlx5_reg_node_desc),
  170. MLX5_REG_NODE_DESC, 0, 0);
  171. }
  172. static int mlx5_ib_query_device(struct ib_device *ibdev,
  173. struct ib_device_attr *props,
  174. struct ib_udata *uhw)
  175. {
  176. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  177. struct mlx5_core_dev *mdev = dev->mdev;
  178. int err = -ENOMEM;
  179. int max_rq_sg;
  180. int max_sq_sg;
  181. if (uhw->inlen || uhw->outlen)
  182. return -EINVAL;
  183. memset(props, 0, sizeof(*props));
  184. err = mlx5_query_system_image_guid(ibdev,
  185. &props->sys_image_guid);
  186. if (err)
  187. return err;
  188. err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
  189. if (err)
  190. return err;
  191. err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
  192. if (err)
  193. return err;
  194. props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
  195. (fw_rev_min(dev->mdev) << 16) |
  196. fw_rev_sub(dev->mdev);
  197. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  198. IB_DEVICE_PORT_ACTIVE_EVENT |
  199. IB_DEVICE_SYS_IMAGE_GUID |
  200. IB_DEVICE_RC_RNR_NAK_GEN;
  201. if (MLX5_CAP_GEN(mdev, pkv))
  202. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  203. if (MLX5_CAP_GEN(mdev, qkv))
  204. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  205. if (MLX5_CAP_GEN(mdev, apm))
  206. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  207. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  208. if (MLX5_CAP_GEN(mdev, xrc))
  209. props->device_cap_flags |= IB_DEVICE_XRC;
  210. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  211. if (MLX5_CAP_GEN(mdev, sho)) {
  212. props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
  213. /* At this stage no support for signature handover */
  214. props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
  215. IB_PROT_T10DIF_TYPE_2 |
  216. IB_PROT_T10DIF_TYPE_3;
  217. props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
  218. IB_GUARD_T10DIF_CSUM;
  219. }
  220. if (MLX5_CAP_GEN(mdev, block_lb_mc))
  221. props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  222. props->vendor_part_id = mdev->pdev->device;
  223. props->hw_ver = mdev->pdev->revision;
  224. props->max_mr_size = ~0ull;
  225. props->page_size_cap = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
  226. props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
  227. props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
  228. max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
  229. sizeof(struct mlx5_wqe_data_seg);
  230. max_sq_sg = (MLX5_CAP_GEN(mdev, max_wqe_sz_sq) -
  231. sizeof(struct mlx5_wqe_ctrl_seg)) /
  232. sizeof(struct mlx5_wqe_data_seg);
  233. props->max_sge = min(max_rq_sg, max_sq_sg);
  234. props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
  235. props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_eq_sz)) - 1;
  236. props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
  237. props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
  238. props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
  239. props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
  240. props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
  241. props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
  242. props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
  243. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  244. props->max_srq_sge = max_rq_sg - 1;
  245. props->max_fast_reg_page_list_len = (unsigned int)-1;
  246. props->atomic_cap = IB_ATOMIC_NONE;
  247. props->masked_atomic_cap = IB_ATOMIC_NONE;
  248. props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
  249. props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
  250. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  251. props->max_mcast_grp;
  252. props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
  253. #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
  254. if (MLX5_CAP_GEN(mdev, pg))
  255. props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
  256. props->odp_caps = dev->odp_caps;
  257. #endif
  258. return 0;
  259. }
  260. enum mlx5_ib_width {
  261. MLX5_IB_WIDTH_1X = 1 << 0,
  262. MLX5_IB_WIDTH_2X = 1 << 1,
  263. MLX5_IB_WIDTH_4X = 1 << 2,
  264. MLX5_IB_WIDTH_8X = 1 << 3,
  265. MLX5_IB_WIDTH_12X = 1 << 4
  266. };
  267. static int translate_active_width(struct ib_device *ibdev, u8 active_width,
  268. u8 *ib_width)
  269. {
  270. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  271. int err = 0;
  272. if (active_width & MLX5_IB_WIDTH_1X) {
  273. *ib_width = IB_WIDTH_1X;
  274. } else if (active_width & MLX5_IB_WIDTH_2X) {
  275. mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
  276. (int)active_width);
  277. err = -EINVAL;
  278. } else if (active_width & MLX5_IB_WIDTH_4X) {
  279. *ib_width = IB_WIDTH_4X;
  280. } else if (active_width & MLX5_IB_WIDTH_8X) {
  281. *ib_width = IB_WIDTH_8X;
  282. } else if (active_width & MLX5_IB_WIDTH_12X) {
  283. *ib_width = IB_WIDTH_12X;
  284. } else {
  285. mlx5_ib_dbg(dev, "Invalid active_width %d\n",
  286. (int)active_width);
  287. err = -EINVAL;
  288. }
  289. return err;
  290. }
  291. static int mlx5_mtu_to_ib_mtu(int mtu)
  292. {
  293. switch (mtu) {
  294. case 256: return 1;
  295. case 512: return 2;
  296. case 1024: return 3;
  297. case 2048: return 4;
  298. case 4096: return 5;
  299. default:
  300. pr_warn("invalid mtu\n");
  301. return -1;
  302. }
  303. }
  304. enum ib_max_vl_num {
  305. __IB_MAX_VL_0 = 1,
  306. __IB_MAX_VL_0_1 = 2,
  307. __IB_MAX_VL_0_3 = 3,
  308. __IB_MAX_VL_0_7 = 4,
  309. __IB_MAX_VL_0_14 = 5,
  310. };
  311. enum mlx5_vl_hw_cap {
  312. MLX5_VL_HW_0 = 1,
  313. MLX5_VL_HW_0_1 = 2,
  314. MLX5_VL_HW_0_2 = 3,
  315. MLX5_VL_HW_0_3 = 4,
  316. MLX5_VL_HW_0_4 = 5,
  317. MLX5_VL_HW_0_5 = 6,
  318. MLX5_VL_HW_0_6 = 7,
  319. MLX5_VL_HW_0_7 = 8,
  320. MLX5_VL_HW_0_14 = 15
  321. };
  322. static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
  323. u8 *max_vl_num)
  324. {
  325. switch (vl_hw_cap) {
  326. case MLX5_VL_HW_0:
  327. *max_vl_num = __IB_MAX_VL_0;
  328. break;
  329. case MLX5_VL_HW_0_1:
  330. *max_vl_num = __IB_MAX_VL_0_1;
  331. break;
  332. case MLX5_VL_HW_0_3:
  333. *max_vl_num = __IB_MAX_VL_0_3;
  334. break;
  335. case MLX5_VL_HW_0_7:
  336. *max_vl_num = __IB_MAX_VL_0_7;
  337. break;
  338. case MLX5_VL_HW_0_14:
  339. *max_vl_num = __IB_MAX_VL_0_14;
  340. break;
  341. default:
  342. return -EINVAL;
  343. }
  344. return 0;
  345. }
  346. static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
  347. struct ib_port_attr *props)
  348. {
  349. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  350. struct mlx5_core_dev *mdev = dev->mdev;
  351. struct mlx5_hca_vport_context *rep;
  352. int max_mtu;
  353. int oper_mtu;
  354. int err;
  355. u8 ib_link_width_oper;
  356. u8 vl_hw_cap;
  357. rep = kzalloc(sizeof(*rep), GFP_KERNEL);
  358. if (!rep) {
  359. err = -ENOMEM;
  360. goto out;
  361. }
  362. memset(props, 0, sizeof(*props));
  363. err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
  364. if (err)
  365. goto out;
  366. props->lid = rep->lid;
  367. props->lmc = rep->lmc;
  368. props->sm_lid = rep->sm_lid;
  369. props->sm_sl = rep->sm_sl;
  370. props->state = rep->vport_state;
  371. props->phys_state = rep->port_physical_state;
  372. props->port_cap_flags = rep->cap_mask1;
  373. props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
  374. props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
  375. props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
  376. props->bad_pkey_cntr = rep->pkey_violation_counter;
  377. props->qkey_viol_cntr = rep->qkey_violation_counter;
  378. props->subnet_timeout = rep->subnet_timeout;
  379. props->init_type_reply = rep->init_type_reply;
  380. err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
  381. if (err)
  382. goto out;
  383. err = translate_active_width(ibdev, ib_link_width_oper,
  384. &props->active_width);
  385. if (err)
  386. goto out;
  387. err = mlx5_query_port_proto_oper(mdev, &props->active_speed, MLX5_PTYS_IB,
  388. port);
  389. if (err)
  390. goto out;
  391. mlx5_query_port_max_mtu(mdev, &max_mtu, port);
  392. props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
  393. mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
  394. props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
  395. err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
  396. if (err)
  397. goto out;
  398. err = translate_max_vl_num(ibdev, vl_hw_cap,
  399. &props->max_vl_num);
  400. out:
  401. kfree(rep);
  402. return err;
  403. }
  404. int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
  405. struct ib_port_attr *props)
  406. {
  407. switch (mlx5_get_vport_access_method(ibdev)) {
  408. case MLX5_VPORT_ACCESS_METHOD_MAD:
  409. return mlx5_query_mad_ifc_port(ibdev, port, props);
  410. case MLX5_VPORT_ACCESS_METHOD_HCA:
  411. return mlx5_query_hca_port(ibdev, port, props);
  412. default:
  413. return -EINVAL;
  414. }
  415. }
  416. static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  417. union ib_gid *gid)
  418. {
  419. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  420. struct mlx5_core_dev *mdev = dev->mdev;
  421. switch (mlx5_get_vport_access_method(ibdev)) {
  422. case MLX5_VPORT_ACCESS_METHOD_MAD:
  423. return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
  424. case MLX5_VPORT_ACCESS_METHOD_HCA:
  425. return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
  426. default:
  427. return -EINVAL;
  428. }
  429. }
  430. static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  431. u16 *pkey)
  432. {
  433. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  434. struct mlx5_core_dev *mdev = dev->mdev;
  435. switch (mlx5_get_vport_access_method(ibdev)) {
  436. case MLX5_VPORT_ACCESS_METHOD_MAD:
  437. return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
  438. case MLX5_VPORT_ACCESS_METHOD_HCA:
  439. case MLX5_VPORT_ACCESS_METHOD_NIC:
  440. return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
  441. pkey);
  442. default:
  443. return -EINVAL;
  444. }
  445. }
  446. static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
  447. struct ib_device_modify *props)
  448. {
  449. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  450. struct mlx5_reg_node_desc in;
  451. struct mlx5_reg_node_desc out;
  452. int err;
  453. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  454. return -EOPNOTSUPP;
  455. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  456. return 0;
  457. /*
  458. * If possible, pass node desc to FW, so it can generate
  459. * a 144 trap. If cmd fails, just ignore.
  460. */
  461. memcpy(&in, props->node_desc, 64);
  462. err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
  463. sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
  464. if (err)
  465. return err;
  466. memcpy(ibdev->node_desc, props->node_desc, 64);
  467. return err;
  468. }
  469. static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  470. struct ib_port_modify *props)
  471. {
  472. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  473. struct ib_port_attr attr;
  474. u32 tmp;
  475. int err;
  476. mutex_lock(&dev->cap_mask_mutex);
  477. err = mlx5_ib_query_port(ibdev, port, &attr);
  478. if (err)
  479. goto out;
  480. tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
  481. ~props->clr_port_cap_mask;
  482. err = mlx5_set_port_caps(dev->mdev, port, tmp);
  483. out:
  484. mutex_unlock(&dev->cap_mask_mutex);
  485. return err;
  486. }
  487. static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
  488. struct ib_udata *udata)
  489. {
  490. struct mlx5_ib_dev *dev = to_mdev(ibdev);
  491. struct mlx5_ib_alloc_ucontext_req_v2 req;
  492. struct mlx5_ib_alloc_ucontext_resp resp;
  493. struct mlx5_ib_ucontext *context;
  494. struct mlx5_uuar_info *uuari;
  495. struct mlx5_uar *uars;
  496. int gross_uuars;
  497. int num_uars;
  498. int ver;
  499. int uuarn;
  500. int err;
  501. int i;
  502. size_t reqlen;
  503. if (!dev->ib_active)
  504. return ERR_PTR(-EAGAIN);
  505. memset(&req, 0, sizeof(req));
  506. reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
  507. if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
  508. ver = 0;
  509. else if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req_v2))
  510. ver = 2;
  511. else
  512. return ERR_PTR(-EINVAL);
  513. err = ib_copy_from_udata(&req, udata, reqlen);
  514. if (err)
  515. return ERR_PTR(err);
  516. if (req.flags || req.reserved)
  517. return ERR_PTR(-EINVAL);
  518. if (req.total_num_uuars > MLX5_MAX_UUARS)
  519. return ERR_PTR(-ENOMEM);
  520. if (req.total_num_uuars == 0)
  521. return ERR_PTR(-EINVAL);
  522. req.total_num_uuars = ALIGN(req.total_num_uuars,
  523. MLX5_NON_FP_BF_REGS_PER_PAGE);
  524. if (req.num_low_latency_uuars > req.total_num_uuars - 1)
  525. return ERR_PTR(-EINVAL);
  526. num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE;
  527. gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE;
  528. resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
  529. resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
  530. resp.cache_line_size = L1_CACHE_BYTES;
  531. resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
  532. resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
  533. resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
  534. resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
  535. resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
  536. context = kzalloc(sizeof(*context), GFP_KERNEL);
  537. if (!context)
  538. return ERR_PTR(-ENOMEM);
  539. uuari = &context->uuari;
  540. mutex_init(&uuari->lock);
  541. uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL);
  542. if (!uars) {
  543. err = -ENOMEM;
  544. goto out_ctx;
  545. }
  546. uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars),
  547. sizeof(*uuari->bitmap),
  548. GFP_KERNEL);
  549. if (!uuari->bitmap) {
  550. err = -ENOMEM;
  551. goto out_uar_ctx;
  552. }
  553. /*
  554. * clear all fast path uuars
  555. */
  556. for (i = 0; i < gross_uuars; i++) {
  557. uuarn = i & 3;
  558. if (uuarn == 2 || uuarn == 3)
  559. set_bit(i, uuari->bitmap);
  560. }
  561. uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL);
  562. if (!uuari->count) {
  563. err = -ENOMEM;
  564. goto out_bitmap;
  565. }
  566. for (i = 0; i < num_uars; i++) {
  567. err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index);
  568. if (err)
  569. goto out_count;
  570. }
  571. #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
  572. context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
  573. #endif
  574. INIT_LIST_HEAD(&context->db_page_list);
  575. mutex_init(&context->db_page_mutex);
  576. resp.tot_uuars = req.total_num_uuars;
  577. resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
  578. err = ib_copy_to_udata(udata, &resp,
  579. sizeof(resp) - sizeof(resp.reserved));
  580. if (err)
  581. goto out_uars;
  582. uuari->ver = ver;
  583. uuari->num_low_latency_uuars = req.num_low_latency_uuars;
  584. uuari->uars = uars;
  585. uuari->num_uars = num_uars;
  586. return &context->ibucontext;
  587. out_uars:
  588. for (i--; i >= 0; i--)
  589. mlx5_cmd_free_uar(dev->mdev, uars[i].index);
  590. out_count:
  591. kfree(uuari->count);
  592. out_bitmap:
  593. kfree(uuari->bitmap);
  594. out_uar_ctx:
  595. kfree(uars);
  596. out_ctx:
  597. kfree(context);
  598. return ERR_PTR(err);
  599. }
  600. static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  601. {
  602. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  603. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  604. struct mlx5_uuar_info *uuari = &context->uuari;
  605. int i;
  606. for (i = 0; i < uuari->num_uars; i++) {
  607. if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index))
  608. mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index);
  609. }
  610. kfree(uuari->count);
  611. kfree(uuari->bitmap);
  612. kfree(uuari->uars);
  613. kfree(context);
  614. return 0;
  615. }
  616. static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index)
  617. {
  618. return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index;
  619. }
  620. static int get_command(unsigned long offset)
  621. {
  622. return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
  623. }
  624. static int get_arg(unsigned long offset)
  625. {
  626. return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
  627. }
  628. static int get_index(unsigned long offset)
  629. {
  630. return get_arg(offset);
  631. }
  632. static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
  633. {
  634. struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
  635. struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
  636. struct mlx5_uuar_info *uuari = &context->uuari;
  637. unsigned long command;
  638. unsigned long idx;
  639. phys_addr_t pfn;
  640. command = get_command(vma->vm_pgoff);
  641. switch (command) {
  642. case MLX5_IB_MMAP_REGULAR_PAGE:
  643. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  644. return -EINVAL;
  645. idx = get_index(vma->vm_pgoff);
  646. if (idx >= uuari->num_uars)
  647. return -EINVAL;
  648. pfn = uar_index2pfn(dev, uuari->uars[idx].index);
  649. mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn 0x%llx\n", idx,
  650. (unsigned long long)pfn);
  651. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  652. if (io_remap_pfn_range(vma, vma->vm_start, pfn,
  653. PAGE_SIZE, vma->vm_page_prot))
  654. return -EAGAIN;
  655. mlx5_ib_dbg(dev, "mapped WC at 0x%lx, PA 0x%llx\n",
  656. vma->vm_start,
  657. (unsigned long long)pfn << PAGE_SHIFT);
  658. break;
  659. case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
  660. return -ENOSYS;
  661. default:
  662. return -EINVAL;
  663. }
  664. return 0;
  665. }
  666. static int alloc_pa_mkey(struct mlx5_ib_dev *dev, u32 *key, u32 pdn)
  667. {
  668. struct mlx5_create_mkey_mbox_in *in;
  669. struct mlx5_mkey_seg *seg;
  670. struct mlx5_core_mr mr;
  671. int err;
  672. in = kzalloc(sizeof(*in), GFP_KERNEL);
  673. if (!in)
  674. return -ENOMEM;
  675. seg = &in->seg;
  676. seg->flags = MLX5_PERM_LOCAL_READ | MLX5_ACCESS_MODE_PA;
  677. seg->flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
  678. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  679. seg->start_addr = 0;
  680. err = mlx5_core_create_mkey(dev->mdev, &mr, in, sizeof(*in),
  681. NULL, NULL, NULL);
  682. if (err) {
  683. mlx5_ib_warn(dev, "failed to create mkey, %d\n", err);
  684. goto err_in;
  685. }
  686. kfree(in);
  687. *key = mr.key;
  688. return 0;
  689. err_in:
  690. kfree(in);
  691. return err;
  692. }
  693. static void free_pa_mkey(struct mlx5_ib_dev *dev, u32 key)
  694. {
  695. struct mlx5_core_mr mr;
  696. int err;
  697. memset(&mr, 0, sizeof(mr));
  698. mr.key = key;
  699. err = mlx5_core_destroy_mkey(dev->mdev, &mr);
  700. if (err)
  701. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x\n", key);
  702. }
  703. static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
  704. struct ib_ucontext *context,
  705. struct ib_udata *udata)
  706. {
  707. struct mlx5_ib_alloc_pd_resp resp;
  708. struct mlx5_ib_pd *pd;
  709. int err;
  710. pd = kmalloc(sizeof(*pd), GFP_KERNEL);
  711. if (!pd)
  712. return ERR_PTR(-ENOMEM);
  713. err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
  714. if (err) {
  715. kfree(pd);
  716. return ERR_PTR(err);
  717. }
  718. if (context) {
  719. resp.pdn = pd->pdn;
  720. if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
  721. mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
  722. kfree(pd);
  723. return ERR_PTR(-EFAULT);
  724. }
  725. } else {
  726. err = alloc_pa_mkey(to_mdev(ibdev), &pd->pa_lkey, pd->pdn);
  727. if (err) {
  728. mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
  729. kfree(pd);
  730. return ERR_PTR(err);
  731. }
  732. }
  733. return &pd->ibpd;
  734. }
  735. static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
  736. {
  737. struct mlx5_ib_dev *mdev = to_mdev(pd->device);
  738. struct mlx5_ib_pd *mpd = to_mpd(pd);
  739. if (!pd->uobject)
  740. free_pa_mkey(mdev, mpd->pa_lkey);
  741. mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
  742. kfree(mpd);
  743. return 0;
  744. }
  745. static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  746. {
  747. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  748. int err;
  749. err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
  750. if (err)
  751. mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
  752. ibqp->qp_num, gid->raw);
  753. return err;
  754. }
  755. static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  756. {
  757. struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
  758. int err;
  759. err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
  760. if (err)
  761. mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
  762. ibqp->qp_num, gid->raw);
  763. return err;
  764. }
  765. static int init_node_data(struct mlx5_ib_dev *dev)
  766. {
  767. int err;
  768. err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
  769. if (err)
  770. return err;
  771. dev->mdev->rev_id = dev->mdev->pdev->revision;
  772. return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
  773. }
  774. static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
  775. char *buf)
  776. {
  777. struct mlx5_ib_dev *dev =
  778. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  779. return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
  780. }
  781. static ssize_t show_reg_pages(struct device *device,
  782. struct device_attribute *attr, char *buf)
  783. {
  784. struct mlx5_ib_dev *dev =
  785. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  786. return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
  787. }
  788. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  789. char *buf)
  790. {
  791. struct mlx5_ib_dev *dev =
  792. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  793. return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
  794. }
  795. static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
  796. char *buf)
  797. {
  798. struct mlx5_ib_dev *dev =
  799. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  800. return sprintf(buf, "%d.%d.%d\n", fw_rev_maj(dev->mdev),
  801. fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
  802. }
  803. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  804. char *buf)
  805. {
  806. struct mlx5_ib_dev *dev =
  807. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  808. return sprintf(buf, "%x\n", dev->mdev->rev_id);
  809. }
  810. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  811. char *buf)
  812. {
  813. struct mlx5_ib_dev *dev =
  814. container_of(device, struct mlx5_ib_dev, ib_dev.dev);
  815. return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
  816. dev->mdev->board_id);
  817. }
  818. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  819. static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
  820. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  821. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  822. static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
  823. static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
  824. static struct device_attribute *mlx5_class_attributes[] = {
  825. &dev_attr_hw_rev,
  826. &dev_attr_fw_ver,
  827. &dev_attr_hca_type,
  828. &dev_attr_board_id,
  829. &dev_attr_fw_pages,
  830. &dev_attr_reg_pages,
  831. };
  832. static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
  833. enum mlx5_dev_event event, unsigned long param)
  834. {
  835. struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
  836. struct ib_event ibev;
  837. u8 port = 0;
  838. switch (event) {
  839. case MLX5_DEV_EVENT_SYS_ERROR:
  840. ibdev->ib_active = false;
  841. ibev.event = IB_EVENT_DEVICE_FATAL;
  842. break;
  843. case MLX5_DEV_EVENT_PORT_UP:
  844. ibev.event = IB_EVENT_PORT_ACTIVE;
  845. port = (u8)param;
  846. break;
  847. case MLX5_DEV_EVENT_PORT_DOWN:
  848. ibev.event = IB_EVENT_PORT_ERR;
  849. port = (u8)param;
  850. break;
  851. case MLX5_DEV_EVENT_PORT_INITIALIZED:
  852. /* not used by ULPs */
  853. return;
  854. case MLX5_DEV_EVENT_LID_CHANGE:
  855. ibev.event = IB_EVENT_LID_CHANGE;
  856. port = (u8)param;
  857. break;
  858. case MLX5_DEV_EVENT_PKEY_CHANGE:
  859. ibev.event = IB_EVENT_PKEY_CHANGE;
  860. port = (u8)param;
  861. break;
  862. case MLX5_DEV_EVENT_GUID_CHANGE:
  863. ibev.event = IB_EVENT_GID_CHANGE;
  864. port = (u8)param;
  865. break;
  866. case MLX5_DEV_EVENT_CLIENT_REREG:
  867. ibev.event = IB_EVENT_CLIENT_REREGISTER;
  868. port = (u8)param;
  869. break;
  870. }
  871. ibev.device = &ibdev->ib_dev;
  872. ibev.element.port_num = port;
  873. if (port < 1 || port > ibdev->num_ports) {
  874. mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
  875. return;
  876. }
  877. if (ibdev->ib_active)
  878. ib_dispatch_event(&ibev);
  879. }
  880. static void get_ext_port_caps(struct mlx5_ib_dev *dev)
  881. {
  882. int port;
  883. for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
  884. mlx5_query_ext_port_caps(dev, port);
  885. }
  886. static int get_port_caps(struct mlx5_ib_dev *dev)
  887. {
  888. struct ib_device_attr *dprops = NULL;
  889. struct ib_port_attr *pprops = NULL;
  890. int err = -ENOMEM;
  891. int port;
  892. struct ib_udata uhw = {.inlen = 0, .outlen = 0};
  893. pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
  894. if (!pprops)
  895. goto out;
  896. dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
  897. if (!dprops)
  898. goto out;
  899. err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
  900. if (err) {
  901. mlx5_ib_warn(dev, "query_device failed %d\n", err);
  902. goto out;
  903. }
  904. for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
  905. err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
  906. if (err) {
  907. mlx5_ib_warn(dev, "query_port %d failed %d\n",
  908. port, err);
  909. break;
  910. }
  911. dev->mdev->port_caps[port - 1].pkey_table_len =
  912. dprops->max_pkeys;
  913. dev->mdev->port_caps[port - 1].gid_table_len =
  914. pprops->gid_tbl_len;
  915. mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
  916. dprops->max_pkeys, pprops->gid_tbl_len);
  917. }
  918. out:
  919. kfree(pprops);
  920. kfree(dprops);
  921. return err;
  922. }
  923. static void destroy_umrc_res(struct mlx5_ib_dev *dev)
  924. {
  925. int err;
  926. err = mlx5_mr_cache_cleanup(dev);
  927. if (err)
  928. mlx5_ib_warn(dev, "mr cache cleanup failed\n");
  929. mlx5_ib_destroy_qp(dev->umrc.qp);
  930. ib_destroy_cq(dev->umrc.cq);
  931. ib_dereg_mr(dev->umrc.mr);
  932. ib_dealloc_pd(dev->umrc.pd);
  933. }
  934. enum {
  935. MAX_UMR_WR = 128,
  936. };
  937. static int create_umr_res(struct mlx5_ib_dev *dev)
  938. {
  939. struct ib_qp_init_attr *init_attr = NULL;
  940. struct ib_qp_attr *attr = NULL;
  941. struct ib_pd *pd;
  942. struct ib_cq *cq;
  943. struct ib_qp *qp;
  944. struct ib_mr *mr;
  945. struct ib_cq_init_attr cq_attr = {};
  946. int ret;
  947. attr = kzalloc(sizeof(*attr), GFP_KERNEL);
  948. init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
  949. if (!attr || !init_attr) {
  950. ret = -ENOMEM;
  951. goto error_0;
  952. }
  953. pd = ib_alloc_pd(&dev->ib_dev);
  954. if (IS_ERR(pd)) {
  955. mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
  956. ret = PTR_ERR(pd);
  957. goto error_0;
  958. }
  959. mr = ib_get_dma_mr(pd, IB_ACCESS_LOCAL_WRITE);
  960. if (IS_ERR(mr)) {
  961. mlx5_ib_dbg(dev, "Couldn't create DMA MR for sync UMR QP\n");
  962. ret = PTR_ERR(mr);
  963. goto error_1;
  964. }
  965. cq_attr.cqe = 128;
  966. cq = ib_create_cq(&dev->ib_dev, mlx5_umr_cq_handler, NULL, NULL,
  967. &cq_attr);
  968. if (IS_ERR(cq)) {
  969. mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
  970. ret = PTR_ERR(cq);
  971. goto error_2;
  972. }
  973. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  974. init_attr->send_cq = cq;
  975. init_attr->recv_cq = cq;
  976. init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
  977. init_attr->cap.max_send_wr = MAX_UMR_WR;
  978. init_attr->cap.max_send_sge = 1;
  979. init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
  980. init_attr->port_num = 1;
  981. qp = mlx5_ib_create_qp(pd, init_attr, NULL);
  982. if (IS_ERR(qp)) {
  983. mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
  984. ret = PTR_ERR(qp);
  985. goto error_3;
  986. }
  987. qp->device = &dev->ib_dev;
  988. qp->real_qp = qp;
  989. qp->uobject = NULL;
  990. qp->qp_type = MLX5_IB_QPT_REG_UMR;
  991. attr->qp_state = IB_QPS_INIT;
  992. attr->port_num = 1;
  993. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
  994. IB_QP_PORT, NULL);
  995. if (ret) {
  996. mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
  997. goto error_4;
  998. }
  999. memset(attr, 0, sizeof(*attr));
  1000. attr->qp_state = IB_QPS_RTR;
  1001. attr->path_mtu = IB_MTU_256;
  1002. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  1003. if (ret) {
  1004. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
  1005. goto error_4;
  1006. }
  1007. memset(attr, 0, sizeof(*attr));
  1008. attr->qp_state = IB_QPS_RTS;
  1009. ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
  1010. if (ret) {
  1011. mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
  1012. goto error_4;
  1013. }
  1014. dev->umrc.qp = qp;
  1015. dev->umrc.cq = cq;
  1016. dev->umrc.mr = mr;
  1017. dev->umrc.pd = pd;
  1018. sema_init(&dev->umrc.sem, MAX_UMR_WR);
  1019. ret = mlx5_mr_cache_init(dev);
  1020. if (ret) {
  1021. mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
  1022. goto error_4;
  1023. }
  1024. kfree(attr);
  1025. kfree(init_attr);
  1026. return 0;
  1027. error_4:
  1028. mlx5_ib_destroy_qp(qp);
  1029. error_3:
  1030. ib_destroy_cq(cq);
  1031. error_2:
  1032. ib_dereg_mr(mr);
  1033. error_1:
  1034. ib_dealloc_pd(pd);
  1035. error_0:
  1036. kfree(attr);
  1037. kfree(init_attr);
  1038. return ret;
  1039. }
  1040. static int create_dev_resources(struct mlx5_ib_resources *devr)
  1041. {
  1042. struct ib_srq_init_attr attr;
  1043. struct mlx5_ib_dev *dev;
  1044. struct ib_cq_init_attr cq_attr = {.cqe = 1};
  1045. int ret = 0;
  1046. dev = container_of(devr, struct mlx5_ib_dev, devr);
  1047. devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
  1048. if (IS_ERR(devr->p0)) {
  1049. ret = PTR_ERR(devr->p0);
  1050. goto error0;
  1051. }
  1052. devr->p0->device = &dev->ib_dev;
  1053. devr->p0->uobject = NULL;
  1054. atomic_set(&devr->p0->usecnt, 0);
  1055. devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
  1056. if (IS_ERR(devr->c0)) {
  1057. ret = PTR_ERR(devr->c0);
  1058. goto error1;
  1059. }
  1060. devr->c0->device = &dev->ib_dev;
  1061. devr->c0->uobject = NULL;
  1062. devr->c0->comp_handler = NULL;
  1063. devr->c0->event_handler = NULL;
  1064. devr->c0->cq_context = NULL;
  1065. atomic_set(&devr->c0->usecnt, 0);
  1066. devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  1067. if (IS_ERR(devr->x0)) {
  1068. ret = PTR_ERR(devr->x0);
  1069. goto error2;
  1070. }
  1071. devr->x0->device = &dev->ib_dev;
  1072. devr->x0->inode = NULL;
  1073. atomic_set(&devr->x0->usecnt, 0);
  1074. mutex_init(&devr->x0->tgt_qp_mutex);
  1075. INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
  1076. devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
  1077. if (IS_ERR(devr->x1)) {
  1078. ret = PTR_ERR(devr->x1);
  1079. goto error3;
  1080. }
  1081. devr->x1->device = &dev->ib_dev;
  1082. devr->x1->inode = NULL;
  1083. atomic_set(&devr->x1->usecnt, 0);
  1084. mutex_init(&devr->x1->tgt_qp_mutex);
  1085. INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
  1086. memset(&attr, 0, sizeof(attr));
  1087. attr.attr.max_sge = 1;
  1088. attr.attr.max_wr = 1;
  1089. attr.srq_type = IB_SRQT_XRC;
  1090. attr.ext.xrc.cq = devr->c0;
  1091. attr.ext.xrc.xrcd = devr->x0;
  1092. devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
  1093. if (IS_ERR(devr->s0)) {
  1094. ret = PTR_ERR(devr->s0);
  1095. goto error4;
  1096. }
  1097. devr->s0->device = &dev->ib_dev;
  1098. devr->s0->pd = devr->p0;
  1099. devr->s0->uobject = NULL;
  1100. devr->s0->event_handler = NULL;
  1101. devr->s0->srq_context = NULL;
  1102. devr->s0->srq_type = IB_SRQT_XRC;
  1103. devr->s0->ext.xrc.xrcd = devr->x0;
  1104. devr->s0->ext.xrc.cq = devr->c0;
  1105. atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
  1106. atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
  1107. atomic_inc(&devr->p0->usecnt);
  1108. atomic_set(&devr->s0->usecnt, 0);
  1109. memset(&attr, 0, sizeof(attr));
  1110. attr.attr.max_sge = 1;
  1111. attr.attr.max_wr = 1;
  1112. attr.srq_type = IB_SRQT_BASIC;
  1113. devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
  1114. if (IS_ERR(devr->s1)) {
  1115. ret = PTR_ERR(devr->s1);
  1116. goto error5;
  1117. }
  1118. devr->s1->device = &dev->ib_dev;
  1119. devr->s1->pd = devr->p0;
  1120. devr->s1->uobject = NULL;
  1121. devr->s1->event_handler = NULL;
  1122. devr->s1->srq_context = NULL;
  1123. devr->s1->srq_type = IB_SRQT_BASIC;
  1124. devr->s1->ext.xrc.cq = devr->c0;
  1125. atomic_inc(&devr->p0->usecnt);
  1126. atomic_set(&devr->s0->usecnt, 0);
  1127. return 0;
  1128. error5:
  1129. mlx5_ib_destroy_srq(devr->s0);
  1130. error4:
  1131. mlx5_ib_dealloc_xrcd(devr->x1);
  1132. error3:
  1133. mlx5_ib_dealloc_xrcd(devr->x0);
  1134. error2:
  1135. mlx5_ib_destroy_cq(devr->c0);
  1136. error1:
  1137. mlx5_ib_dealloc_pd(devr->p0);
  1138. error0:
  1139. return ret;
  1140. }
  1141. static void destroy_dev_resources(struct mlx5_ib_resources *devr)
  1142. {
  1143. mlx5_ib_destroy_srq(devr->s1);
  1144. mlx5_ib_destroy_srq(devr->s0);
  1145. mlx5_ib_dealloc_xrcd(devr->x0);
  1146. mlx5_ib_dealloc_xrcd(devr->x1);
  1147. mlx5_ib_destroy_cq(devr->c0);
  1148. mlx5_ib_dealloc_pd(devr->p0);
  1149. }
  1150. static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
  1151. struct ib_port_immutable *immutable)
  1152. {
  1153. struct ib_port_attr attr;
  1154. int err;
  1155. err = mlx5_ib_query_port(ibdev, port_num, &attr);
  1156. if (err)
  1157. return err;
  1158. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  1159. immutable->gid_tbl_len = attr.gid_tbl_len;
  1160. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
  1161. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  1162. return 0;
  1163. }
  1164. static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
  1165. {
  1166. struct mlx5_ib_dev *dev;
  1167. int err;
  1168. int i;
  1169. /* don't create IB instance over Eth ports, no RoCE yet! */
  1170. if (MLX5_CAP_GEN(mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
  1171. return NULL;
  1172. printk_once(KERN_INFO "%s", mlx5_version);
  1173. dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
  1174. if (!dev)
  1175. return NULL;
  1176. dev->mdev = mdev;
  1177. err = get_port_caps(dev);
  1178. if (err)
  1179. goto err_dealloc;
  1180. if (mlx5_use_mad_ifc(dev))
  1181. get_ext_port_caps(dev);
  1182. MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock);
  1183. strlcpy(dev->ib_dev.name, "mlx5_%d", IB_DEVICE_NAME_MAX);
  1184. dev->ib_dev.owner = THIS_MODULE;
  1185. dev->ib_dev.node_type = RDMA_NODE_IB_CA;
  1186. dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
  1187. dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
  1188. dev->ib_dev.phys_port_cnt = dev->num_ports;
  1189. dev->ib_dev.num_comp_vectors =
  1190. dev->mdev->priv.eq_table.num_comp_vectors;
  1191. dev->ib_dev.dma_device = &mdev->pdev->dev;
  1192. dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
  1193. dev->ib_dev.uverbs_cmd_mask =
  1194. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  1195. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  1196. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  1197. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  1198. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  1199. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  1200. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  1201. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  1202. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  1203. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  1204. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  1205. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  1206. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  1207. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  1208. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  1209. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  1210. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  1211. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  1212. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  1213. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  1214. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  1215. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  1216. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  1217. dev->ib_dev.uverbs_ex_cmd_mask =
  1218. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
  1219. dev->ib_dev.query_device = mlx5_ib_query_device;
  1220. dev->ib_dev.query_port = mlx5_ib_query_port;
  1221. dev->ib_dev.query_gid = mlx5_ib_query_gid;
  1222. dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
  1223. dev->ib_dev.modify_device = mlx5_ib_modify_device;
  1224. dev->ib_dev.modify_port = mlx5_ib_modify_port;
  1225. dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
  1226. dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
  1227. dev->ib_dev.mmap = mlx5_ib_mmap;
  1228. dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
  1229. dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
  1230. dev->ib_dev.create_ah = mlx5_ib_create_ah;
  1231. dev->ib_dev.query_ah = mlx5_ib_query_ah;
  1232. dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
  1233. dev->ib_dev.create_srq = mlx5_ib_create_srq;
  1234. dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
  1235. dev->ib_dev.query_srq = mlx5_ib_query_srq;
  1236. dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
  1237. dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
  1238. dev->ib_dev.create_qp = mlx5_ib_create_qp;
  1239. dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
  1240. dev->ib_dev.query_qp = mlx5_ib_query_qp;
  1241. dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
  1242. dev->ib_dev.post_send = mlx5_ib_post_send;
  1243. dev->ib_dev.post_recv = mlx5_ib_post_recv;
  1244. dev->ib_dev.create_cq = mlx5_ib_create_cq;
  1245. dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
  1246. dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
  1247. dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
  1248. dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
  1249. dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
  1250. dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
  1251. dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
  1252. dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
  1253. dev->ib_dev.destroy_mr = mlx5_ib_destroy_mr;
  1254. dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
  1255. dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
  1256. dev->ib_dev.process_mad = mlx5_ib_process_mad;
  1257. dev->ib_dev.create_mr = mlx5_ib_create_mr;
  1258. dev->ib_dev.alloc_fast_reg_mr = mlx5_ib_alloc_fast_reg_mr;
  1259. dev->ib_dev.alloc_fast_reg_page_list = mlx5_ib_alloc_fast_reg_page_list;
  1260. dev->ib_dev.free_fast_reg_page_list = mlx5_ib_free_fast_reg_page_list;
  1261. dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
  1262. dev->ib_dev.get_port_immutable = mlx5_port_immutable;
  1263. mlx5_ib_internal_fill_odp_caps(dev);
  1264. if (MLX5_CAP_GEN(mdev, xrc)) {
  1265. dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
  1266. dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
  1267. dev->ib_dev.uverbs_cmd_mask |=
  1268. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  1269. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  1270. }
  1271. err = init_node_data(dev);
  1272. if (err)
  1273. goto err_dealloc;
  1274. mutex_init(&dev->cap_mask_mutex);
  1275. err = create_dev_resources(&dev->devr);
  1276. if (err)
  1277. goto err_dealloc;
  1278. err = mlx5_ib_odp_init_one(dev);
  1279. if (err)
  1280. goto err_rsrc;
  1281. err = ib_register_device(&dev->ib_dev, NULL);
  1282. if (err)
  1283. goto err_odp;
  1284. err = create_umr_res(dev);
  1285. if (err)
  1286. goto err_dev;
  1287. for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
  1288. err = device_create_file(&dev->ib_dev.dev,
  1289. mlx5_class_attributes[i]);
  1290. if (err)
  1291. goto err_umrc;
  1292. }
  1293. dev->ib_active = true;
  1294. return dev;
  1295. err_umrc:
  1296. destroy_umrc_res(dev);
  1297. err_dev:
  1298. ib_unregister_device(&dev->ib_dev);
  1299. err_odp:
  1300. mlx5_ib_odp_remove_one(dev);
  1301. err_rsrc:
  1302. destroy_dev_resources(&dev->devr);
  1303. err_dealloc:
  1304. ib_dealloc_device((struct ib_device *)dev);
  1305. return NULL;
  1306. }
  1307. static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
  1308. {
  1309. struct mlx5_ib_dev *dev = context;
  1310. ib_unregister_device(&dev->ib_dev);
  1311. destroy_umrc_res(dev);
  1312. mlx5_ib_odp_remove_one(dev);
  1313. destroy_dev_resources(&dev->devr);
  1314. ib_dealloc_device(&dev->ib_dev);
  1315. }
  1316. static struct mlx5_interface mlx5_ib_interface = {
  1317. .add = mlx5_ib_add,
  1318. .remove = mlx5_ib_remove,
  1319. .event = mlx5_ib_event,
  1320. .protocol = MLX5_INTERFACE_PROTOCOL_IB,
  1321. };
  1322. static int __init mlx5_ib_init(void)
  1323. {
  1324. int err;
  1325. if (deprecated_prof_sel != 2)
  1326. pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
  1327. err = mlx5_ib_odp_init();
  1328. if (err)
  1329. return err;
  1330. err = mlx5_register_interface(&mlx5_ib_interface);
  1331. if (err)
  1332. goto clean_odp;
  1333. return err;
  1334. clean_odp:
  1335. mlx5_ib_odp_cleanup();
  1336. return err;
  1337. }
  1338. static void __exit mlx5_ib_cleanup(void)
  1339. {
  1340. mlx5_unregister_interface(&mlx5_ib_interface);
  1341. mlx5_ib_odp_cleanup();
  1342. }
  1343. module_init(mlx5_ib_init);
  1344. module_exit(mlx5_ib_cleanup);