c2.c 33 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242
  1. /*
  2. * Copyright (c) 2005 Ammasso, Inc. All rights reserved.
  3. * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/pci.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/etherdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/delay.h>
  41. #include <linux/ethtool.h>
  42. #include <linux/mii.h>
  43. #include <linux/if_vlan.h>
  44. #include <linux/crc32.h>
  45. #include <linux/in.h>
  46. #include <linux/ip.h>
  47. #include <linux/tcp.h>
  48. #include <linux/init.h>
  49. #include <linux/dma-mapping.h>
  50. #include <linux/slab.h>
  51. #include <linux/prefetch.h>
  52. #include <asm/io.h>
  53. #include <asm/irq.h>
  54. #include <asm/byteorder.h>
  55. #include <rdma/ib_smi.h>
  56. #include "c2.h"
  57. #include "c2_provider.h"
  58. MODULE_AUTHOR("Tom Tucker <tom@opengridcomputing.com>");
  59. MODULE_DESCRIPTION("Ammasso AMSO1100 Low-level iWARP Driver");
  60. MODULE_LICENSE("Dual BSD/GPL");
  61. MODULE_VERSION(DRV_VERSION);
  62. static const u32 default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  63. | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  64. static int debug = -1; /* defaults above */
  65. module_param(debug, int, 0);
  66. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  67. static int c2_up(struct net_device *netdev);
  68. static int c2_down(struct net_device *netdev);
  69. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  70. static void c2_tx_interrupt(struct net_device *netdev);
  71. static void c2_rx_interrupt(struct net_device *netdev);
  72. static irqreturn_t c2_interrupt(int irq, void *dev_id);
  73. static void c2_tx_timeout(struct net_device *netdev);
  74. static int c2_change_mtu(struct net_device *netdev, int new_mtu);
  75. static void c2_reset(struct c2_port *c2_port);
  76. static struct pci_device_id c2_pci_table[] = {
  77. { PCI_DEVICE(0x18b8, 0xb001) },
  78. { 0 }
  79. };
  80. MODULE_DEVICE_TABLE(pci, c2_pci_table);
  81. static void c2_print_macaddr(struct net_device *netdev)
  82. {
  83. pr_debug("%s: MAC %pM, IRQ %u\n", netdev->name, netdev->dev_addr, netdev->irq);
  84. }
  85. static void c2_set_rxbufsize(struct c2_port *c2_port)
  86. {
  87. struct net_device *netdev = c2_port->netdev;
  88. if (netdev->mtu > RX_BUF_SIZE)
  89. c2_port->rx_buf_size =
  90. netdev->mtu + ETH_HLEN + sizeof(struct c2_rxp_hdr) +
  91. NET_IP_ALIGN;
  92. else
  93. c2_port->rx_buf_size = sizeof(struct c2_rxp_hdr) + RX_BUF_SIZE;
  94. }
  95. /*
  96. * Allocate TX ring elements and chain them together.
  97. * One-to-one association of adapter descriptors with ring elements.
  98. */
  99. static int c2_tx_ring_alloc(struct c2_ring *tx_ring, void *vaddr,
  100. dma_addr_t base, void __iomem * mmio_txp_ring)
  101. {
  102. struct c2_tx_desc *tx_desc;
  103. struct c2_txp_desc __iomem *txp_desc;
  104. struct c2_element *elem;
  105. int i;
  106. tx_ring->start = kmalloc(sizeof(*elem) * tx_ring->count, GFP_KERNEL);
  107. if (!tx_ring->start)
  108. return -ENOMEM;
  109. elem = tx_ring->start;
  110. tx_desc = vaddr;
  111. txp_desc = mmio_txp_ring;
  112. for (i = 0; i < tx_ring->count; i++, elem++, tx_desc++, txp_desc++) {
  113. tx_desc->len = 0;
  114. tx_desc->status = 0;
  115. /* Set TXP_HTXD_UNINIT */
  116. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  117. (void __iomem *) txp_desc + C2_TXP_ADDR);
  118. __raw_writew(0, (void __iomem *) txp_desc + C2_TXP_LEN);
  119. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  120. (void __iomem *) txp_desc + C2_TXP_FLAGS);
  121. elem->skb = NULL;
  122. elem->ht_desc = tx_desc;
  123. elem->hw_desc = txp_desc;
  124. if (i == tx_ring->count - 1) {
  125. elem->next = tx_ring->start;
  126. tx_desc->next_offset = base;
  127. } else {
  128. elem->next = elem + 1;
  129. tx_desc->next_offset =
  130. base + (i + 1) * sizeof(*tx_desc);
  131. }
  132. }
  133. tx_ring->to_use = tx_ring->to_clean = tx_ring->start;
  134. return 0;
  135. }
  136. /*
  137. * Allocate RX ring elements and chain them together.
  138. * One-to-one association of adapter descriptors with ring elements.
  139. */
  140. static int c2_rx_ring_alloc(struct c2_ring *rx_ring, void *vaddr,
  141. dma_addr_t base, void __iomem * mmio_rxp_ring)
  142. {
  143. struct c2_rx_desc *rx_desc;
  144. struct c2_rxp_desc __iomem *rxp_desc;
  145. struct c2_element *elem;
  146. int i;
  147. rx_ring->start = kmalloc(sizeof(*elem) * rx_ring->count, GFP_KERNEL);
  148. if (!rx_ring->start)
  149. return -ENOMEM;
  150. elem = rx_ring->start;
  151. rx_desc = vaddr;
  152. rxp_desc = mmio_rxp_ring;
  153. for (i = 0; i < rx_ring->count; i++, elem++, rx_desc++, rxp_desc++) {
  154. rx_desc->len = 0;
  155. rx_desc->status = 0;
  156. /* Set RXP_HRXD_UNINIT */
  157. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_OK),
  158. (void __iomem *) rxp_desc + C2_RXP_STATUS);
  159. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_COUNT);
  160. __raw_writew(0, (void __iomem *) rxp_desc + C2_RXP_LEN);
  161. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  162. (void __iomem *) rxp_desc + C2_RXP_ADDR);
  163. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  164. (void __iomem *) rxp_desc + C2_RXP_FLAGS);
  165. elem->skb = NULL;
  166. elem->ht_desc = rx_desc;
  167. elem->hw_desc = rxp_desc;
  168. if (i == rx_ring->count - 1) {
  169. elem->next = rx_ring->start;
  170. rx_desc->next_offset = base;
  171. } else {
  172. elem->next = elem + 1;
  173. rx_desc->next_offset =
  174. base + (i + 1) * sizeof(*rx_desc);
  175. }
  176. }
  177. rx_ring->to_use = rx_ring->to_clean = rx_ring->start;
  178. return 0;
  179. }
  180. /* Setup buffer for receiving */
  181. static inline int c2_rx_alloc(struct c2_port *c2_port, struct c2_element *elem)
  182. {
  183. struct c2_dev *c2dev = c2_port->c2dev;
  184. struct c2_rx_desc *rx_desc = elem->ht_desc;
  185. struct sk_buff *skb;
  186. dma_addr_t mapaddr;
  187. u32 maplen;
  188. struct c2_rxp_hdr *rxp_hdr;
  189. skb = dev_alloc_skb(c2_port->rx_buf_size);
  190. if (unlikely(!skb)) {
  191. pr_debug("%s: out of memory for receive\n",
  192. c2_port->netdev->name);
  193. return -ENOMEM;
  194. }
  195. /* Zero out the rxp hdr in the sk_buff */
  196. memset(skb->data, 0, sizeof(*rxp_hdr));
  197. skb->dev = c2_port->netdev;
  198. maplen = c2_port->rx_buf_size;
  199. mapaddr =
  200. pci_map_single(c2dev->pcidev, skb->data, maplen,
  201. PCI_DMA_FROMDEVICE);
  202. /* Set the sk_buff RXP_header to RXP_HRXD_READY */
  203. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  204. rxp_hdr->flags = RXP_HRXD_READY;
  205. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  206. __raw_writew((__force u16) cpu_to_be16((u16) maplen - sizeof(*rxp_hdr)),
  207. elem->hw_desc + C2_RXP_LEN);
  208. __raw_writeq((__force u64) cpu_to_be64(mapaddr), elem->hw_desc + C2_RXP_ADDR);
  209. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  210. elem->hw_desc + C2_RXP_FLAGS);
  211. elem->skb = skb;
  212. elem->mapaddr = mapaddr;
  213. elem->maplen = maplen;
  214. rx_desc->len = maplen;
  215. return 0;
  216. }
  217. /*
  218. * Allocate buffers for the Rx ring
  219. * For receive: rx_ring.to_clean is next received frame
  220. */
  221. static int c2_rx_fill(struct c2_port *c2_port)
  222. {
  223. struct c2_ring *rx_ring = &c2_port->rx_ring;
  224. struct c2_element *elem;
  225. int ret = 0;
  226. elem = rx_ring->start;
  227. do {
  228. if (c2_rx_alloc(c2_port, elem)) {
  229. ret = 1;
  230. break;
  231. }
  232. } while ((elem = elem->next) != rx_ring->start);
  233. rx_ring->to_clean = rx_ring->start;
  234. return ret;
  235. }
  236. /* Free all buffers in RX ring, assumes receiver stopped */
  237. static void c2_rx_clean(struct c2_port *c2_port)
  238. {
  239. struct c2_dev *c2dev = c2_port->c2dev;
  240. struct c2_ring *rx_ring = &c2_port->rx_ring;
  241. struct c2_element *elem;
  242. struct c2_rx_desc *rx_desc;
  243. elem = rx_ring->start;
  244. do {
  245. rx_desc = elem->ht_desc;
  246. rx_desc->len = 0;
  247. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  248. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  249. __raw_writew(0, elem->hw_desc + C2_RXP_LEN);
  250. __raw_writeq((__force u64) cpu_to_be64(0x99aabbccddeeffULL),
  251. elem->hw_desc + C2_RXP_ADDR);
  252. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_UNINIT),
  253. elem->hw_desc + C2_RXP_FLAGS);
  254. if (elem->skb) {
  255. pci_unmap_single(c2dev->pcidev, elem->mapaddr,
  256. elem->maplen, PCI_DMA_FROMDEVICE);
  257. dev_kfree_skb(elem->skb);
  258. elem->skb = NULL;
  259. }
  260. } while ((elem = elem->next) != rx_ring->start);
  261. }
  262. static inline int c2_tx_free(struct c2_dev *c2dev, struct c2_element *elem)
  263. {
  264. struct c2_tx_desc *tx_desc = elem->ht_desc;
  265. tx_desc->len = 0;
  266. pci_unmap_single(c2dev->pcidev, elem->mapaddr, elem->maplen,
  267. PCI_DMA_TODEVICE);
  268. if (elem->skb) {
  269. dev_kfree_skb_any(elem->skb);
  270. elem->skb = NULL;
  271. }
  272. return 0;
  273. }
  274. /* Free all buffers in TX ring, assumes transmitter stopped */
  275. static void c2_tx_clean(struct c2_port *c2_port)
  276. {
  277. struct c2_ring *tx_ring = &c2_port->tx_ring;
  278. struct c2_element *elem;
  279. struct c2_txp_desc txp_htxd;
  280. int retry;
  281. unsigned long flags;
  282. spin_lock_irqsave(&c2_port->tx_lock, flags);
  283. elem = tx_ring->start;
  284. do {
  285. retry = 0;
  286. do {
  287. txp_htxd.flags =
  288. readw(elem->hw_desc + C2_TXP_FLAGS);
  289. if (txp_htxd.flags == TXP_HTXD_READY) {
  290. retry = 1;
  291. __raw_writew(0,
  292. elem->hw_desc + C2_TXP_LEN);
  293. __raw_writeq(0,
  294. elem->hw_desc + C2_TXP_ADDR);
  295. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_DONE),
  296. elem->hw_desc + C2_TXP_FLAGS);
  297. c2_port->netdev->stats.tx_dropped++;
  298. break;
  299. } else {
  300. __raw_writew(0,
  301. elem->hw_desc + C2_TXP_LEN);
  302. __raw_writeq((__force u64) cpu_to_be64(0x1122334455667788ULL),
  303. elem->hw_desc + C2_TXP_ADDR);
  304. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_UNINIT),
  305. elem->hw_desc + C2_TXP_FLAGS);
  306. }
  307. c2_tx_free(c2_port->c2dev, elem);
  308. } while ((elem = elem->next) != tx_ring->start);
  309. } while (retry);
  310. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  311. c2_port->c2dev->cur_tx = tx_ring->to_use - tx_ring->start;
  312. if (c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  313. netif_wake_queue(c2_port->netdev);
  314. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  315. }
  316. /*
  317. * Process transmit descriptors marked 'DONE' by the firmware,
  318. * freeing up their unneeded sk_buffs.
  319. */
  320. static void c2_tx_interrupt(struct net_device *netdev)
  321. {
  322. struct c2_port *c2_port = netdev_priv(netdev);
  323. struct c2_dev *c2dev = c2_port->c2dev;
  324. struct c2_ring *tx_ring = &c2_port->tx_ring;
  325. struct c2_element *elem;
  326. struct c2_txp_desc txp_htxd;
  327. spin_lock(&c2_port->tx_lock);
  328. for (elem = tx_ring->to_clean; elem != tx_ring->to_use;
  329. elem = elem->next) {
  330. txp_htxd.flags =
  331. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_FLAGS));
  332. if (txp_htxd.flags != TXP_HTXD_DONE)
  333. break;
  334. if (netif_msg_tx_done(c2_port)) {
  335. /* PCI reads are expensive in fast path */
  336. txp_htxd.len =
  337. be16_to_cpu((__force __be16) readw(elem->hw_desc + C2_TXP_LEN));
  338. pr_debug("%s: tx done slot %3Zu status 0x%x len "
  339. "%5u bytes\n",
  340. netdev->name, elem - tx_ring->start,
  341. txp_htxd.flags, txp_htxd.len);
  342. }
  343. c2_tx_free(c2dev, elem);
  344. ++(c2_port->tx_avail);
  345. }
  346. tx_ring->to_clean = elem;
  347. if (netif_queue_stopped(netdev)
  348. && c2_port->tx_avail > MAX_SKB_FRAGS + 1)
  349. netif_wake_queue(netdev);
  350. spin_unlock(&c2_port->tx_lock);
  351. }
  352. static void c2_rx_error(struct c2_port *c2_port, struct c2_element *elem)
  353. {
  354. struct c2_rx_desc *rx_desc = elem->ht_desc;
  355. struct c2_rxp_hdr *rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  356. if (rxp_hdr->status != RXP_HRXD_OK ||
  357. rxp_hdr->len > (rx_desc->len - sizeof(*rxp_hdr))) {
  358. pr_debug("BAD RXP_HRXD\n");
  359. pr_debug(" rx_desc : %p\n", rx_desc);
  360. pr_debug(" index : %Zu\n",
  361. elem - c2_port->rx_ring.start);
  362. pr_debug(" len : %u\n", rx_desc->len);
  363. pr_debug(" rxp_hdr : %p [PA %p]\n", rxp_hdr,
  364. (void *) __pa((unsigned long) rxp_hdr));
  365. pr_debug(" flags : 0x%x\n", rxp_hdr->flags);
  366. pr_debug(" status: 0x%x\n", rxp_hdr->status);
  367. pr_debug(" len : %u\n", rxp_hdr->len);
  368. pr_debug(" rsvd : 0x%x\n", rxp_hdr->rsvd);
  369. }
  370. /* Setup the skb for reuse since we're dropping this pkt */
  371. elem->skb->data = elem->skb->head;
  372. skb_reset_tail_pointer(elem->skb);
  373. /* Zero out the rxp hdr in the sk_buff */
  374. memset(elem->skb->data, 0, sizeof(*rxp_hdr));
  375. /* Write the descriptor to the adapter's rx ring */
  376. __raw_writew(0, elem->hw_desc + C2_RXP_STATUS);
  377. __raw_writew(0, elem->hw_desc + C2_RXP_COUNT);
  378. __raw_writew((__force u16) cpu_to_be16((u16) elem->maplen - sizeof(*rxp_hdr)),
  379. elem->hw_desc + C2_RXP_LEN);
  380. __raw_writeq((__force u64) cpu_to_be64(elem->mapaddr),
  381. elem->hw_desc + C2_RXP_ADDR);
  382. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  383. elem->hw_desc + C2_RXP_FLAGS);
  384. pr_debug("packet dropped\n");
  385. c2_port->netdev->stats.rx_dropped++;
  386. }
  387. static void c2_rx_interrupt(struct net_device *netdev)
  388. {
  389. struct c2_port *c2_port = netdev_priv(netdev);
  390. struct c2_dev *c2dev = c2_port->c2dev;
  391. struct c2_ring *rx_ring = &c2_port->rx_ring;
  392. struct c2_element *elem;
  393. struct c2_rx_desc *rx_desc;
  394. struct c2_rxp_hdr *rxp_hdr;
  395. struct sk_buff *skb;
  396. dma_addr_t mapaddr;
  397. u32 maplen, buflen;
  398. unsigned long flags;
  399. spin_lock_irqsave(&c2dev->lock, flags);
  400. /* Begin where we left off */
  401. rx_ring->to_clean = rx_ring->start + c2dev->cur_rx;
  402. for (elem = rx_ring->to_clean; elem->next != rx_ring->to_clean;
  403. elem = elem->next) {
  404. rx_desc = elem->ht_desc;
  405. mapaddr = elem->mapaddr;
  406. maplen = elem->maplen;
  407. skb = elem->skb;
  408. rxp_hdr = (struct c2_rxp_hdr *) skb->data;
  409. if (rxp_hdr->flags != RXP_HRXD_DONE)
  410. break;
  411. buflen = rxp_hdr->len;
  412. /* Sanity check the RXP header */
  413. if (rxp_hdr->status != RXP_HRXD_OK ||
  414. buflen > (rx_desc->len - sizeof(*rxp_hdr))) {
  415. c2_rx_error(c2_port, elem);
  416. continue;
  417. }
  418. /*
  419. * Allocate and map a new skb for replenishing the host
  420. * RX desc
  421. */
  422. if (c2_rx_alloc(c2_port, elem)) {
  423. c2_rx_error(c2_port, elem);
  424. continue;
  425. }
  426. /* Unmap the old skb */
  427. pci_unmap_single(c2dev->pcidev, mapaddr, maplen,
  428. PCI_DMA_FROMDEVICE);
  429. prefetch(skb->data);
  430. /*
  431. * Skip past the leading 8 bytes comprising of the
  432. * "struct c2_rxp_hdr", prepended by the adapter
  433. * to the usual Ethernet header ("struct ethhdr"),
  434. * to the start of the raw Ethernet packet.
  435. *
  436. * Fix up the various fields in the sk_buff before
  437. * passing it up to netif_rx(). The transfer size
  438. * (in bytes) specified by the adapter len field of
  439. * the "struct rxp_hdr_t" does NOT include the
  440. * "sizeof(struct c2_rxp_hdr)".
  441. */
  442. skb->data += sizeof(*rxp_hdr);
  443. skb_set_tail_pointer(skb, buflen);
  444. skb->len = buflen;
  445. skb->protocol = eth_type_trans(skb, netdev);
  446. netif_rx(skb);
  447. netdev->stats.rx_packets++;
  448. netdev->stats.rx_bytes += buflen;
  449. }
  450. /* Save where we left off */
  451. rx_ring->to_clean = elem;
  452. c2dev->cur_rx = elem - rx_ring->start;
  453. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  454. spin_unlock_irqrestore(&c2dev->lock, flags);
  455. }
  456. /*
  457. * Handle netisr0 TX & RX interrupts.
  458. */
  459. static irqreturn_t c2_interrupt(int irq, void *dev_id)
  460. {
  461. unsigned int netisr0, dmaisr;
  462. int handled = 0;
  463. struct c2_dev *c2dev = (struct c2_dev *) dev_id;
  464. /* Process CCILNET interrupts */
  465. netisr0 = readl(c2dev->regs + C2_NISR0);
  466. if (netisr0) {
  467. /*
  468. * There is an issue with the firmware that always
  469. * provides the status of RX for both TX & RX
  470. * interrupts. So process both queues here.
  471. */
  472. c2_rx_interrupt(c2dev->netdev);
  473. c2_tx_interrupt(c2dev->netdev);
  474. /* Clear the interrupt */
  475. writel(netisr0, c2dev->regs + C2_NISR0);
  476. handled++;
  477. }
  478. /* Process RNIC interrupts */
  479. dmaisr = readl(c2dev->regs + C2_DISR);
  480. if (dmaisr) {
  481. writel(dmaisr, c2dev->regs + C2_DISR);
  482. c2_rnic_interrupt(c2dev);
  483. handled++;
  484. }
  485. if (handled) {
  486. return IRQ_HANDLED;
  487. } else {
  488. return IRQ_NONE;
  489. }
  490. }
  491. static int c2_up(struct net_device *netdev)
  492. {
  493. struct c2_port *c2_port = netdev_priv(netdev);
  494. struct c2_dev *c2dev = c2_port->c2dev;
  495. struct c2_element *elem;
  496. struct c2_rxp_hdr *rxp_hdr;
  497. struct in_device *in_dev;
  498. size_t rx_size, tx_size;
  499. int ret, i;
  500. unsigned int netimr0;
  501. if (netif_msg_ifup(c2_port))
  502. pr_debug("%s: enabling interface\n", netdev->name);
  503. /* Set the Rx buffer size based on MTU */
  504. c2_set_rxbufsize(c2_port);
  505. /* Allocate DMA'able memory for Tx/Rx host descriptor rings */
  506. rx_size = c2_port->rx_ring.count * sizeof(struct c2_rx_desc);
  507. tx_size = c2_port->tx_ring.count * sizeof(struct c2_tx_desc);
  508. c2_port->mem_size = tx_size + rx_size;
  509. c2_port->mem = pci_zalloc_consistent(c2dev->pcidev, c2_port->mem_size,
  510. &c2_port->dma);
  511. if (c2_port->mem == NULL) {
  512. pr_debug("Unable to allocate memory for "
  513. "host descriptor rings\n");
  514. return -ENOMEM;
  515. }
  516. /* Create the Rx host descriptor ring */
  517. if ((ret =
  518. c2_rx_ring_alloc(&c2_port->rx_ring, c2_port->mem, c2_port->dma,
  519. c2dev->mmio_rxp_ring))) {
  520. pr_debug("Unable to create RX ring\n");
  521. goto bail0;
  522. }
  523. /* Allocate Rx buffers for the host descriptor ring */
  524. if (c2_rx_fill(c2_port)) {
  525. pr_debug("Unable to fill RX ring\n");
  526. goto bail1;
  527. }
  528. /* Create the Tx host descriptor ring */
  529. if ((ret = c2_tx_ring_alloc(&c2_port->tx_ring, c2_port->mem + rx_size,
  530. c2_port->dma + rx_size,
  531. c2dev->mmio_txp_ring))) {
  532. pr_debug("Unable to create TX ring\n");
  533. goto bail1;
  534. }
  535. /* Set the TX pointer to where we left off */
  536. c2_port->tx_avail = c2_port->tx_ring.count - 1;
  537. c2_port->tx_ring.to_use = c2_port->tx_ring.to_clean =
  538. c2_port->tx_ring.start + c2dev->cur_tx;
  539. /* missing: Initialize MAC */
  540. BUG_ON(c2_port->tx_ring.to_use != c2_port->tx_ring.to_clean);
  541. /* Reset the adapter, ensures the driver is in sync with the RXP */
  542. c2_reset(c2_port);
  543. /* Reset the READY bit in the sk_buff RXP headers & adapter HRXDQ */
  544. for (i = 0, elem = c2_port->rx_ring.start; i < c2_port->rx_ring.count;
  545. i++, elem++) {
  546. rxp_hdr = (struct c2_rxp_hdr *) elem->skb->data;
  547. rxp_hdr->flags = 0;
  548. __raw_writew((__force u16) cpu_to_be16(RXP_HRXD_READY),
  549. elem->hw_desc + C2_RXP_FLAGS);
  550. }
  551. /* Enable network packets */
  552. netif_start_queue(netdev);
  553. /* Enable IRQ */
  554. writel(0, c2dev->regs + C2_IDIS);
  555. netimr0 = readl(c2dev->regs + C2_NIMR0);
  556. netimr0 &= ~(C2_PCI_HTX_INT | C2_PCI_HRX_INT);
  557. writel(netimr0, c2dev->regs + C2_NIMR0);
  558. /* Tell the stack to ignore arp requests for ipaddrs bound to
  559. * other interfaces. This is needed to prevent the host stack
  560. * from responding to arp requests to the ipaddr bound on the
  561. * rdma interface.
  562. */
  563. in_dev = in_dev_get(netdev);
  564. IN_DEV_CONF_SET(in_dev, ARP_IGNORE, 1);
  565. in_dev_put(in_dev);
  566. return 0;
  567. bail1:
  568. c2_rx_clean(c2_port);
  569. kfree(c2_port->rx_ring.start);
  570. bail0:
  571. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  572. c2_port->dma);
  573. return ret;
  574. }
  575. static int c2_down(struct net_device *netdev)
  576. {
  577. struct c2_port *c2_port = netdev_priv(netdev);
  578. struct c2_dev *c2dev = c2_port->c2dev;
  579. if (netif_msg_ifdown(c2_port))
  580. pr_debug("%s: disabling interface\n",
  581. netdev->name);
  582. /* Wait for all the queued packets to get sent */
  583. c2_tx_interrupt(netdev);
  584. /* Disable network packets */
  585. netif_stop_queue(netdev);
  586. /* Disable IRQs by clearing the interrupt mask */
  587. writel(1, c2dev->regs + C2_IDIS);
  588. writel(0, c2dev->regs + C2_NIMR0);
  589. /* missing: Stop transmitter */
  590. /* missing: Stop receiver */
  591. /* Reset the adapter, ensures the driver is in sync with the RXP */
  592. c2_reset(c2_port);
  593. /* missing: Turn off LEDs here */
  594. /* Free all buffers in the host descriptor rings */
  595. c2_tx_clean(c2_port);
  596. c2_rx_clean(c2_port);
  597. /* Free the host descriptor rings */
  598. kfree(c2_port->rx_ring.start);
  599. kfree(c2_port->tx_ring.start);
  600. pci_free_consistent(c2dev->pcidev, c2_port->mem_size, c2_port->mem,
  601. c2_port->dma);
  602. return 0;
  603. }
  604. static void c2_reset(struct c2_port *c2_port)
  605. {
  606. struct c2_dev *c2dev = c2_port->c2dev;
  607. unsigned int cur_rx = c2dev->cur_rx;
  608. /* Tell the hardware to quiesce */
  609. C2_SET_CUR_RX(c2dev, cur_rx | C2_PCI_HRX_QUI);
  610. /*
  611. * The hardware will reset the C2_PCI_HRX_QUI bit once
  612. * the RXP is quiesced. Wait 2 seconds for this.
  613. */
  614. ssleep(2);
  615. cur_rx = C2_GET_CUR_RX(c2dev);
  616. if (cur_rx & C2_PCI_HRX_QUI)
  617. pr_debug("c2_reset: failed to quiesce the hardware!\n");
  618. cur_rx &= ~C2_PCI_HRX_QUI;
  619. c2dev->cur_rx = cur_rx;
  620. pr_debug("Current RX: %u\n", c2dev->cur_rx);
  621. }
  622. static int c2_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
  623. {
  624. struct c2_port *c2_port = netdev_priv(netdev);
  625. struct c2_dev *c2dev = c2_port->c2dev;
  626. struct c2_ring *tx_ring = &c2_port->tx_ring;
  627. struct c2_element *elem;
  628. dma_addr_t mapaddr;
  629. u32 maplen;
  630. unsigned long flags;
  631. unsigned int i;
  632. spin_lock_irqsave(&c2_port->tx_lock, flags);
  633. if (unlikely(c2_port->tx_avail < (skb_shinfo(skb)->nr_frags + 1))) {
  634. netif_stop_queue(netdev);
  635. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  636. pr_debug("%s: Tx ring full when queue awake!\n",
  637. netdev->name);
  638. return NETDEV_TX_BUSY;
  639. }
  640. maplen = skb_headlen(skb);
  641. mapaddr =
  642. pci_map_single(c2dev->pcidev, skb->data, maplen, PCI_DMA_TODEVICE);
  643. elem = tx_ring->to_use;
  644. elem->skb = skb;
  645. elem->mapaddr = mapaddr;
  646. elem->maplen = maplen;
  647. /* Tell HW to xmit */
  648. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  649. elem->hw_desc + C2_TXP_ADDR);
  650. __raw_writew((__force u16) cpu_to_be16(maplen),
  651. elem->hw_desc + C2_TXP_LEN);
  652. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  653. elem->hw_desc + C2_TXP_FLAGS);
  654. netdev->stats.tx_packets++;
  655. netdev->stats.tx_bytes += maplen;
  656. /* Loop thru additional data fragments and queue them */
  657. if (skb_shinfo(skb)->nr_frags) {
  658. for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  659. const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  660. maplen = skb_frag_size(frag);
  661. mapaddr = skb_frag_dma_map(&c2dev->pcidev->dev, frag,
  662. 0, maplen, DMA_TO_DEVICE);
  663. elem = elem->next;
  664. elem->skb = NULL;
  665. elem->mapaddr = mapaddr;
  666. elem->maplen = maplen;
  667. /* Tell HW to xmit */
  668. __raw_writeq((__force u64) cpu_to_be64(mapaddr),
  669. elem->hw_desc + C2_TXP_ADDR);
  670. __raw_writew((__force u16) cpu_to_be16(maplen),
  671. elem->hw_desc + C2_TXP_LEN);
  672. __raw_writew((__force u16) cpu_to_be16(TXP_HTXD_READY),
  673. elem->hw_desc + C2_TXP_FLAGS);
  674. netdev->stats.tx_packets++;
  675. netdev->stats.tx_bytes += maplen;
  676. }
  677. }
  678. tx_ring->to_use = elem->next;
  679. c2_port->tx_avail -= (skb_shinfo(skb)->nr_frags + 1);
  680. if (c2_port->tx_avail <= MAX_SKB_FRAGS + 1) {
  681. netif_stop_queue(netdev);
  682. if (netif_msg_tx_queued(c2_port))
  683. pr_debug("%s: transmit queue full\n",
  684. netdev->name);
  685. }
  686. spin_unlock_irqrestore(&c2_port->tx_lock, flags);
  687. netdev->trans_start = jiffies;
  688. return NETDEV_TX_OK;
  689. }
  690. static void c2_tx_timeout(struct net_device *netdev)
  691. {
  692. struct c2_port *c2_port = netdev_priv(netdev);
  693. if (netif_msg_timer(c2_port))
  694. pr_debug("%s: tx timeout\n", netdev->name);
  695. c2_tx_clean(c2_port);
  696. }
  697. static int c2_change_mtu(struct net_device *netdev, int new_mtu)
  698. {
  699. int ret = 0;
  700. if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
  701. return -EINVAL;
  702. netdev->mtu = new_mtu;
  703. if (netif_running(netdev)) {
  704. c2_down(netdev);
  705. c2_up(netdev);
  706. }
  707. return ret;
  708. }
  709. static const struct net_device_ops c2_netdev = {
  710. .ndo_open = c2_up,
  711. .ndo_stop = c2_down,
  712. .ndo_start_xmit = c2_xmit_frame,
  713. .ndo_tx_timeout = c2_tx_timeout,
  714. .ndo_change_mtu = c2_change_mtu,
  715. .ndo_set_mac_address = eth_mac_addr,
  716. .ndo_validate_addr = eth_validate_addr,
  717. };
  718. /* Initialize network device */
  719. static struct net_device *c2_devinit(struct c2_dev *c2dev,
  720. void __iomem * mmio_addr)
  721. {
  722. struct c2_port *c2_port = NULL;
  723. struct net_device *netdev = alloc_etherdev(sizeof(*c2_port));
  724. if (!netdev) {
  725. pr_debug("c2_port etherdev alloc failed");
  726. return NULL;
  727. }
  728. SET_NETDEV_DEV(netdev, &c2dev->pcidev->dev);
  729. netdev->netdev_ops = &c2_netdev;
  730. netdev->watchdog_timeo = C2_TX_TIMEOUT;
  731. netdev->irq = c2dev->pcidev->irq;
  732. c2_port = netdev_priv(netdev);
  733. c2_port->netdev = netdev;
  734. c2_port->c2dev = c2dev;
  735. c2_port->msg_enable = netif_msg_init(debug, default_msg);
  736. c2_port->tx_ring.count = C2_NUM_TX_DESC;
  737. c2_port->rx_ring.count = C2_NUM_RX_DESC;
  738. spin_lock_init(&c2_port->tx_lock);
  739. /* Copy our 48-bit ethernet hardware address */
  740. memcpy_fromio(netdev->dev_addr, mmio_addr + C2_REGS_ENADDR, 6);
  741. /* Validate the MAC address */
  742. if (!is_valid_ether_addr(netdev->dev_addr)) {
  743. pr_debug("Invalid MAC Address\n");
  744. c2_print_macaddr(netdev);
  745. free_netdev(netdev);
  746. return NULL;
  747. }
  748. c2dev->netdev = netdev;
  749. return netdev;
  750. }
  751. static int c2_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
  752. {
  753. int ret = 0, i;
  754. unsigned long reg0_start, reg0_flags, reg0_len;
  755. unsigned long reg2_start, reg2_flags, reg2_len;
  756. unsigned long reg4_start, reg4_flags, reg4_len;
  757. unsigned kva_map_size;
  758. struct net_device *netdev = NULL;
  759. struct c2_dev *c2dev = NULL;
  760. void __iomem *mmio_regs = NULL;
  761. printk(KERN_INFO PFX "AMSO1100 Gigabit Ethernet driver v%s loaded\n",
  762. DRV_VERSION);
  763. /* Enable PCI device */
  764. ret = pci_enable_device(pcidev);
  765. if (ret) {
  766. printk(KERN_ERR PFX "%s: Unable to enable PCI device\n",
  767. pci_name(pcidev));
  768. goto bail0;
  769. }
  770. reg0_start = pci_resource_start(pcidev, BAR_0);
  771. reg0_len = pci_resource_len(pcidev, BAR_0);
  772. reg0_flags = pci_resource_flags(pcidev, BAR_0);
  773. reg2_start = pci_resource_start(pcidev, BAR_2);
  774. reg2_len = pci_resource_len(pcidev, BAR_2);
  775. reg2_flags = pci_resource_flags(pcidev, BAR_2);
  776. reg4_start = pci_resource_start(pcidev, BAR_4);
  777. reg4_len = pci_resource_len(pcidev, BAR_4);
  778. reg4_flags = pci_resource_flags(pcidev, BAR_4);
  779. pr_debug("BAR0 size = 0x%lX bytes\n", reg0_len);
  780. pr_debug("BAR2 size = 0x%lX bytes\n", reg2_len);
  781. pr_debug("BAR4 size = 0x%lX bytes\n", reg4_len);
  782. /* Make sure PCI base addr are MMIO */
  783. if (!(reg0_flags & IORESOURCE_MEM) ||
  784. !(reg2_flags & IORESOURCE_MEM) || !(reg4_flags & IORESOURCE_MEM)) {
  785. printk(KERN_ERR PFX "PCI regions not an MMIO resource\n");
  786. ret = -ENODEV;
  787. goto bail1;
  788. }
  789. /* Check for weird/broken PCI region reporting */
  790. if ((reg0_len < C2_REG0_SIZE) ||
  791. (reg2_len < C2_REG2_SIZE) || (reg4_len < C2_REG4_SIZE)) {
  792. printk(KERN_ERR PFX "Invalid PCI region sizes\n");
  793. ret = -ENODEV;
  794. goto bail1;
  795. }
  796. /* Reserve PCI I/O and memory resources */
  797. ret = pci_request_regions(pcidev, DRV_NAME);
  798. if (ret) {
  799. printk(KERN_ERR PFX "%s: Unable to request regions\n",
  800. pci_name(pcidev));
  801. goto bail1;
  802. }
  803. if ((sizeof(dma_addr_t) > 4)) {
  804. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
  805. if (ret < 0) {
  806. printk(KERN_ERR PFX "64b DMA configuration failed\n");
  807. goto bail2;
  808. }
  809. } else {
  810. ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
  811. if (ret < 0) {
  812. printk(KERN_ERR PFX "32b DMA configuration failed\n");
  813. goto bail2;
  814. }
  815. }
  816. /* Enables bus-mastering on the device */
  817. pci_set_master(pcidev);
  818. /* Remap the adapter PCI registers in BAR4 */
  819. mmio_regs = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  820. sizeof(struct c2_adapter_pci_regs));
  821. if (!mmio_regs) {
  822. printk(KERN_ERR PFX
  823. "Unable to remap adapter PCI registers in BAR4\n");
  824. ret = -EIO;
  825. goto bail2;
  826. }
  827. /* Validate PCI regs magic */
  828. for (i = 0; i < sizeof(c2_magic); i++) {
  829. if (c2_magic[i] != readb(mmio_regs + C2_REGS_MAGIC + i)) {
  830. printk(KERN_ERR PFX "Downlevel Firmware boot loader "
  831. "[%d/%Zd: got 0x%x, exp 0x%x]. Use the cc_flash "
  832. "utility to update your boot loader\n",
  833. i + 1, sizeof(c2_magic),
  834. readb(mmio_regs + C2_REGS_MAGIC + i),
  835. c2_magic[i]);
  836. printk(KERN_ERR PFX "Adapter not claimed\n");
  837. iounmap(mmio_regs);
  838. ret = -EIO;
  839. goto bail2;
  840. }
  841. }
  842. /* Validate the adapter version */
  843. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)) != C2_VERSION) {
  844. printk(KERN_ERR PFX "Version mismatch "
  845. "[fw=%u, c2=%u], Adapter not claimed\n",
  846. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_VERS)),
  847. C2_VERSION);
  848. ret = -EINVAL;
  849. iounmap(mmio_regs);
  850. goto bail2;
  851. }
  852. /* Validate the adapter IVN */
  853. if (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)) != C2_IVN) {
  854. printk(KERN_ERR PFX "Downlevel FIrmware level. You should be using "
  855. "the OpenIB device support kit. "
  856. "[fw=0x%x, c2=0x%x], Adapter not claimed\n",
  857. be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_IVN)),
  858. C2_IVN);
  859. ret = -EINVAL;
  860. iounmap(mmio_regs);
  861. goto bail2;
  862. }
  863. /* Allocate hardware structure */
  864. c2dev = (struct c2_dev *) ib_alloc_device(sizeof(*c2dev));
  865. if (!c2dev) {
  866. printk(KERN_ERR PFX "%s: Unable to alloc hardware struct\n",
  867. pci_name(pcidev));
  868. ret = -ENOMEM;
  869. iounmap(mmio_regs);
  870. goto bail2;
  871. }
  872. memset(c2dev, 0, sizeof(*c2dev));
  873. spin_lock_init(&c2dev->lock);
  874. c2dev->pcidev = pcidev;
  875. c2dev->cur_tx = 0;
  876. /* Get the last RX index */
  877. c2dev->cur_rx =
  878. (be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_HRX_CUR)) -
  879. 0xffffc000) / sizeof(struct c2_rxp_desc);
  880. /* Request an interrupt line for the driver */
  881. ret = request_irq(pcidev->irq, c2_interrupt, IRQF_SHARED, DRV_NAME, c2dev);
  882. if (ret) {
  883. printk(KERN_ERR PFX "%s: requested IRQ %u is busy\n",
  884. pci_name(pcidev), pcidev->irq);
  885. iounmap(mmio_regs);
  886. goto bail3;
  887. }
  888. /* Set driver specific data */
  889. pci_set_drvdata(pcidev, c2dev);
  890. /* Initialize network device */
  891. if ((netdev = c2_devinit(c2dev, mmio_regs)) == NULL) {
  892. ret = -ENOMEM;
  893. iounmap(mmio_regs);
  894. goto bail4;
  895. }
  896. /* Save off the actual size prior to unmapping mmio_regs */
  897. kva_map_size = be32_to_cpu((__force __be32) readl(mmio_regs + C2_REGS_PCI_WINSIZE));
  898. /* Unmap the adapter PCI registers in BAR4 */
  899. iounmap(mmio_regs);
  900. /* Register network device */
  901. ret = register_netdev(netdev);
  902. if (ret) {
  903. printk(KERN_ERR PFX "Unable to register netdev, ret = %d\n",
  904. ret);
  905. goto bail5;
  906. }
  907. /* Disable network packets */
  908. netif_stop_queue(netdev);
  909. /* Remap the adapter HRXDQ PA space to kernel VA space */
  910. c2dev->mmio_rxp_ring = ioremap_nocache(reg4_start + C2_RXP_HRXDQ_OFFSET,
  911. C2_RXP_HRXDQ_SIZE);
  912. if (!c2dev->mmio_rxp_ring) {
  913. printk(KERN_ERR PFX "Unable to remap MMIO HRXDQ region\n");
  914. ret = -EIO;
  915. goto bail6;
  916. }
  917. /* Remap the adapter HTXDQ PA space to kernel VA space */
  918. c2dev->mmio_txp_ring = ioremap_nocache(reg4_start + C2_TXP_HTXDQ_OFFSET,
  919. C2_TXP_HTXDQ_SIZE);
  920. if (!c2dev->mmio_txp_ring) {
  921. printk(KERN_ERR PFX "Unable to remap MMIO HTXDQ region\n");
  922. ret = -EIO;
  923. goto bail7;
  924. }
  925. /* Save off the current RX index in the last 4 bytes of the TXP Ring */
  926. C2_SET_CUR_RX(c2dev, c2dev->cur_rx);
  927. /* Remap the PCI registers in adapter BAR0 to kernel VA space */
  928. c2dev->regs = ioremap_nocache(reg0_start, reg0_len);
  929. if (!c2dev->regs) {
  930. printk(KERN_ERR PFX "Unable to remap BAR0\n");
  931. ret = -EIO;
  932. goto bail8;
  933. }
  934. /* Remap the PCI registers in adapter BAR4 to kernel VA space */
  935. c2dev->pa = reg4_start + C2_PCI_REGS_OFFSET;
  936. c2dev->kva = ioremap_nocache(reg4_start + C2_PCI_REGS_OFFSET,
  937. kva_map_size);
  938. if (!c2dev->kva) {
  939. printk(KERN_ERR PFX "Unable to remap BAR4\n");
  940. ret = -EIO;
  941. goto bail9;
  942. }
  943. /* Print out the MAC address */
  944. c2_print_macaddr(netdev);
  945. ret = c2_rnic_init(c2dev);
  946. if (ret) {
  947. printk(KERN_ERR PFX "c2_rnic_init failed: %d\n", ret);
  948. goto bail10;
  949. }
  950. ret = c2_register_device(c2dev);
  951. if (ret)
  952. goto bail10;
  953. return 0;
  954. bail10:
  955. iounmap(c2dev->kva);
  956. bail9:
  957. iounmap(c2dev->regs);
  958. bail8:
  959. iounmap(c2dev->mmio_txp_ring);
  960. bail7:
  961. iounmap(c2dev->mmio_rxp_ring);
  962. bail6:
  963. unregister_netdev(netdev);
  964. bail5:
  965. free_netdev(netdev);
  966. bail4:
  967. free_irq(pcidev->irq, c2dev);
  968. bail3:
  969. ib_dealloc_device(&c2dev->ibdev);
  970. bail2:
  971. pci_release_regions(pcidev);
  972. bail1:
  973. pci_disable_device(pcidev);
  974. bail0:
  975. return ret;
  976. }
  977. static void c2_remove(struct pci_dev *pcidev)
  978. {
  979. struct c2_dev *c2dev = pci_get_drvdata(pcidev);
  980. struct net_device *netdev = c2dev->netdev;
  981. /* Unregister with OpenIB */
  982. c2_unregister_device(c2dev);
  983. /* Clean up the RNIC resources */
  984. c2_rnic_term(c2dev);
  985. /* Remove network device from the kernel */
  986. unregister_netdev(netdev);
  987. /* Free network device */
  988. free_netdev(netdev);
  989. /* Free the interrupt line */
  990. free_irq(pcidev->irq, c2dev);
  991. /* missing: Turn LEDs off here */
  992. /* Unmap adapter PA space */
  993. iounmap(c2dev->kva);
  994. iounmap(c2dev->regs);
  995. iounmap(c2dev->mmio_txp_ring);
  996. iounmap(c2dev->mmio_rxp_ring);
  997. /* Free the hardware structure */
  998. ib_dealloc_device(&c2dev->ibdev);
  999. /* Release reserved PCI I/O and memory resources */
  1000. pci_release_regions(pcidev);
  1001. /* Disable PCI device */
  1002. pci_disable_device(pcidev);
  1003. /* Clear driver specific data */
  1004. pci_set_drvdata(pcidev, NULL);
  1005. }
  1006. static struct pci_driver c2_pci_driver = {
  1007. .name = DRV_NAME,
  1008. .id_table = c2_pci_table,
  1009. .probe = c2_probe,
  1010. .remove = c2_remove,
  1011. };
  1012. module_pci_driver(c2_pci_driver);