slc90e66.c 4.8 KB

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  1. /*
  2. * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
  3. * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
  4. *
  5. * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
  6. * but this keeps the ISA-Bridge and slots alive.
  7. *
  8. */
  9. #include <linux/types.h>
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/pci.h>
  13. #include <linux/ide.h>
  14. #include <linux/init.h>
  15. #define DRV_NAME "slc90e66"
  16. static DEFINE_SPINLOCK(slc90e66_lock);
  17. static void slc90e66_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  18. {
  19. struct pci_dev *dev = to_pci_dev(hwif->dev);
  20. int is_slave = drive->dn & 1;
  21. int master_port = hwif->channel ? 0x42 : 0x40;
  22. int slave_port = 0x44;
  23. unsigned long flags;
  24. u16 master_data;
  25. u8 slave_data;
  26. int control = 0;
  27. const u8 pio = drive->pio_mode - XFER_PIO_0;
  28. /* ISP RTC */
  29. static const u8 timings[][2] = {
  30. { 0, 0 },
  31. { 0, 0 },
  32. { 1, 0 },
  33. { 2, 1 },
  34. { 2, 3 }, };
  35. spin_lock_irqsave(&slc90e66_lock, flags);
  36. pci_read_config_word(dev, master_port, &master_data);
  37. if (pio > 1)
  38. control |= 1; /* Programmable timing on */
  39. if (drive->media == ide_disk)
  40. control |= 4; /* Prefetch, post write */
  41. if (ide_pio_need_iordy(drive, pio))
  42. control |= 2; /* IORDY */
  43. if (is_slave) {
  44. master_data |= 0x4000;
  45. master_data &= ~0x0070;
  46. if (pio > 1) {
  47. /* Set PPE, IE and TIME */
  48. master_data |= control << 4;
  49. }
  50. pci_read_config_byte(dev, slave_port, &slave_data);
  51. slave_data &= hwif->channel ? 0x0f : 0xf0;
  52. slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
  53. (hwif->channel ? 4 : 0);
  54. } else {
  55. master_data &= ~0x3307;
  56. if (pio > 1) {
  57. /* enable PPE, IE and TIME */
  58. master_data |= control;
  59. }
  60. master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
  61. }
  62. pci_write_config_word(dev, master_port, master_data);
  63. if (is_slave)
  64. pci_write_config_byte(dev, slave_port, slave_data);
  65. spin_unlock_irqrestore(&slc90e66_lock, flags);
  66. }
  67. static void slc90e66_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  68. {
  69. struct pci_dev *dev = to_pci_dev(hwif->dev);
  70. u8 maslave = hwif->channel ? 0x42 : 0x40;
  71. int sitre = 0, a_speed = 7 << (drive->dn * 4);
  72. int u_speed = 0, u_flag = 1 << drive->dn;
  73. u16 reg4042, reg44, reg48, reg4a;
  74. const u8 speed = drive->dma_mode;
  75. pci_read_config_word(dev, maslave, &reg4042);
  76. sitre = (reg4042 & 0x4000) ? 1 : 0;
  77. pci_read_config_word(dev, 0x44, &reg44);
  78. pci_read_config_word(dev, 0x48, &reg48);
  79. pci_read_config_word(dev, 0x4a, &reg4a);
  80. if (speed >= XFER_UDMA_0) {
  81. u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
  82. if (!(reg48 & u_flag))
  83. pci_write_config_word(dev, 0x48, reg48|u_flag);
  84. if ((reg4a & a_speed) != u_speed) {
  85. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  86. pci_read_config_word(dev, 0x4a, &reg4a);
  87. pci_write_config_word(dev, 0x4a, reg4a|u_speed);
  88. }
  89. } else {
  90. const u8 mwdma_to_pio[] = { 0, 3, 4 };
  91. if (reg48 & u_flag)
  92. pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
  93. if (reg4a & a_speed)
  94. pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
  95. if (speed >= XFER_MW_DMA_0)
  96. drive->pio_mode =
  97. mwdma_to_pio[speed - XFER_MW_DMA_0] + XFER_PIO_0;
  98. else
  99. drive->pio_mode = XFER_PIO_2; /* for SWDMA2 */
  100. slc90e66_set_pio_mode(hwif, drive);
  101. }
  102. }
  103. static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
  104. {
  105. struct pci_dev *dev = to_pci_dev(hwif->dev);
  106. u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
  107. pci_read_config_byte(dev, 0x47, &reg47);
  108. /* bit[0(1)]: 0:80, 1:40 */
  109. return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
  110. }
  111. static const struct ide_port_ops slc90e66_port_ops = {
  112. .set_pio_mode = slc90e66_set_pio_mode,
  113. .set_dma_mode = slc90e66_set_dma_mode,
  114. .cable_detect = slc90e66_cable_detect,
  115. };
  116. static const struct ide_port_info slc90e66_chipset = {
  117. .name = DRV_NAME,
  118. .enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
  119. .port_ops = &slc90e66_port_ops,
  120. .pio_mask = ATA_PIO4,
  121. .swdma_mask = ATA_SWDMA2_ONLY,
  122. .mwdma_mask = ATA_MWDMA12_ONLY,
  123. .udma_mask = ATA_UDMA4,
  124. };
  125. static int slc90e66_init_one(struct pci_dev *dev,
  126. const struct pci_device_id *id)
  127. {
  128. return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
  129. }
  130. static const struct pci_device_id slc90e66_pci_tbl[] = {
  131. { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
  132. { 0, },
  133. };
  134. MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
  135. static struct pci_driver slc90e66_pci_driver = {
  136. .name = "SLC90e66_IDE",
  137. .id_table = slc90e66_pci_tbl,
  138. .probe = slc90e66_init_one,
  139. .remove = ide_pci_remove,
  140. .suspend = ide_pci_suspend,
  141. .resume = ide_pci_resume,
  142. };
  143. static int __init slc90e66_ide_init(void)
  144. {
  145. return ide_pci_register_driver(&slc90e66_pci_driver);
  146. }
  147. static void __exit slc90e66_ide_exit(void)
  148. {
  149. pci_unregister_driver(&slc90e66_pci_driver);
  150. }
  151. module_init(slc90e66_ide_init);
  152. module_exit(slc90e66_ide_exit);
  153. MODULE_AUTHOR("Andre Hedrick");
  154. MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
  155. MODULE_LICENSE("GPL");