radeon_gem.c 20 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <drm/drmP.h>
  29. #include <drm/radeon_drm.h>
  30. #include "radeon.h"
  31. void radeon_gem_object_free(struct drm_gem_object *gobj)
  32. {
  33. struct radeon_bo *robj = gem_to_radeon_bo(gobj);
  34. if (robj) {
  35. if (robj->gem_base.import_attach)
  36. drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg);
  37. radeon_bo_unref(&robj);
  38. }
  39. }
  40. int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size,
  41. int alignment, int initial_domain,
  42. u32 flags, bool kernel,
  43. struct drm_gem_object **obj)
  44. {
  45. struct radeon_bo *robj;
  46. unsigned long max_size;
  47. int r;
  48. *obj = NULL;
  49. /* At least align on page size */
  50. if (alignment < PAGE_SIZE) {
  51. alignment = PAGE_SIZE;
  52. }
  53. /* Maximum bo size is the unpinned gtt size since we use the gtt to
  54. * handle vram to system pool migrations.
  55. */
  56. max_size = rdev->mc.gtt_size - rdev->gart_pin_size;
  57. if (size > max_size) {
  58. DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n",
  59. size >> 20, max_size >> 20);
  60. return -ENOMEM;
  61. }
  62. retry:
  63. r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain,
  64. flags, NULL, NULL, &robj);
  65. if (r) {
  66. if (r != -ERESTARTSYS) {
  67. if (initial_domain == RADEON_GEM_DOMAIN_VRAM) {
  68. initial_domain |= RADEON_GEM_DOMAIN_GTT;
  69. goto retry;
  70. }
  71. DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
  72. size, initial_domain, alignment, r);
  73. }
  74. return r;
  75. }
  76. *obj = &robj->gem_base;
  77. robj->pid = task_pid_nr(current);
  78. mutex_lock(&rdev->gem.mutex);
  79. list_add_tail(&robj->list, &rdev->gem.objects);
  80. mutex_unlock(&rdev->gem.mutex);
  81. return 0;
  82. }
  83. static int radeon_gem_set_domain(struct drm_gem_object *gobj,
  84. uint32_t rdomain, uint32_t wdomain)
  85. {
  86. struct radeon_bo *robj;
  87. uint32_t domain;
  88. long r;
  89. /* FIXME: reeimplement */
  90. robj = gem_to_radeon_bo(gobj);
  91. /* work out where to validate the buffer to */
  92. domain = wdomain;
  93. if (!domain) {
  94. domain = rdomain;
  95. }
  96. if (!domain) {
  97. /* Do nothings */
  98. printk(KERN_WARNING "Set domain without domain !\n");
  99. return 0;
  100. }
  101. if (domain == RADEON_GEM_DOMAIN_CPU) {
  102. /* Asking for cpu access wait for object idle */
  103. r = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
  104. if (!r)
  105. r = -EBUSY;
  106. if (r < 0 && r != -EINTR) {
  107. printk(KERN_ERR "Failed to wait for object: %li\n", r);
  108. return r;
  109. }
  110. }
  111. return 0;
  112. }
  113. int radeon_gem_init(struct radeon_device *rdev)
  114. {
  115. INIT_LIST_HEAD(&rdev->gem.objects);
  116. return 0;
  117. }
  118. void radeon_gem_fini(struct radeon_device *rdev)
  119. {
  120. radeon_bo_force_delete(rdev);
  121. }
  122. /*
  123. * Call from drm_gem_handle_create which appear in both new and open ioctl
  124. * case.
  125. */
  126. int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv)
  127. {
  128. struct radeon_bo *rbo = gem_to_radeon_bo(obj);
  129. struct radeon_device *rdev = rbo->rdev;
  130. struct radeon_fpriv *fpriv = file_priv->driver_priv;
  131. struct radeon_vm *vm = &fpriv->vm;
  132. struct radeon_bo_va *bo_va;
  133. int r;
  134. if ((rdev->family < CHIP_CAYMAN) ||
  135. (!rdev->accel_working)) {
  136. return 0;
  137. }
  138. r = radeon_bo_reserve(rbo, false);
  139. if (r) {
  140. return r;
  141. }
  142. bo_va = radeon_vm_bo_find(vm, rbo);
  143. if (!bo_va) {
  144. bo_va = radeon_vm_bo_add(rdev, vm, rbo);
  145. } else {
  146. ++bo_va->ref_count;
  147. }
  148. radeon_bo_unreserve(rbo);
  149. return 0;
  150. }
  151. void radeon_gem_object_close(struct drm_gem_object *obj,
  152. struct drm_file *file_priv)
  153. {
  154. struct radeon_bo *rbo = gem_to_radeon_bo(obj);
  155. struct radeon_device *rdev = rbo->rdev;
  156. struct radeon_fpriv *fpriv = file_priv->driver_priv;
  157. struct radeon_vm *vm = &fpriv->vm;
  158. struct radeon_bo_va *bo_va;
  159. int r;
  160. if ((rdev->family < CHIP_CAYMAN) ||
  161. (!rdev->accel_working)) {
  162. return;
  163. }
  164. r = radeon_bo_reserve(rbo, true);
  165. if (r) {
  166. dev_err(rdev->dev, "leaking bo va because "
  167. "we fail to reserve bo (%d)\n", r);
  168. return;
  169. }
  170. bo_va = radeon_vm_bo_find(vm, rbo);
  171. if (bo_va) {
  172. if (--bo_va->ref_count == 0) {
  173. radeon_vm_bo_rmv(rdev, bo_va);
  174. }
  175. }
  176. radeon_bo_unreserve(rbo);
  177. }
  178. static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r)
  179. {
  180. if (r == -EDEADLK) {
  181. r = radeon_gpu_reset(rdev);
  182. if (!r)
  183. r = -EAGAIN;
  184. }
  185. return r;
  186. }
  187. /*
  188. * GEM ioctls.
  189. */
  190. int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
  191. struct drm_file *filp)
  192. {
  193. struct radeon_device *rdev = dev->dev_private;
  194. struct drm_radeon_gem_info *args = data;
  195. struct ttm_mem_type_manager *man;
  196. man = &rdev->mman.bdev.man[TTM_PL_VRAM];
  197. args->vram_size = rdev->mc.real_vram_size;
  198. args->vram_visible = (u64)man->size << PAGE_SHIFT;
  199. args->vram_visible -= rdev->vram_pin_size;
  200. args->gart_size = rdev->mc.gtt_size;
  201. args->gart_size -= rdev->gart_pin_size;
  202. return 0;
  203. }
  204. int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
  205. struct drm_file *filp)
  206. {
  207. /* TODO: implement */
  208. DRM_ERROR("unimplemented %s\n", __func__);
  209. return -ENOSYS;
  210. }
  211. int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
  212. struct drm_file *filp)
  213. {
  214. /* TODO: implement */
  215. DRM_ERROR("unimplemented %s\n", __func__);
  216. return -ENOSYS;
  217. }
  218. int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
  219. struct drm_file *filp)
  220. {
  221. struct radeon_device *rdev = dev->dev_private;
  222. struct drm_radeon_gem_create *args = data;
  223. struct drm_gem_object *gobj;
  224. uint32_t handle;
  225. int r;
  226. down_read(&rdev->exclusive_lock);
  227. /* create a gem object to contain this object in */
  228. args->size = roundup(args->size, PAGE_SIZE);
  229. r = radeon_gem_object_create(rdev, args->size, args->alignment,
  230. args->initial_domain, args->flags,
  231. false, &gobj);
  232. if (r) {
  233. up_read(&rdev->exclusive_lock);
  234. r = radeon_gem_handle_lockup(rdev, r);
  235. return r;
  236. }
  237. r = drm_gem_handle_create(filp, gobj, &handle);
  238. /* drop reference from allocate - handle holds it now */
  239. drm_gem_object_unreference_unlocked(gobj);
  240. if (r) {
  241. up_read(&rdev->exclusive_lock);
  242. r = radeon_gem_handle_lockup(rdev, r);
  243. return r;
  244. }
  245. args->handle = handle;
  246. up_read(&rdev->exclusive_lock);
  247. return 0;
  248. }
  249. int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data,
  250. struct drm_file *filp)
  251. {
  252. struct radeon_device *rdev = dev->dev_private;
  253. struct drm_radeon_gem_userptr *args = data;
  254. struct drm_gem_object *gobj;
  255. struct radeon_bo *bo;
  256. uint32_t handle;
  257. int r;
  258. if (offset_in_page(args->addr | args->size))
  259. return -EINVAL;
  260. /* reject unknown flag values */
  261. if (args->flags & ~(RADEON_GEM_USERPTR_READONLY |
  262. RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE |
  263. RADEON_GEM_USERPTR_REGISTER))
  264. return -EINVAL;
  265. if (args->flags & RADEON_GEM_USERPTR_READONLY) {
  266. /* readonly pages not tested on older hardware */
  267. if (rdev->family < CHIP_R600)
  268. return -EINVAL;
  269. } else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) ||
  270. !(args->flags & RADEON_GEM_USERPTR_REGISTER)) {
  271. /* if we want to write to it we must require anonymous
  272. memory and install a MMU notifier */
  273. return -EACCES;
  274. }
  275. down_read(&rdev->exclusive_lock);
  276. /* create a gem object to contain this object in */
  277. r = radeon_gem_object_create(rdev, args->size, 0,
  278. RADEON_GEM_DOMAIN_CPU, 0,
  279. false, &gobj);
  280. if (r)
  281. goto handle_lockup;
  282. bo = gem_to_radeon_bo(gobj);
  283. r = radeon_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
  284. if (r)
  285. goto release_object;
  286. if (args->flags & RADEON_GEM_USERPTR_REGISTER) {
  287. r = radeon_mn_register(bo, args->addr);
  288. if (r)
  289. goto release_object;
  290. }
  291. if (args->flags & RADEON_GEM_USERPTR_VALIDATE) {
  292. down_read(&current->mm->mmap_sem);
  293. r = radeon_bo_reserve(bo, true);
  294. if (r) {
  295. up_read(&current->mm->mmap_sem);
  296. goto release_object;
  297. }
  298. radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT);
  299. r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
  300. radeon_bo_unreserve(bo);
  301. up_read(&current->mm->mmap_sem);
  302. if (r)
  303. goto release_object;
  304. }
  305. r = drm_gem_handle_create(filp, gobj, &handle);
  306. /* drop reference from allocate - handle holds it now */
  307. drm_gem_object_unreference_unlocked(gobj);
  308. if (r)
  309. goto handle_lockup;
  310. args->handle = handle;
  311. up_read(&rdev->exclusive_lock);
  312. return 0;
  313. release_object:
  314. drm_gem_object_unreference_unlocked(gobj);
  315. handle_lockup:
  316. up_read(&rdev->exclusive_lock);
  317. r = radeon_gem_handle_lockup(rdev, r);
  318. return r;
  319. }
  320. int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
  321. struct drm_file *filp)
  322. {
  323. /* transition the BO to a domain -
  324. * just validate the BO into a certain domain */
  325. struct radeon_device *rdev = dev->dev_private;
  326. struct drm_radeon_gem_set_domain *args = data;
  327. struct drm_gem_object *gobj;
  328. struct radeon_bo *robj;
  329. int r;
  330. /* for now if someone requests domain CPU -
  331. * just make sure the buffer is finished with */
  332. down_read(&rdev->exclusive_lock);
  333. /* just do a BO wait for now */
  334. gobj = drm_gem_object_lookup(dev, filp, args->handle);
  335. if (gobj == NULL) {
  336. up_read(&rdev->exclusive_lock);
  337. return -ENOENT;
  338. }
  339. robj = gem_to_radeon_bo(gobj);
  340. r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain);
  341. drm_gem_object_unreference_unlocked(gobj);
  342. up_read(&rdev->exclusive_lock);
  343. r = radeon_gem_handle_lockup(robj->rdev, r);
  344. return r;
  345. }
  346. int radeon_mode_dumb_mmap(struct drm_file *filp,
  347. struct drm_device *dev,
  348. uint32_t handle, uint64_t *offset_p)
  349. {
  350. struct drm_gem_object *gobj;
  351. struct radeon_bo *robj;
  352. gobj = drm_gem_object_lookup(dev, filp, handle);
  353. if (gobj == NULL) {
  354. return -ENOENT;
  355. }
  356. robj = gem_to_radeon_bo(gobj);
  357. if (radeon_ttm_tt_has_userptr(robj->tbo.ttm)) {
  358. drm_gem_object_unreference_unlocked(gobj);
  359. return -EPERM;
  360. }
  361. *offset_p = radeon_bo_mmap_offset(robj);
  362. drm_gem_object_unreference_unlocked(gobj);
  363. return 0;
  364. }
  365. int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
  366. struct drm_file *filp)
  367. {
  368. struct drm_radeon_gem_mmap *args = data;
  369. return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr);
  370. }
  371. int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
  372. struct drm_file *filp)
  373. {
  374. struct radeon_device *rdev = dev->dev_private;
  375. struct drm_radeon_gem_busy *args = data;
  376. struct drm_gem_object *gobj;
  377. struct radeon_bo *robj;
  378. int r;
  379. uint32_t cur_placement = 0;
  380. gobj = drm_gem_object_lookup(dev, filp, args->handle);
  381. if (gobj == NULL) {
  382. return -ENOENT;
  383. }
  384. robj = gem_to_radeon_bo(gobj);
  385. r = radeon_bo_wait(robj, &cur_placement, true);
  386. args->domain = radeon_mem_type_to_domain(cur_placement);
  387. drm_gem_object_unreference_unlocked(gobj);
  388. r = radeon_gem_handle_lockup(rdev, r);
  389. return r;
  390. }
  391. int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
  392. struct drm_file *filp)
  393. {
  394. struct radeon_device *rdev = dev->dev_private;
  395. struct drm_radeon_gem_wait_idle *args = data;
  396. struct drm_gem_object *gobj;
  397. struct radeon_bo *robj;
  398. int r = 0;
  399. uint32_t cur_placement = 0;
  400. long ret;
  401. gobj = drm_gem_object_lookup(dev, filp, args->handle);
  402. if (gobj == NULL) {
  403. return -ENOENT;
  404. }
  405. robj = gem_to_radeon_bo(gobj);
  406. ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, 30 * HZ);
  407. if (ret == 0)
  408. r = -EBUSY;
  409. else if (ret < 0)
  410. r = ret;
  411. /* Flush HDP cache via MMIO if necessary */
  412. if (rdev->asic->mmio_hdp_flush &&
  413. radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM)
  414. robj->rdev->asic->mmio_hdp_flush(rdev);
  415. drm_gem_object_unreference_unlocked(gobj);
  416. r = radeon_gem_handle_lockup(rdev, r);
  417. return r;
  418. }
  419. int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
  420. struct drm_file *filp)
  421. {
  422. struct drm_radeon_gem_set_tiling *args = data;
  423. struct drm_gem_object *gobj;
  424. struct radeon_bo *robj;
  425. int r = 0;
  426. DRM_DEBUG("%d \n", args->handle);
  427. gobj = drm_gem_object_lookup(dev, filp, args->handle);
  428. if (gobj == NULL)
  429. return -ENOENT;
  430. robj = gem_to_radeon_bo(gobj);
  431. r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch);
  432. drm_gem_object_unreference_unlocked(gobj);
  433. return r;
  434. }
  435. int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
  436. struct drm_file *filp)
  437. {
  438. struct drm_radeon_gem_get_tiling *args = data;
  439. struct drm_gem_object *gobj;
  440. struct radeon_bo *rbo;
  441. int r = 0;
  442. DRM_DEBUG("\n");
  443. gobj = drm_gem_object_lookup(dev, filp, args->handle);
  444. if (gobj == NULL)
  445. return -ENOENT;
  446. rbo = gem_to_radeon_bo(gobj);
  447. r = radeon_bo_reserve(rbo, false);
  448. if (unlikely(r != 0))
  449. goto out;
  450. radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch);
  451. radeon_bo_unreserve(rbo);
  452. out:
  453. drm_gem_object_unreference_unlocked(gobj);
  454. return r;
  455. }
  456. /**
  457. * radeon_gem_va_update_vm -update the bo_va in its VM
  458. *
  459. * @rdev: radeon_device pointer
  460. * @bo_va: bo_va to update
  461. *
  462. * Update the bo_va directly after setting it's address. Errors are not
  463. * vital here, so they are not reported back to userspace.
  464. */
  465. static void radeon_gem_va_update_vm(struct radeon_device *rdev,
  466. struct radeon_bo_va *bo_va)
  467. {
  468. struct ttm_validate_buffer tv, *entry;
  469. struct radeon_bo_list *vm_bos;
  470. struct ww_acquire_ctx ticket;
  471. struct list_head list;
  472. unsigned domain;
  473. int r;
  474. INIT_LIST_HEAD(&list);
  475. tv.bo = &bo_va->bo->tbo;
  476. tv.shared = true;
  477. list_add(&tv.head, &list);
  478. vm_bos = radeon_vm_get_bos(rdev, bo_va->vm, &list);
  479. if (!vm_bos)
  480. return;
  481. r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
  482. if (r)
  483. goto error_free;
  484. list_for_each_entry(entry, &list, head) {
  485. domain = radeon_mem_type_to_domain(entry->bo->mem.mem_type);
  486. /* if anything is swapped out don't swap it in here,
  487. just abort and wait for the next CS */
  488. if (domain == RADEON_GEM_DOMAIN_CPU)
  489. goto error_unreserve;
  490. }
  491. mutex_lock(&bo_va->vm->mutex);
  492. r = radeon_vm_clear_freed(rdev, bo_va->vm);
  493. if (r)
  494. goto error_unlock;
  495. if (bo_va->it.start)
  496. r = radeon_vm_bo_update(rdev, bo_va, &bo_va->bo->tbo.mem);
  497. error_unlock:
  498. mutex_unlock(&bo_va->vm->mutex);
  499. error_unreserve:
  500. ttm_eu_backoff_reservation(&ticket, &list);
  501. error_free:
  502. drm_free_large(vm_bos);
  503. if (r && r != -ERESTARTSYS)
  504. DRM_ERROR("Couldn't update BO_VA (%d)\n", r);
  505. }
  506. int radeon_gem_va_ioctl(struct drm_device *dev, void *data,
  507. struct drm_file *filp)
  508. {
  509. struct drm_radeon_gem_va *args = data;
  510. struct drm_gem_object *gobj;
  511. struct radeon_device *rdev = dev->dev_private;
  512. struct radeon_fpriv *fpriv = filp->driver_priv;
  513. struct radeon_bo *rbo;
  514. struct radeon_bo_va *bo_va;
  515. u32 invalid_flags;
  516. int r = 0;
  517. if (!rdev->vm_manager.enabled) {
  518. args->operation = RADEON_VA_RESULT_ERROR;
  519. return -ENOTTY;
  520. }
  521. /* !! DONT REMOVE !!
  522. * We don't support vm_id yet, to be sure we don't have have broken
  523. * userspace, reject anyone trying to use non 0 value thus moving
  524. * forward we can use those fields without breaking existant userspace
  525. */
  526. if (args->vm_id) {
  527. args->operation = RADEON_VA_RESULT_ERROR;
  528. return -EINVAL;
  529. }
  530. if (args->offset < RADEON_VA_RESERVED_SIZE) {
  531. dev_err(&dev->pdev->dev,
  532. "offset 0x%lX is in reserved area 0x%X\n",
  533. (unsigned long)args->offset,
  534. RADEON_VA_RESERVED_SIZE);
  535. args->operation = RADEON_VA_RESULT_ERROR;
  536. return -EINVAL;
  537. }
  538. /* don't remove, we need to enforce userspace to set the snooped flag
  539. * otherwise we will endup with broken userspace and we won't be able
  540. * to enable this feature without adding new interface
  541. */
  542. invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM;
  543. if ((args->flags & invalid_flags)) {
  544. dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n",
  545. args->flags, invalid_flags);
  546. args->operation = RADEON_VA_RESULT_ERROR;
  547. return -EINVAL;
  548. }
  549. switch (args->operation) {
  550. case RADEON_VA_MAP:
  551. case RADEON_VA_UNMAP:
  552. break;
  553. default:
  554. dev_err(&dev->pdev->dev, "unsupported operation %d\n",
  555. args->operation);
  556. args->operation = RADEON_VA_RESULT_ERROR;
  557. return -EINVAL;
  558. }
  559. gobj = drm_gem_object_lookup(dev, filp, args->handle);
  560. if (gobj == NULL) {
  561. args->operation = RADEON_VA_RESULT_ERROR;
  562. return -ENOENT;
  563. }
  564. rbo = gem_to_radeon_bo(gobj);
  565. r = radeon_bo_reserve(rbo, false);
  566. if (r) {
  567. args->operation = RADEON_VA_RESULT_ERROR;
  568. drm_gem_object_unreference_unlocked(gobj);
  569. return r;
  570. }
  571. bo_va = radeon_vm_bo_find(&fpriv->vm, rbo);
  572. if (!bo_va) {
  573. args->operation = RADEON_VA_RESULT_ERROR;
  574. drm_gem_object_unreference_unlocked(gobj);
  575. return -ENOENT;
  576. }
  577. switch (args->operation) {
  578. case RADEON_VA_MAP:
  579. if (bo_va->it.start) {
  580. args->operation = RADEON_VA_RESULT_VA_EXIST;
  581. args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE;
  582. radeon_bo_unreserve(rbo);
  583. goto out;
  584. }
  585. r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags);
  586. break;
  587. case RADEON_VA_UNMAP:
  588. r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0);
  589. break;
  590. default:
  591. break;
  592. }
  593. if (!r)
  594. radeon_gem_va_update_vm(rdev, bo_va);
  595. args->operation = RADEON_VA_RESULT_OK;
  596. if (r) {
  597. args->operation = RADEON_VA_RESULT_ERROR;
  598. }
  599. out:
  600. drm_gem_object_unreference_unlocked(gobj);
  601. return r;
  602. }
  603. int radeon_gem_op_ioctl(struct drm_device *dev, void *data,
  604. struct drm_file *filp)
  605. {
  606. struct drm_radeon_gem_op *args = data;
  607. struct drm_gem_object *gobj;
  608. struct radeon_bo *robj;
  609. int r;
  610. gobj = drm_gem_object_lookup(dev, filp, args->handle);
  611. if (gobj == NULL) {
  612. return -ENOENT;
  613. }
  614. robj = gem_to_radeon_bo(gobj);
  615. r = -EPERM;
  616. if (radeon_ttm_tt_has_userptr(robj->tbo.ttm))
  617. goto out;
  618. r = radeon_bo_reserve(robj, false);
  619. if (unlikely(r))
  620. goto out;
  621. switch (args->op) {
  622. case RADEON_GEM_OP_GET_INITIAL_DOMAIN:
  623. args->value = robj->initial_domain;
  624. break;
  625. case RADEON_GEM_OP_SET_INITIAL_DOMAIN:
  626. robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM |
  627. RADEON_GEM_DOMAIN_GTT |
  628. RADEON_GEM_DOMAIN_CPU);
  629. break;
  630. default:
  631. r = -EINVAL;
  632. }
  633. radeon_bo_unreserve(robj);
  634. out:
  635. drm_gem_object_unreference_unlocked(gobj);
  636. return r;
  637. }
  638. int radeon_mode_dumb_create(struct drm_file *file_priv,
  639. struct drm_device *dev,
  640. struct drm_mode_create_dumb *args)
  641. {
  642. struct radeon_device *rdev = dev->dev_private;
  643. struct drm_gem_object *gobj;
  644. uint32_t handle;
  645. int r;
  646. args->pitch = radeon_align_pitch(rdev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8);
  647. args->size = args->pitch * args->height;
  648. args->size = ALIGN(args->size, PAGE_SIZE);
  649. r = radeon_gem_object_create(rdev, args->size, 0,
  650. RADEON_GEM_DOMAIN_VRAM, 0,
  651. false, &gobj);
  652. if (r)
  653. return -ENOMEM;
  654. r = drm_gem_handle_create(file_priv, gobj, &handle);
  655. /* drop reference from allocate - handle holds it now */
  656. drm_gem_object_unreference_unlocked(gobj);
  657. if (r) {
  658. return r;
  659. }
  660. args->handle = handle;
  661. return 0;
  662. }
  663. #if defined(CONFIG_DEBUG_FS)
  664. static int radeon_debugfs_gem_info(struct seq_file *m, void *data)
  665. {
  666. struct drm_info_node *node = (struct drm_info_node *)m->private;
  667. struct drm_device *dev = node->minor->dev;
  668. struct radeon_device *rdev = dev->dev_private;
  669. struct radeon_bo *rbo;
  670. unsigned i = 0;
  671. mutex_lock(&rdev->gem.mutex);
  672. list_for_each_entry(rbo, &rdev->gem.objects, list) {
  673. unsigned domain;
  674. const char *placement;
  675. domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type);
  676. switch (domain) {
  677. case RADEON_GEM_DOMAIN_VRAM:
  678. placement = "VRAM";
  679. break;
  680. case RADEON_GEM_DOMAIN_GTT:
  681. placement = " GTT";
  682. break;
  683. case RADEON_GEM_DOMAIN_CPU:
  684. default:
  685. placement = " CPU";
  686. break;
  687. }
  688. seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n",
  689. i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20,
  690. placement, (unsigned long)rbo->pid);
  691. i++;
  692. }
  693. mutex_unlock(&rdev->gem.mutex);
  694. return 0;
  695. }
  696. static struct drm_info_list radeon_debugfs_gem_list[] = {
  697. {"radeon_gem_info", &radeon_debugfs_gem_info, 0, NULL},
  698. };
  699. #endif
  700. int radeon_gem_debugfs_init(struct radeon_device *rdev)
  701. {
  702. #if defined(CONFIG_DEBUG_FS)
  703. return radeon_debugfs_add_files(rdev, radeon_debugfs_gem_list, 1);
  704. #endif
  705. return 0;
  706. }