nouveau_drm.c 29 KB

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  1. /*
  2. * Copyright 2012 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include <linux/console.h>
  25. #include <linux/delay.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/pm_runtime.h>
  29. #include <linux/vga_switcheroo.h>
  30. #include "drmP.h"
  31. #include "drm_crtc_helper.h"
  32. #include <core/device.h>
  33. #include <core/gpuobj.h>
  34. #include <core/option.h>
  35. #include "nouveau_drm.h"
  36. #include "nouveau_dma.h"
  37. #include "nouveau_ttm.h"
  38. #include "nouveau_gem.h"
  39. #include "nouveau_agp.h"
  40. #include "nouveau_vga.h"
  41. #include "nouveau_sysfs.h"
  42. #include "nouveau_hwmon.h"
  43. #include "nouveau_acpi.h"
  44. #include "nouveau_bios.h"
  45. #include "nouveau_ioctl.h"
  46. #include "nouveau_abi16.h"
  47. #include "nouveau_fbcon.h"
  48. #include "nouveau_fence.h"
  49. #include "nouveau_debugfs.h"
  50. #include "nouveau_usif.h"
  51. #include "nouveau_connector.h"
  52. #include "nouveau_platform.h"
  53. MODULE_PARM_DESC(config, "option string to pass to driver core");
  54. static char *nouveau_config;
  55. module_param_named(config, nouveau_config, charp, 0400);
  56. MODULE_PARM_DESC(debug, "debug string to pass to driver core");
  57. static char *nouveau_debug;
  58. module_param_named(debug, nouveau_debug, charp, 0400);
  59. MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
  60. static int nouveau_noaccel = 0;
  61. module_param_named(noaccel, nouveau_noaccel, int, 0400);
  62. MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
  63. "0 = disabled, 1 = enabled, 2 = headless)");
  64. int nouveau_modeset = -1;
  65. module_param_named(modeset, nouveau_modeset, int, 0400);
  66. MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
  67. int nouveau_runtime_pm = -1;
  68. module_param_named(runpm, nouveau_runtime_pm, int, 0400);
  69. static struct drm_driver driver_stub;
  70. static struct drm_driver driver_pci;
  71. static struct drm_driver driver_platform;
  72. static u64
  73. nouveau_pci_name(struct pci_dev *pdev)
  74. {
  75. u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
  76. name |= pdev->bus->number << 16;
  77. name |= PCI_SLOT(pdev->devfn) << 8;
  78. return name | PCI_FUNC(pdev->devfn);
  79. }
  80. static u64
  81. nouveau_platform_name(struct platform_device *platformdev)
  82. {
  83. return platformdev->id;
  84. }
  85. static u64
  86. nouveau_name(struct drm_device *dev)
  87. {
  88. if (dev->pdev)
  89. return nouveau_pci_name(dev->pdev);
  90. else
  91. return nouveau_platform_name(dev->platformdev);
  92. }
  93. static int
  94. nouveau_cli_create(u64 name, const char *sname,
  95. int size, void **pcli)
  96. {
  97. struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL);
  98. if (cli) {
  99. int ret = nvif_client_init(NULL, NULL, sname, name,
  100. nouveau_config, nouveau_debug,
  101. &cli->base);
  102. if (ret == 0) {
  103. mutex_init(&cli->mutex);
  104. usif_client_init(cli);
  105. }
  106. return ret;
  107. }
  108. return -ENOMEM;
  109. }
  110. static void
  111. nouveau_cli_destroy(struct nouveau_cli *cli)
  112. {
  113. nvkm_vm_ref(NULL, &nvxx_client(&cli->base)->vm, NULL);
  114. nvif_client_fini(&cli->base);
  115. usif_client_fini(cli);
  116. }
  117. static void
  118. nouveau_accel_fini(struct nouveau_drm *drm)
  119. {
  120. nouveau_channel_del(&drm->channel);
  121. nvif_object_fini(&drm->ntfy);
  122. nvkm_gpuobj_ref(NULL, &drm->notify);
  123. nvif_object_fini(&drm->nvsw);
  124. nouveau_channel_del(&drm->cechan);
  125. nvif_object_fini(&drm->ttm.copy);
  126. if (drm->fence)
  127. nouveau_fence(drm)->dtor(drm);
  128. }
  129. static void
  130. nouveau_accel_init(struct nouveau_drm *drm)
  131. {
  132. struct nvif_device *device = &drm->device;
  133. u32 arg0, arg1;
  134. u32 sclass[16];
  135. int ret, i;
  136. if (nouveau_noaccel)
  137. return;
  138. /* initialise synchronisation routines */
  139. /*XXX: this is crap, but the fence/channel stuff is a little
  140. * backwards in some places. this will be fixed.
  141. */
  142. ret = nvif_object_sclass(&device->base, sclass, ARRAY_SIZE(sclass));
  143. if (ret < 0)
  144. return;
  145. for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) {
  146. switch (sclass[i]) {
  147. case NV03_CHANNEL_DMA:
  148. ret = nv04_fence_create(drm);
  149. break;
  150. case NV10_CHANNEL_DMA:
  151. ret = nv10_fence_create(drm);
  152. break;
  153. case NV17_CHANNEL_DMA:
  154. case NV40_CHANNEL_DMA:
  155. ret = nv17_fence_create(drm);
  156. break;
  157. case NV50_CHANNEL_GPFIFO:
  158. ret = nv50_fence_create(drm);
  159. break;
  160. case G82_CHANNEL_GPFIFO:
  161. ret = nv84_fence_create(drm);
  162. break;
  163. case FERMI_CHANNEL_GPFIFO:
  164. case KEPLER_CHANNEL_GPFIFO_A:
  165. case MAXWELL_CHANNEL_GPFIFO_A:
  166. ret = nvc0_fence_create(drm);
  167. break;
  168. default:
  169. break;
  170. }
  171. }
  172. if (ret) {
  173. NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
  174. nouveau_accel_fini(drm);
  175. return;
  176. }
  177. if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
  178. ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
  179. KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0|
  180. KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1,
  181. 0, &drm->cechan);
  182. if (ret)
  183. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  184. arg0 = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR;
  185. arg1 = 1;
  186. } else
  187. if (device->info.chipset >= 0xa3 &&
  188. device->info.chipset != 0xaa &&
  189. device->info.chipset != 0xac) {
  190. ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
  191. NvDmaFB, NvDmaTT, &drm->cechan);
  192. if (ret)
  193. NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
  194. arg0 = NvDmaFB;
  195. arg1 = NvDmaTT;
  196. } else {
  197. arg0 = NvDmaFB;
  198. arg1 = NvDmaTT;
  199. }
  200. ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN, arg0, arg1,
  201. &drm->channel);
  202. if (ret) {
  203. NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
  204. nouveau_accel_fini(drm);
  205. return;
  206. }
  207. ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
  208. nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
  209. if (ret == 0) {
  210. struct nvkm_sw_chan *swch;
  211. ret = RING_SPACE(drm->channel, 2);
  212. if (ret == 0) {
  213. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  214. BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
  215. OUT_RING (drm->channel, NVDRM_NVSW);
  216. } else
  217. if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
  218. BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
  219. OUT_RING (drm->channel, 0x001f0000);
  220. }
  221. }
  222. swch = (void *)nvxx_object(&drm->nvsw)->parent;
  223. swch->flip = nouveau_flip_complete;
  224. swch->flip_data = drm->channel;
  225. }
  226. if (ret) {
  227. NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
  228. nouveau_accel_fini(drm);
  229. return;
  230. }
  231. if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
  232. ret = nvkm_gpuobj_new(nvxx_object(&drm->device), NULL, 32,
  233. 0, 0, &drm->notify);
  234. if (ret) {
  235. NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
  236. nouveau_accel_fini(drm);
  237. return;
  238. }
  239. ret = nvif_object_init(drm->channel->object, NULL, NvNotify0,
  240. NV_DMA_IN_MEMORY,
  241. &(struct nv_dma_v0) {
  242. .target = NV_DMA_V0_TARGET_VRAM,
  243. .access = NV_DMA_V0_ACCESS_RDWR,
  244. .start = drm->notify->addr,
  245. .limit = drm->notify->addr + 31
  246. }, sizeof(struct nv_dma_v0),
  247. &drm->ntfy);
  248. if (ret) {
  249. nouveau_accel_fini(drm);
  250. return;
  251. }
  252. }
  253. nouveau_bo_move_init(drm);
  254. }
  255. static int nouveau_drm_probe(struct pci_dev *pdev,
  256. const struct pci_device_id *pent)
  257. {
  258. struct nvkm_device *device;
  259. struct apertures_struct *aper;
  260. bool boot = false;
  261. int ret;
  262. /* remove conflicting drivers (vesafb, efifb etc) */
  263. aper = alloc_apertures(3);
  264. if (!aper)
  265. return -ENOMEM;
  266. aper->ranges[0].base = pci_resource_start(pdev, 1);
  267. aper->ranges[0].size = pci_resource_len(pdev, 1);
  268. aper->count = 1;
  269. if (pci_resource_len(pdev, 2)) {
  270. aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
  271. aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
  272. aper->count++;
  273. }
  274. if (pci_resource_len(pdev, 3)) {
  275. aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
  276. aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
  277. aper->count++;
  278. }
  279. #ifdef CONFIG_X86
  280. boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  281. #endif
  282. if (nouveau_modeset != 2)
  283. remove_conflicting_framebuffers(aper, "nouveaufb", boot);
  284. kfree(aper);
  285. ret = nvkm_device_create(pdev, NVKM_BUS_PCI,
  286. nouveau_pci_name(pdev), pci_name(pdev),
  287. nouveau_config, nouveau_debug, &device);
  288. if (ret)
  289. return ret;
  290. pci_set_master(pdev);
  291. ret = drm_get_pci_dev(pdev, pent, &driver_pci);
  292. if (ret) {
  293. nvkm_object_ref(NULL, (struct nvkm_object **)&device);
  294. return ret;
  295. }
  296. return 0;
  297. }
  298. #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
  299. static void
  300. nouveau_get_hdmi_dev(struct nouveau_drm *drm)
  301. {
  302. struct pci_dev *pdev = drm->dev->pdev;
  303. if (!pdev) {
  304. DRM_INFO("not a PCI device; no HDMI\n");
  305. drm->hdmi_device = NULL;
  306. return;
  307. }
  308. /* subfunction one is a hdmi audio device? */
  309. drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
  310. PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
  311. if (!drm->hdmi_device) {
  312. NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
  313. return;
  314. }
  315. if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
  316. NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
  317. pci_dev_put(drm->hdmi_device);
  318. drm->hdmi_device = NULL;
  319. return;
  320. }
  321. }
  322. static int
  323. nouveau_drm_load(struct drm_device *dev, unsigned long flags)
  324. {
  325. struct pci_dev *pdev = dev->pdev;
  326. struct nouveau_drm *drm;
  327. int ret;
  328. ret = nouveau_cli_create(nouveau_name(dev), "DRM", sizeof(*drm),
  329. (void **)&drm);
  330. if (ret)
  331. return ret;
  332. dev->dev_private = drm;
  333. drm->dev = dev;
  334. nvxx_client(&drm->client.base)->debug =
  335. nvkm_dbgopt(nouveau_debug, "DRM");
  336. INIT_LIST_HEAD(&drm->clients);
  337. spin_lock_init(&drm->tile.lock);
  338. nouveau_get_hdmi_dev(drm);
  339. /* make sure AGP controller is in a consistent state before we
  340. * (possibly) execute vbios init tables (see nouveau_agp.h)
  341. */
  342. if (pdev && drm_pci_device_is_agp(dev) && dev->agp) {
  343. const u64 enables = NV_DEVICE_V0_DISABLE_IDENTIFY |
  344. NV_DEVICE_V0_DISABLE_MMIO;
  345. /* dummy device object, doesn't init anything, but allows
  346. * agp code access to registers
  347. */
  348. ret = nvif_device_init(&drm->client.base.base, NULL,
  349. NVDRM_DEVICE, NV_DEVICE,
  350. &(struct nv_device_v0) {
  351. .device = ~0,
  352. .disable = ~enables,
  353. .debug0 = ~0,
  354. }, sizeof(struct nv_device_v0),
  355. &drm->device);
  356. if (ret)
  357. goto fail_device;
  358. nouveau_agp_reset(drm);
  359. nvif_device_fini(&drm->device);
  360. }
  361. ret = nvif_device_init(&drm->client.base.base, NULL, NVDRM_DEVICE,
  362. NV_DEVICE,
  363. &(struct nv_device_v0) {
  364. .device = ~0,
  365. .disable = 0,
  366. .debug0 = 0,
  367. }, sizeof(struct nv_device_v0),
  368. &drm->device);
  369. if (ret)
  370. goto fail_device;
  371. dev->irq_enabled = true;
  372. /* workaround an odd issue on nvc1 by disabling the device's
  373. * nosnoop capability. hopefully won't cause issues until a
  374. * better fix is found - assuming there is one...
  375. */
  376. if (drm->device.info.chipset == 0xc1)
  377. nvif_mask(&drm->device, 0x00088080, 0x00000800, 0x00000000);
  378. nouveau_vga_init(drm);
  379. nouveau_agp_init(drm);
  380. if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
  381. ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
  382. 0x1000, &drm->client.vm);
  383. if (ret)
  384. goto fail_device;
  385. nvxx_client(&drm->client.base)->vm = drm->client.vm;
  386. }
  387. ret = nouveau_ttm_init(drm);
  388. if (ret)
  389. goto fail_ttm;
  390. ret = nouveau_bios_init(dev);
  391. if (ret)
  392. goto fail_bios;
  393. ret = nouveau_display_create(dev);
  394. if (ret)
  395. goto fail_dispctor;
  396. if (dev->mode_config.num_crtc) {
  397. ret = nouveau_display_init(dev);
  398. if (ret)
  399. goto fail_dispinit;
  400. }
  401. nouveau_sysfs_init(dev);
  402. nouveau_hwmon_init(dev);
  403. nouveau_accel_init(drm);
  404. nouveau_fbcon_init(dev);
  405. if (nouveau_runtime_pm != 0) {
  406. pm_runtime_use_autosuspend(dev->dev);
  407. pm_runtime_set_autosuspend_delay(dev->dev, 5000);
  408. pm_runtime_set_active(dev->dev);
  409. pm_runtime_allow(dev->dev);
  410. pm_runtime_mark_last_busy(dev->dev);
  411. pm_runtime_put(dev->dev);
  412. }
  413. return 0;
  414. fail_dispinit:
  415. nouveau_display_destroy(dev);
  416. fail_dispctor:
  417. nouveau_bios_takedown(dev);
  418. fail_bios:
  419. nouveau_ttm_fini(drm);
  420. fail_ttm:
  421. nouveau_agp_fini(drm);
  422. nouveau_vga_fini(drm);
  423. fail_device:
  424. nvif_device_fini(&drm->device);
  425. nouveau_cli_destroy(&drm->client);
  426. return ret;
  427. }
  428. static int
  429. nouveau_drm_unload(struct drm_device *dev)
  430. {
  431. struct nouveau_drm *drm = nouveau_drm(dev);
  432. pm_runtime_get_sync(dev->dev);
  433. nouveau_fbcon_fini(dev);
  434. nouveau_accel_fini(drm);
  435. nouveau_hwmon_fini(dev);
  436. nouveau_sysfs_fini(dev);
  437. if (dev->mode_config.num_crtc)
  438. nouveau_display_fini(dev);
  439. nouveau_display_destroy(dev);
  440. nouveau_bios_takedown(dev);
  441. nouveau_ttm_fini(drm);
  442. nouveau_agp_fini(drm);
  443. nouveau_vga_fini(drm);
  444. nvif_device_fini(&drm->device);
  445. if (drm->hdmi_device)
  446. pci_dev_put(drm->hdmi_device);
  447. nouveau_cli_destroy(&drm->client);
  448. return 0;
  449. }
  450. void
  451. nouveau_drm_device_remove(struct drm_device *dev)
  452. {
  453. struct nouveau_drm *drm = nouveau_drm(dev);
  454. struct nvkm_client *client;
  455. struct nvkm_object *device;
  456. dev->irq_enabled = false;
  457. client = nvxx_client(&drm->client.base);
  458. device = client->device;
  459. drm_put_dev(dev);
  460. nvkm_object_ref(NULL, &device);
  461. nvkm_object_debug();
  462. }
  463. static void
  464. nouveau_drm_remove(struct pci_dev *pdev)
  465. {
  466. struct drm_device *dev = pci_get_drvdata(pdev);
  467. nouveau_drm_device_remove(dev);
  468. }
  469. static int
  470. nouveau_do_suspend(struct drm_device *dev, bool runtime)
  471. {
  472. struct nouveau_drm *drm = nouveau_drm(dev);
  473. struct nouveau_cli *cli;
  474. int ret;
  475. if (dev->mode_config.num_crtc) {
  476. NV_INFO(drm, "suspending console...\n");
  477. nouveau_fbcon_set_suspend(dev, 1);
  478. NV_INFO(drm, "suspending display...\n");
  479. ret = nouveau_display_suspend(dev, runtime);
  480. if (ret)
  481. return ret;
  482. }
  483. NV_INFO(drm, "evicting buffers...\n");
  484. ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
  485. NV_INFO(drm, "waiting for kernel channels to go idle...\n");
  486. if (drm->cechan) {
  487. ret = nouveau_channel_idle(drm->cechan);
  488. if (ret)
  489. goto fail_display;
  490. }
  491. if (drm->channel) {
  492. ret = nouveau_channel_idle(drm->channel);
  493. if (ret)
  494. goto fail_display;
  495. }
  496. NV_INFO(drm, "suspending client object trees...\n");
  497. if (drm->fence && nouveau_fence(drm)->suspend) {
  498. if (!nouveau_fence(drm)->suspend(drm)) {
  499. ret = -ENOMEM;
  500. goto fail_display;
  501. }
  502. }
  503. list_for_each_entry(cli, &drm->clients, head) {
  504. ret = nvif_client_suspend(&cli->base);
  505. if (ret)
  506. goto fail_client;
  507. }
  508. NV_INFO(drm, "suspending kernel object tree...\n");
  509. ret = nvif_client_suspend(&drm->client.base);
  510. if (ret)
  511. goto fail_client;
  512. nouveau_agp_fini(drm);
  513. return 0;
  514. fail_client:
  515. list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
  516. nvif_client_resume(&cli->base);
  517. }
  518. if (drm->fence && nouveau_fence(drm)->resume)
  519. nouveau_fence(drm)->resume(drm);
  520. fail_display:
  521. if (dev->mode_config.num_crtc) {
  522. NV_INFO(drm, "resuming display...\n");
  523. nouveau_display_resume(dev, runtime);
  524. }
  525. return ret;
  526. }
  527. static int
  528. nouveau_do_resume(struct drm_device *dev, bool runtime)
  529. {
  530. struct nouveau_drm *drm = nouveau_drm(dev);
  531. struct nouveau_cli *cli;
  532. NV_INFO(drm, "re-enabling device...\n");
  533. nouveau_agp_reset(drm);
  534. NV_INFO(drm, "resuming kernel object tree...\n");
  535. nvif_client_resume(&drm->client.base);
  536. nouveau_agp_init(drm);
  537. NV_INFO(drm, "resuming client object trees...\n");
  538. if (drm->fence && nouveau_fence(drm)->resume)
  539. nouveau_fence(drm)->resume(drm);
  540. list_for_each_entry(cli, &drm->clients, head) {
  541. nvif_client_resume(&cli->base);
  542. }
  543. nouveau_run_vbios_init(dev);
  544. if (dev->mode_config.num_crtc) {
  545. NV_INFO(drm, "resuming display...\n");
  546. nouveau_display_resume(dev, runtime);
  547. NV_INFO(drm, "resuming console...\n");
  548. nouveau_fbcon_set_suspend(dev, 0);
  549. }
  550. return 0;
  551. }
  552. int
  553. nouveau_pmops_suspend(struct device *dev)
  554. {
  555. struct pci_dev *pdev = to_pci_dev(dev);
  556. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  557. int ret;
  558. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  559. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  560. return 0;
  561. ret = nouveau_do_suspend(drm_dev, false);
  562. if (ret)
  563. return ret;
  564. pci_save_state(pdev);
  565. pci_disable_device(pdev);
  566. pci_set_power_state(pdev, PCI_D3hot);
  567. udelay(200);
  568. return 0;
  569. }
  570. int
  571. nouveau_pmops_resume(struct device *dev)
  572. {
  573. struct pci_dev *pdev = to_pci_dev(dev);
  574. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  575. int ret;
  576. if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
  577. drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
  578. return 0;
  579. pci_set_power_state(pdev, PCI_D0);
  580. pci_restore_state(pdev);
  581. ret = pci_enable_device(pdev);
  582. if (ret)
  583. return ret;
  584. pci_set_master(pdev);
  585. return nouveau_do_resume(drm_dev, false);
  586. }
  587. static int
  588. nouveau_pmops_freeze(struct device *dev)
  589. {
  590. struct pci_dev *pdev = to_pci_dev(dev);
  591. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  592. return nouveau_do_suspend(drm_dev, false);
  593. }
  594. static int
  595. nouveau_pmops_thaw(struct device *dev)
  596. {
  597. struct pci_dev *pdev = to_pci_dev(dev);
  598. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  599. return nouveau_do_resume(drm_dev, false);
  600. }
  601. static int
  602. nouveau_pmops_runtime_suspend(struct device *dev)
  603. {
  604. struct pci_dev *pdev = to_pci_dev(dev);
  605. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  606. int ret;
  607. if (nouveau_runtime_pm == 0) {
  608. pm_runtime_forbid(dev);
  609. return -EBUSY;
  610. }
  611. /* are we optimus enabled? */
  612. if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
  613. DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
  614. pm_runtime_forbid(dev);
  615. return -EBUSY;
  616. }
  617. nv_debug_level(SILENT);
  618. drm_kms_helper_poll_disable(drm_dev);
  619. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
  620. nouveau_switcheroo_optimus_dsm();
  621. ret = nouveau_do_suspend(drm_dev, true);
  622. pci_save_state(pdev);
  623. pci_disable_device(pdev);
  624. pci_ignore_hotplug(pdev);
  625. pci_set_power_state(pdev, PCI_D3cold);
  626. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  627. return ret;
  628. }
  629. static int
  630. nouveau_pmops_runtime_resume(struct device *dev)
  631. {
  632. struct pci_dev *pdev = to_pci_dev(dev);
  633. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  634. struct nvif_device *device = &nouveau_drm(drm_dev)->device;
  635. int ret;
  636. if (nouveau_runtime_pm == 0)
  637. return -EINVAL;
  638. pci_set_power_state(pdev, PCI_D0);
  639. pci_restore_state(pdev);
  640. ret = pci_enable_device(pdev);
  641. if (ret)
  642. return ret;
  643. pci_set_master(pdev);
  644. ret = nouveau_do_resume(drm_dev, true);
  645. drm_kms_helper_poll_enable(drm_dev);
  646. /* do magic */
  647. nvif_mask(device, 0x88488, (1 << 25), (1 << 25));
  648. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
  649. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  650. nv_debug_level(NORMAL);
  651. return ret;
  652. }
  653. static int
  654. nouveau_pmops_runtime_idle(struct device *dev)
  655. {
  656. struct pci_dev *pdev = to_pci_dev(dev);
  657. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  658. struct nouveau_drm *drm = nouveau_drm(drm_dev);
  659. struct drm_crtc *crtc;
  660. if (nouveau_runtime_pm == 0) {
  661. pm_runtime_forbid(dev);
  662. return -EBUSY;
  663. }
  664. /* are we optimus enabled? */
  665. if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
  666. DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
  667. pm_runtime_forbid(dev);
  668. return -EBUSY;
  669. }
  670. /* if we have a hdmi audio device - make sure it has a driver loaded */
  671. if (drm->hdmi_device) {
  672. if (!drm->hdmi_device->driver) {
  673. DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
  674. pm_runtime_mark_last_busy(dev);
  675. return -EBUSY;
  676. }
  677. }
  678. list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
  679. if (crtc->enabled) {
  680. DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
  681. return -EBUSY;
  682. }
  683. }
  684. pm_runtime_mark_last_busy(dev);
  685. pm_runtime_autosuspend(dev);
  686. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  687. return 1;
  688. }
  689. static int
  690. nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
  691. {
  692. struct nouveau_drm *drm = nouveau_drm(dev);
  693. struct nouveau_cli *cli;
  694. char name[32], tmpname[TASK_COMM_LEN];
  695. int ret;
  696. /* need to bring up power immediately if opening device */
  697. ret = pm_runtime_get_sync(dev->dev);
  698. if (ret < 0 && ret != -EACCES)
  699. return ret;
  700. get_task_comm(tmpname, current);
  701. snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
  702. ret = nouveau_cli_create(nouveau_name(dev), name, sizeof(*cli),
  703. (void **)&cli);
  704. if (ret)
  705. goto out_suspend;
  706. cli->base.super = false;
  707. if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
  708. ret = nvkm_vm_new(nvxx_device(&drm->device), 0, (1ULL << 40),
  709. 0x1000, &cli->vm);
  710. if (ret) {
  711. nouveau_cli_destroy(cli);
  712. goto out_suspend;
  713. }
  714. nvxx_client(&cli->base)->vm = cli->vm;
  715. }
  716. fpriv->driver_priv = cli;
  717. mutex_lock(&drm->client.mutex);
  718. list_add(&cli->head, &drm->clients);
  719. mutex_unlock(&drm->client.mutex);
  720. out_suspend:
  721. pm_runtime_mark_last_busy(dev->dev);
  722. pm_runtime_put_autosuspend(dev->dev);
  723. return ret;
  724. }
  725. static void
  726. nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
  727. {
  728. struct nouveau_cli *cli = nouveau_cli(fpriv);
  729. struct nouveau_drm *drm = nouveau_drm(dev);
  730. pm_runtime_get_sync(dev->dev);
  731. if (cli->abi16)
  732. nouveau_abi16_fini(cli->abi16);
  733. mutex_lock(&drm->client.mutex);
  734. list_del(&cli->head);
  735. mutex_unlock(&drm->client.mutex);
  736. }
  737. static void
  738. nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
  739. {
  740. struct nouveau_cli *cli = nouveau_cli(fpriv);
  741. nouveau_cli_destroy(cli);
  742. pm_runtime_mark_last_busy(dev->dev);
  743. pm_runtime_put_autosuspend(dev->dev);
  744. }
  745. static const struct drm_ioctl_desc
  746. nouveau_ioctls[] = {
  747. DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  748. DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  749. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  750. DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  751. DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  752. DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  753. DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  754. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  755. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  756. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  757. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  758. DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  759. };
  760. long
  761. nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
  762. {
  763. struct drm_file *filp = file->private_data;
  764. struct drm_device *dev = filp->minor->dev;
  765. long ret;
  766. ret = pm_runtime_get_sync(dev->dev);
  767. if (ret < 0 && ret != -EACCES)
  768. return ret;
  769. switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) {
  770. case DRM_NOUVEAU_NVIF:
  771. ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd));
  772. break;
  773. default:
  774. ret = drm_ioctl(file, cmd, arg);
  775. break;
  776. }
  777. pm_runtime_mark_last_busy(dev->dev);
  778. pm_runtime_put_autosuspend(dev->dev);
  779. return ret;
  780. }
  781. static const struct file_operations
  782. nouveau_driver_fops = {
  783. .owner = THIS_MODULE,
  784. .open = drm_open,
  785. .release = drm_release,
  786. .unlocked_ioctl = nouveau_drm_ioctl,
  787. .mmap = nouveau_ttm_mmap,
  788. .poll = drm_poll,
  789. .read = drm_read,
  790. #if defined(CONFIG_COMPAT)
  791. .compat_ioctl = nouveau_compat_ioctl,
  792. #endif
  793. .llseek = noop_llseek,
  794. };
  795. static struct drm_driver
  796. driver_stub = {
  797. .driver_features =
  798. DRIVER_USE_AGP |
  799. DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
  800. .load = nouveau_drm_load,
  801. .unload = nouveau_drm_unload,
  802. .open = nouveau_drm_open,
  803. .preclose = nouveau_drm_preclose,
  804. .postclose = nouveau_drm_postclose,
  805. .lastclose = nouveau_vga_lastclose,
  806. #if defined(CONFIG_DEBUG_FS)
  807. .debugfs_init = nouveau_debugfs_init,
  808. .debugfs_cleanup = nouveau_debugfs_takedown,
  809. #endif
  810. .get_vblank_counter = drm_vblank_count,
  811. .enable_vblank = nouveau_display_vblank_enable,
  812. .disable_vblank = nouveau_display_vblank_disable,
  813. .get_scanout_position = nouveau_display_scanoutpos,
  814. .get_vblank_timestamp = nouveau_display_vblstamp,
  815. .ioctls = nouveau_ioctls,
  816. .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
  817. .fops = &nouveau_driver_fops,
  818. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  819. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  820. .gem_prime_export = drm_gem_prime_export,
  821. .gem_prime_import = drm_gem_prime_import,
  822. .gem_prime_pin = nouveau_gem_prime_pin,
  823. .gem_prime_res_obj = nouveau_gem_prime_res_obj,
  824. .gem_prime_unpin = nouveau_gem_prime_unpin,
  825. .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
  826. .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
  827. .gem_prime_vmap = nouveau_gem_prime_vmap,
  828. .gem_prime_vunmap = nouveau_gem_prime_vunmap,
  829. .gem_free_object = nouveau_gem_object_del,
  830. .gem_open_object = nouveau_gem_object_open,
  831. .gem_close_object = nouveau_gem_object_close,
  832. .dumb_create = nouveau_display_dumb_create,
  833. .dumb_map_offset = nouveau_display_dumb_map_offset,
  834. .dumb_destroy = drm_gem_dumb_destroy,
  835. .name = DRIVER_NAME,
  836. .desc = DRIVER_DESC,
  837. #ifdef GIT_REVISION
  838. .date = GIT_REVISION,
  839. #else
  840. .date = DRIVER_DATE,
  841. #endif
  842. .major = DRIVER_MAJOR,
  843. .minor = DRIVER_MINOR,
  844. .patchlevel = DRIVER_PATCHLEVEL,
  845. };
  846. static struct pci_device_id
  847. nouveau_drm_pci_table[] = {
  848. {
  849. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
  850. .class = PCI_BASE_CLASS_DISPLAY << 16,
  851. .class_mask = 0xff << 16,
  852. },
  853. {
  854. PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
  855. .class = PCI_BASE_CLASS_DISPLAY << 16,
  856. .class_mask = 0xff << 16,
  857. },
  858. {}
  859. };
  860. static void nouveau_display_options(void)
  861. {
  862. DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n");
  863. DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable);
  864. DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid);
  865. DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink);
  866. DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel);
  867. DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config);
  868. DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug);
  869. DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel);
  870. DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset);
  871. DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm);
  872. DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf);
  873. DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate);
  874. }
  875. static const struct dev_pm_ops nouveau_pm_ops = {
  876. .suspend = nouveau_pmops_suspend,
  877. .resume = nouveau_pmops_resume,
  878. .freeze = nouveau_pmops_freeze,
  879. .thaw = nouveau_pmops_thaw,
  880. .poweroff = nouveau_pmops_freeze,
  881. .restore = nouveau_pmops_resume,
  882. .runtime_suspend = nouveau_pmops_runtime_suspend,
  883. .runtime_resume = nouveau_pmops_runtime_resume,
  884. .runtime_idle = nouveau_pmops_runtime_idle,
  885. };
  886. static struct pci_driver
  887. nouveau_drm_pci_driver = {
  888. .name = "nouveau",
  889. .id_table = nouveau_drm_pci_table,
  890. .probe = nouveau_drm_probe,
  891. .remove = nouveau_drm_remove,
  892. .driver.pm = &nouveau_pm_ops,
  893. };
  894. struct drm_device *
  895. nouveau_platform_device_create_(struct platform_device *pdev, int size,
  896. void **pobject)
  897. {
  898. struct drm_device *drm;
  899. int err;
  900. err = nvkm_device_create_(pdev, NVKM_BUS_PLATFORM,
  901. nouveau_platform_name(pdev),
  902. dev_name(&pdev->dev), nouveau_config,
  903. nouveau_debug, size, pobject);
  904. if (err)
  905. return ERR_PTR(err);
  906. drm = drm_dev_alloc(&driver_platform, &pdev->dev);
  907. if (!drm) {
  908. err = -ENOMEM;
  909. goto err_free;
  910. }
  911. err = drm_dev_set_unique(drm, "%s", dev_name(&pdev->dev));
  912. if (err < 0)
  913. goto err_free;
  914. drm->platformdev = pdev;
  915. platform_set_drvdata(pdev, drm);
  916. return drm;
  917. err_free:
  918. nvkm_object_ref(NULL, (struct nvkm_object **)pobject);
  919. return ERR_PTR(err);
  920. }
  921. static int __init
  922. nouveau_drm_init(void)
  923. {
  924. driver_pci = driver_stub;
  925. driver_pci.set_busid = drm_pci_set_busid;
  926. driver_platform = driver_stub;
  927. driver_platform.set_busid = drm_platform_set_busid;
  928. nouveau_display_options();
  929. if (nouveau_modeset == -1) {
  930. #ifdef CONFIG_VGA_CONSOLE
  931. if (vgacon_text_force())
  932. nouveau_modeset = 0;
  933. #endif
  934. }
  935. if (!nouveau_modeset)
  936. return 0;
  937. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  938. platform_driver_register(&nouveau_platform_driver);
  939. #endif
  940. nouveau_register_dsm_handler();
  941. return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver);
  942. }
  943. static void __exit
  944. nouveau_drm_exit(void)
  945. {
  946. if (!nouveau_modeset)
  947. return;
  948. drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver);
  949. nouveau_unregister_dsm_handler();
  950. #ifdef CONFIG_NOUVEAU_PLATFORM_DRIVER
  951. platform_driver_unregister(&nouveau_platform_driver);
  952. #endif
  953. }
  954. module_init(nouveau_drm_init);
  955. module_exit(nouveau_drm_exit);
  956. MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
  957. MODULE_AUTHOR(DRIVER_AUTHOR);
  958. MODULE_DESCRIPTION(DRIVER_DESC);
  959. MODULE_LICENSE("GPL and additional rights");