armada_overlay.c 14 KB

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  1. /*
  2. * Copyright (C) 2012 Russell King
  3. * Rewritten from the dovefb driver, and Armada510 manuals.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. */
  9. #include <drm/drmP.h>
  10. #include "armada_crtc.h"
  11. #include "armada_drm.h"
  12. #include "armada_fb.h"
  13. #include "armada_gem.h"
  14. #include "armada_hw.h"
  15. #include <drm/armada_drm.h>
  16. #include "armada_ioctlP.h"
  17. struct armada_plane_properties {
  18. uint32_t colorkey_yr;
  19. uint32_t colorkey_ug;
  20. uint32_t colorkey_vb;
  21. #define K2R(val) (((val) >> 0) & 0xff)
  22. #define K2G(val) (((val) >> 8) & 0xff)
  23. #define K2B(val) (((val) >> 16) & 0xff)
  24. int16_t brightness;
  25. uint16_t contrast;
  26. uint16_t saturation;
  27. uint32_t colorkey_mode;
  28. };
  29. struct armada_plane {
  30. struct drm_plane base;
  31. spinlock_t lock;
  32. struct drm_framebuffer *old_fb;
  33. uint32_t src_hw;
  34. uint32_t dst_hw;
  35. uint32_t dst_yx;
  36. uint32_t ctrl0;
  37. struct {
  38. struct armada_vbl_event update;
  39. struct armada_regs regs[13];
  40. wait_queue_head_t wait;
  41. } vbl;
  42. struct armada_plane_properties prop;
  43. };
  44. #define drm_to_armada_plane(p) container_of(p, struct armada_plane, base)
  45. static void
  46. armada_ovl_update_attr(struct armada_plane_properties *prop,
  47. struct armada_crtc *dcrtc)
  48. {
  49. writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y);
  50. writel_relaxed(prop->colorkey_ug, dcrtc->base + LCD_SPU_COLORKEY_U);
  51. writel_relaxed(prop->colorkey_vb, dcrtc->base + LCD_SPU_COLORKEY_V);
  52. writel_relaxed(prop->brightness << 16 | prop->contrast,
  53. dcrtc->base + LCD_SPU_CONTRAST);
  54. /* Docs say 15:0, but it seems to actually be 31:16 on Armada 510 */
  55. writel_relaxed(prop->saturation << 16,
  56. dcrtc->base + LCD_SPU_SATURATION);
  57. writel_relaxed(0x00002000, dcrtc->base + LCD_SPU_CBSH_HUE);
  58. spin_lock_irq(&dcrtc->irq_lock);
  59. armada_updatel(prop->colorkey_mode | CFG_ALPHAM_GRA,
  60. CFG_CKMODE_MASK | CFG_ALPHAM_MASK | CFG_ALPHA_MASK,
  61. dcrtc->base + LCD_SPU_DMA_CTRL1);
  62. armada_updatel(ADV_GRACOLORKEY, 0, dcrtc->base + LCD_SPU_ADV_REG);
  63. spin_unlock_irq(&dcrtc->irq_lock);
  64. }
  65. /* === Plane support === */
  66. static void armada_plane_vbl(struct armada_crtc *dcrtc, void *data)
  67. {
  68. struct armada_plane *dplane = data;
  69. struct drm_framebuffer *fb;
  70. armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
  71. spin_lock(&dplane->lock);
  72. fb = dplane->old_fb;
  73. dplane->old_fb = NULL;
  74. spin_unlock(&dplane->lock);
  75. if (fb)
  76. armada_drm_queue_unref_work(dcrtc->crtc.dev, fb);
  77. }
  78. static unsigned armada_limit(int start, unsigned size, unsigned max)
  79. {
  80. int end = start + size;
  81. if (end < 0)
  82. return 0;
  83. if (start < 0)
  84. start = 0;
  85. return (unsigned)end > max ? max - start : end - start;
  86. }
  87. static int
  88. armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
  89. struct drm_framebuffer *fb,
  90. int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h,
  91. uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h)
  92. {
  93. struct armada_plane *dplane = drm_to_armada_plane(plane);
  94. struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc);
  95. uint32_t val, ctrl0;
  96. unsigned idx = 0;
  97. int ret;
  98. crtc_w = armada_limit(crtc_x, crtc_w, dcrtc->crtc.mode.hdisplay);
  99. crtc_h = armada_limit(crtc_y, crtc_h, dcrtc->crtc.mode.vdisplay);
  100. ctrl0 = CFG_DMA_FMT(drm_fb_to_armada_fb(fb)->fmt) |
  101. CFG_DMA_MOD(drm_fb_to_armada_fb(fb)->mod) |
  102. CFG_CBSH_ENA | CFG_DMA_HSMOOTH | CFG_DMA_ENA;
  103. /* Does the position/size result in nothing to display? */
  104. if (crtc_w == 0 || crtc_h == 0) {
  105. ctrl0 &= ~CFG_DMA_ENA;
  106. }
  107. /*
  108. * FIXME: if the starting point is off screen, we need to
  109. * adjust src_x, src_y, src_w, src_h appropriately, and
  110. * according to the scale.
  111. */
  112. if (!dcrtc->plane) {
  113. dcrtc->plane = plane;
  114. armada_ovl_update_attr(&dplane->prop, dcrtc);
  115. }
  116. /* FIXME: overlay on an interlaced display */
  117. /* Just updating the position/size? */
  118. if (plane->fb == fb && dplane->ctrl0 == ctrl0) {
  119. val = (src_h & 0xffff0000) | src_w >> 16;
  120. dplane->src_hw = val;
  121. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_HPXL_VLN);
  122. val = crtc_h << 16 | crtc_w;
  123. dplane->dst_hw = val;
  124. writel_relaxed(val, dcrtc->base + LCD_SPU_DZM_HPXL_VLN);
  125. val = crtc_y << 16 | crtc_x;
  126. dplane->dst_yx = val;
  127. writel_relaxed(val, dcrtc->base + LCD_SPU_DMA_OVSA_HPXL_VLN);
  128. return 0;
  129. } else if (~dplane->ctrl0 & ctrl0 & CFG_DMA_ENA) {
  130. /* Power up the Y/U/V FIFOs on ENA 0->1 transitions */
  131. armada_updatel(0, CFG_PDWN16x66 | CFG_PDWN32x66,
  132. dcrtc->base + LCD_SPU_SRAM_PARA1);
  133. }
  134. ret = wait_event_timeout(dplane->vbl.wait,
  135. list_empty(&dplane->vbl.update.node),
  136. HZ/25);
  137. if (ret < 0)
  138. return ret;
  139. if (plane->fb != fb) {
  140. struct armada_gem_object *obj = drm_fb_obj(fb);
  141. uint32_t sy, su, sv;
  142. /*
  143. * Take a reference on the new framebuffer - we want to
  144. * hold on to it while the hardware is displaying it.
  145. */
  146. drm_framebuffer_reference(fb);
  147. if (plane->fb) {
  148. struct drm_framebuffer *older_fb;
  149. spin_lock_irq(&dplane->lock);
  150. older_fb = dplane->old_fb;
  151. dplane->old_fb = plane->fb;
  152. spin_unlock_irq(&dplane->lock);
  153. if (older_fb)
  154. armada_drm_queue_unref_work(dcrtc->crtc.dev,
  155. older_fb);
  156. }
  157. src_y >>= 16;
  158. src_x >>= 16;
  159. sy = obj->dev_addr + fb->offsets[0] + src_y * fb->pitches[0] +
  160. src_x * fb->bits_per_pixel / 8;
  161. su = obj->dev_addr + fb->offsets[1] + src_y * fb->pitches[1] +
  162. src_x;
  163. sv = obj->dev_addr + fb->offsets[2] + src_y * fb->pitches[2] +
  164. src_x;
  165. armada_reg_queue_set(dplane->vbl.regs, idx, sy,
  166. LCD_SPU_DMA_START_ADDR_Y0);
  167. armada_reg_queue_set(dplane->vbl.regs, idx, su,
  168. LCD_SPU_DMA_START_ADDR_U0);
  169. armada_reg_queue_set(dplane->vbl.regs, idx, sv,
  170. LCD_SPU_DMA_START_ADDR_V0);
  171. armada_reg_queue_set(dplane->vbl.regs, idx, sy,
  172. LCD_SPU_DMA_START_ADDR_Y1);
  173. armada_reg_queue_set(dplane->vbl.regs, idx, su,
  174. LCD_SPU_DMA_START_ADDR_U1);
  175. armada_reg_queue_set(dplane->vbl.regs, idx, sv,
  176. LCD_SPU_DMA_START_ADDR_V1);
  177. val = fb->pitches[0] << 16 | fb->pitches[0];
  178. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  179. LCD_SPU_DMA_PITCH_YC);
  180. val = fb->pitches[1] << 16 | fb->pitches[2];
  181. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  182. LCD_SPU_DMA_PITCH_UV);
  183. }
  184. val = (src_h & 0xffff0000) | src_w >> 16;
  185. if (dplane->src_hw != val) {
  186. dplane->src_hw = val;
  187. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  188. LCD_SPU_DMA_HPXL_VLN);
  189. }
  190. val = crtc_h << 16 | crtc_w;
  191. if (dplane->dst_hw != val) {
  192. dplane->dst_hw = val;
  193. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  194. LCD_SPU_DZM_HPXL_VLN);
  195. }
  196. val = crtc_y << 16 | crtc_x;
  197. if (dplane->dst_yx != val) {
  198. dplane->dst_yx = val;
  199. armada_reg_queue_set(dplane->vbl.regs, idx, val,
  200. LCD_SPU_DMA_OVSA_HPXL_VLN);
  201. }
  202. if (dplane->ctrl0 != ctrl0) {
  203. dplane->ctrl0 = ctrl0;
  204. armada_reg_queue_mod(dplane->vbl.regs, idx, ctrl0,
  205. CFG_CBSH_ENA | CFG_DMAFORMAT | CFG_DMA_FTOGGLE |
  206. CFG_DMA_HSMOOTH | CFG_DMA_TSTMODE |
  207. CFG_DMA_MOD(CFG_SWAPRB | CFG_SWAPUV | CFG_SWAPYU |
  208. CFG_YUV2RGB) | CFG_DMA_ENA,
  209. LCD_SPU_DMA_CTRL0);
  210. }
  211. if (idx) {
  212. armada_reg_queue_end(dplane->vbl.regs, idx);
  213. armada_drm_vbl_event_add(dcrtc, &dplane->vbl.update);
  214. }
  215. return 0;
  216. }
  217. static int armada_plane_disable(struct drm_plane *plane)
  218. {
  219. struct armada_plane *dplane = drm_to_armada_plane(plane);
  220. struct drm_framebuffer *fb;
  221. struct armada_crtc *dcrtc;
  222. if (!dplane->base.crtc)
  223. return 0;
  224. dcrtc = drm_to_armada_crtc(dplane->base.crtc);
  225. dcrtc->plane = NULL;
  226. spin_lock_irq(&dcrtc->irq_lock);
  227. armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update);
  228. armada_updatel(0, CFG_DMA_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0);
  229. dplane->ctrl0 = 0;
  230. spin_unlock_irq(&dcrtc->irq_lock);
  231. /* Power down the Y/U/V FIFOs */
  232. armada_updatel(CFG_PDWN16x66 | CFG_PDWN32x66, 0,
  233. dcrtc->base + LCD_SPU_SRAM_PARA1);
  234. if (plane->fb)
  235. drm_framebuffer_unreference(plane->fb);
  236. spin_lock_irq(&dplane->lock);
  237. fb = dplane->old_fb;
  238. dplane->old_fb = NULL;
  239. spin_unlock_irq(&dplane->lock);
  240. if (fb)
  241. drm_framebuffer_unreference(fb);
  242. return 0;
  243. }
  244. static void armada_plane_destroy(struct drm_plane *plane)
  245. {
  246. kfree(plane);
  247. }
  248. static int armada_plane_set_property(struct drm_plane *plane,
  249. struct drm_property *property, uint64_t val)
  250. {
  251. struct armada_private *priv = plane->dev->dev_private;
  252. struct armada_plane *dplane = drm_to_armada_plane(plane);
  253. bool update_attr = false;
  254. if (property == priv->colorkey_prop) {
  255. #define CCC(v) ((v) << 24 | (v) << 16 | (v) << 8)
  256. dplane->prop.colorkey_yr = CCC(K2R(val));
  257. dplane->prop.colorkey_ug = CCC(K2G(val));
  258. dplane->prop.colorkey_vb = CCC(K2B(val));
  259. #undef CCC
  260. update_attr = true;
  261. } else if (property == priv->colorkey_min_prop) {
  262. dplane->prop.colorkey_yr &= ~0x00ff0000;
  263. dplane->prop.colorkey_yr |= K2R(val) << 16;
  264. dplane->prop.colorkey_ug &= ~0x00ff0000;
  265. dplane->prop.colorkey_ug |= K2G(val) << 16;
  266. dplane->prop.colorkey_vb &= ~0x00ff0000;
  267. dplane->prop.colorkey_vb |= K2B(val) << 16;
  268. update_attr = true;
  269. } else if (property == priv->colorkey_max_prop) {
  270. dplane->prop.colorkey_yr &= ~0xff000000;
  271. dplane->prop.colorkey_yr |= K2R(val) << 24;
  272. dplane->prop.colorkey_ug &= ~0xff000000;
  273. dplane->prop.colorkey_ug |= K2G(val) << 24;
  274. dplane->prop.colorkey_vb &= ~0xff000000;
  275. dplane->prop.colorkey_vb |= K2B(val) << 24;
  276. update_attr = true;
  277. } else if (property == priv->colorkey_val_prop) {
  278. dplane->prop.colorkey_yr &= ~0x0000ff00;
  279. dplane->prop.colorkey_yr |= K2R(val) << 8;
  280. dplane->prop.colorkey_ug &= ~0x0000ff00;
  281. dplane->prop.colorkey_ug |= K2G(val) << 8;
  282. dplane->prop.colorkey_vb &= ~0x0000ff00;
  283. dplane->prop.colorkey_vb |= K2B(val) << 8;
  284. update_attr = true;
  285. } else if (property == priv->colorkey_alpha_prop) {
  286. dplane->prop.colorkey_yr &= ~0x000000ff;
  287. dplane->prop.colorkey_yr |= K2R(val);
  288. dplane->prop.colorkey_ug &= ~0x000000ff;
  289. dplane->prop.colorkey_ug |= K2G(val);
  290. dplane->prop.colorkey_vb &= ~0x000000ff;
  291. dplane->prop.colorkey_vb |= K2B(val);
  292. update_attr = true;
  293. } else if (property == priv->colorkey_mode_prop) {
  294. dplane->prop.colorkey_mode &= ~CFG_CKMODE_MASK;
  295. dplane->prop.colorkey_mode |= CFG_CKMODE(val);
  296. update_attr = true;
  297. } else if (property == priv->brightness_prop) {
  298. dplane->prop.brightness = val - 256;
  299. update_attr = true;
  300. } else if (property == priv->contrast_prop) {
  301. dplane->prop.contrast = val;
  302. update_attr = true;
  303. } else if (property == priv->saturation_prop) {
  304. dplane->prop.saturation = val;
  305. update_attr = true;
  306. }
  307. if (update_attr && dplane->base.crtc)
  308. armada_ovl_update_attr(&dplane->prop,
  309. drm_to_armada_crtc(dplane->base.crtc));
  310. return 0;
  311. }
  312. static const struct drm_plane_funcs armada_plane_funcs = {
  313. .update_plane = armada_plane_update,
  314. .disable_plane = armada_plane_disable,
  315. .destroy = armada_plane_destroy,
  316. .set_property = armada_plane_set_property,
  317. };
  318. static const uint32_t armada_formats[] = {
  319. DRM_FORMAT_UYVY,
  320. DRM_FORMAT_YUYV,
  321. DRM_FORMAT_YUV420,
  322. DRM_FORMAT_YVU420,
  323. DRM_FORMAT_YUV422,
  324. DRM_FORMAT_YVU422,
  325. DRM_FORMAT_VYUY,
  326. DRM_FORMAT_YVYU,
  327. DRM_FORMAT_ARGB8888,
  328. DRM_FORMAT_ABGR8888,
  329. DRM_FORMAT_XRGB8888,
  330. DRM_FORMAT_XBGR8888,
  331. DRM_FORMAT_RGB888,
  332. DRM_FORMAT_BGR888,
  333. DRM_FORMAT_ARGB1555,
  334. DRM_FORMAT_ABGR1555,
  335. DRM_FORMAT_RGB565,
  336. DRM_FORMAT_BGR565,
  337. };
  338. static struct drm_prop_enum_list armada_drm_colorkey_enum_list[] = {
  339. { CKMODE_DISABLE, "disabled" },
  340. { CKMODE_Y, "Y component" },
  341. { CKMODE_U, "U component" },
  342. { CKMODE_V, "V component" },
  343. { CKMODE_RGB, "RGB" },
  344. { CKMODE_R, "R component" },
  345. { CKMODE_G, "G component" },
  346. { CKMODE_B, "B component" },
  347. };
  348. static int armada_overlay_create_properties(struct drm_device *dev)
  349. {
  350. struct armada_private *priv = dev->dev_private;
  351. if (priv->colorkey_prop)
  352. return 0;
  353. priv->colorkey_prop = drm_property_create_range(dev, 0,
  354. "colorkey", 0, 0xffffff);
  355. priv->colorkey_min_prop = drm_property_create_range(dev, 0,
  356. "colorkey_min", 0, 0xffffff);
  357. priv->colorkey_max_prop = drm_property_create_range(dev, 0,
  358. "colorkey_max", 0, 0xffffff);
  359. priv->colorkey_val_prop = drm_property_create_range(dev, 0,
  360. "colorkey_val", 0, 0xffffff);
  361. priv->colorkey_alpha_prop = drm_property_create_range(dev, 0,
  362. "colorkey_alpha", 0, 0xffffff);
  363. priv->colorkey_mode_prop = drm_property_create_enum(dev, 0,
  364. "colorkey_mode",
  365. armada_drm_colorkey_enum_list,
  366. ARRAY_SIZE(armada_drm_colorkey_enum_list));
  367. priv->brightness_prop = drm_property_create_range(dev, 0,
  368. "brightness", 0, 256 + 255);
  369. priv->contrast_prop = drm_property_create_range(dev, 0,
  370. "contrast", 0, 0x7fff);
  371. priv->saturation_prop = drm_property_create_range(dev, 0,
  372. "saturation", 0, 0x7fff);
  373. if (!priv->colorkey_prop)
  374. return -ENOMEM;
  375. return 0;
  376. }
  377. int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
  378. {
  379. struct armada_private *priv = dev->dev_private;
  380. struct drm_mode_object *mobj;
  381. struct armada_plane *dplane;
  382. int ret;
  383. ret = armada_overlay_create_properties(dev);
  384. if (ret)
  385. return ret;
  386. dplane = kzalloc(sizeof(*dplane), GFP_KERNEL);
  387. if (!dplane)
  388. return -ENOMEM;
  389. spin_lock_init(&dplane->lock);
  390. init_waitqueue_head(&dplane->vbl.wait);
  391. armada_drm_vbl_event_init(&dplane->vbl.update, armada_plane_vbl,
  392. dplane);
  393. drm_plane_init(dev, &dplane->base, crtcs, &armada_plane_funcs,
  394. armada_formats, ARRAY_SIZE(armada_formats), false);
  395. dplane->prop.colorkey_yr = 0xfefefe00;
  396. dplane->prop.colorkey_ug = 0x01010100;
  397. dplane->prop.colorkey_vb = 0x01010100;
  398. dplane->prop.colorkey_mode = CFG_CKMODE(CKMODE_RGB);
  399. dplane->prop.brightness = 0;
  400. dplane->prop.contrast = 0x4000;
  401. dplane->prop.saturation = 0x4000;
  402. mobj = &dplane->base.base;
  403. drm_object_attach_property(mobj, priv->colorkey_prop,
  404. 0x0101fe);
  405. drm_object_attach_property(mobj, priv->colorkey_min_prop,
  406. 0x0101fe);
  407. drm_object_attach_property(mobj, priv->colorkey_max_prop,
  408. 0x0101fe);
  409. drm_object_attach_property(mobj, priv->colorkey_val_prop,
  410. 0x0101fe);
  411. drm_object_attach_property(mobj, priv->colorkey_alpha_prop,
  412. 0x000000);
  413. drm_object_attach_property(mobj, priv->colorkey_mode_prop,
  414. CKMODE_RGB);
  415. drm_object_attach_property(mobj, priv->brightness_prop, 256);
  416. drm_object_attach_property(mobj, priv->contrast_prop,
  417. dplane->prop.contrast);
  418. drm_object_attach_property(mobj, priv->saturation_prop,
  419. dplane->prop.saturation);
  420. return 0;
  421. }