gpio-intel-mid.c 11 KB

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  1. /*
  2. * Intel MID GPIO driver
  3. *
  4. * Copyright (c) 2008-2014 Intel Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. /* Supports:
  16. * Moorestown platform Langwell chip.
  17. * Medfield platform Penwell chip.
  18. * Clovertrail platform Cloverview chip.
  19. * Merrifield platform Tangier chip.
  20. */
  21. #include <linux/module.h>
  22. #include <linux/pci.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/kernel.h>
  25. #include <linux/delay.h>
  26. #include <linux/stddef.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/init.h>
  29. #include <linux/io.h>
  30. #include <linux/gpio/driver.h>
  31. #include <linux/slab.h>
  32. #include <linux/pm_runtime.h>
  33. #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
  34. #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
  35. /*
  36. * Langwell chip has 64 pins and thus there are 2 32bit registers to control
  37. * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
  38. * registers to control them, so we only define the order here instead of a
  39. * structure, to get a bit offset for a pin (use GPDR as an example):
  40. *
  41. * nreg = ngpio / 32;
  42. * reg = offset / 32;
  43. * bit = offset % 32;
  44. * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
  45. *
  46. * so the bit of reg_addr is to control pin offset's GPDR feature
  47. */
  48. enum GPIO_REG {
  49. GPLR = 0, /* pin level read-only */
  50. GPDR, /* pin direction */
  51. GPSR, /* pin set */
  52. GPCR, /* pin clear */
  53. GRER, /* rising edge detect */
  54. GFER, /* falling edge detect */
  55. GEDR, /* edge detect result */
  56. GAFR, /* alt function */
  57. };
  58. /* intel_mid gpio driver data */
  59. struct intel_mid_gpio_ddata {
  60. u16 ngpio; /* number of gpio pins */
  61. u32 gplr_offset; /* offset of first GPLR register from base */
  62. u32 flis_base; /* base address of FLIS registers */
  63. u32 flis_len; /* length of FLIS registers */
  64. u32 (*get_flis_offset)(int gpio);
  65. u32 chip_irq_type; /* chip interrupt type */
  66. };
  67. struct intel_mid_gpio {
  68. struct gpio_chip chip;
  69. void __iomem *reg_base;
  70. spinlock_t lock;
  71. struct pci_dev *pdev;
  72. };
  73. static inline struct intel_mid_gpio *to_intel_gpio_priv(struct gpio_chip *gc)
  74. {
  75. return container_of(gc, struct intel_mid_gpio, chip);
  76. }
  77. static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
  78. enum GPIO_REG reg_type)
  79. {
  80. struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
  81. unsigned nreg = chip->ngpio / 32;
  82. u8 reg = offset / 32;
  83. return priv->reg_base + reg_type * nreg * 4 + reg * 4;
  84. }
  85. static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
  86. enum GPIO_REG reg_type)
  87. {
  88. struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
  89. unsigned nreg = chip->ngpio / 32;
  90. u8 reg = offset / 16;
  91. return priv->reg_base + reg_type * nreg * 4 + reg * 4;
  92. }
  93. static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
  94. {
  95. void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
  96. u32 value = readl(gafr);
  97. int shift = (offset % 16) << 1, af = (value >> shift) & 3;
  98. if (af) {
  99. value &= ~(3 << shift);
  100. writel(value, gafr);
  101. }
  102. return 0;
  103. }
  104. static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
  105. {
  106. void __iomem *gplr = gpio_reg(chip, offset, GPLR);
  107. return readl(gplr) & BIT(offset % 32);
  108. }
  109. static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  110. {
  111. void __iomem *gpsr, *gpcr;
  112. if (value) {
  113. gpsr = gpio_reg(chip, offset, GPSR);
  114. writel(BIT(offset % 32), gpsr);
  115. } else {
  116. gpcr = gpio_reg(chip, offset, GPCR);
  117. writel(BIT(offset % 32), gpcr);
  118. }
  119. }
  120. static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  121. {
  122. struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
  123. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  124. u32 value;
  125. unsigned long flags;
  126. if (priv->pdev)
  127. pm_runtime_get(&priv->pdev->dev);
  128. spin_lock_irqsave(&priv->lock, flags);
  129. value = readl(gpdr);
  130. value &= ~BIT(offset % 32);
  131. writel(value, gpdr);
  132. spin_unlock_irqrestore(&priv->lock, flags);
  133. if (priv->pdev)
  134. pm_runtime_put(&priv->pdev->dev);
  135. return 0;
  136. }
  137. static int intel_gpio_direction_output(struct gpio_chip *chip,
  138. unsigned offset, int value)
  139. {
  140. struct intel_mid_gpio *priv = to_intel_gpio_priv(chip);
  141. void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
  142. unsigned long flags;
  143. intel_gpio_set(chip, offset, value);
  144. if (priv->pdev)
  145. pm_runtime_get(&priv->pdev->dev);
  146. spin_lock_irqsave(&priv->lock, flags);
  147. value = readl(gpdr);
  148. value |= BIT(offset % 32);
  149. writel(value, gpdr);
  150. spin_unlock_irqrestore(&priv->lock, flags);
  151. if (priv->pdev)
  152. pm_runtime_put(&priv->pdev->dev);
  153. return 0;
  154. }
  155. static int intel_mid_irq_type(struct irq_data *d, unsigned type)
  156. {
  157. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  158. struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
  159. u32 gpio = irqd_to_hwirq(d);
  160. unsigned long flags;
  161. u32 value;
  162. void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
  163. void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
  164. if (gpio >= priv->chip.ngpio)
  165. return -EINVAL;
  166. if (priv->pdev)
  167. pm_runtime_get(&priv->pdev->dev);
  168. spin_lock_irqsave(&priv->lock, flags);
  169. if (type & IRQ_TYPE_EDGE_RISING)
  170. value = readl(grer) | BIT(gpio % 32);
  171. else
  172. value = readl(grer) & (~BIT(gpio % 32));
  173. writel(value, grer);
  174. if (type & IRQ_TYPE_EDGE_FALLING)
  175. value = readl(gfer) | BIT(gpio % 32);
  176. else
  177. value = readl(gfer) & (~BIT(gpio % 32));
  178. writel(value, gfer);
  179. spin_unlock_irqrestore(&priv->lock, flags);
  180. if (priv->pdev)
  181. pm_runtime_put(&priv->pdev->dev);
  182. return 0;
  183. }
  184. static void intel_mid_irq_unmask(struct irq_data *d)
  185. {
  186. }
  187. static void intel_mid_irq_mask(struct irq_data *d)
  188. {
  189. }
  190. static struct irq_chip intel_mid_irqchip = {
  191. .name = "INTEL_MID-GPIO",
  192. .irq_mask = intel_mid_irq_mask,
  193. .irq_unmask = intel_mid_irq_unmask,
  194. .irq_set_type = intel_mid_irq_type,
  195. };
  196. static const struct intel_mid_gpio_ddata gpio_lincroft = {
  197. .ngpio = 64,
  198. };
  199. static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
  200. .ngpio = 96,
  201. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
  202. };
  203. static const struct intel_mid_gpio_ddata gpio_penwell_core = {
  204. .ngpio = 96,
  205. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
  206. };
  207. static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
  208. .ngpio = 96,
  209. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
  210. };
  211. static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
  212. .ngpio = 96,
  213. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
  214. };
  215. static const struct intel_mid_gpio_ddata gpio_tangier = {
  216. .ngpio = 192,
  217. .gplr_offset = 4,
  218. .flis_base = 0xff0c0000,
  219. .flis_len = 0x8000,
  220. .get_flis_offset = NULL,
  221. .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
  222. };
  223. static const struct pci_device_id intel_gpio_ids[] = {
  224. {
  225. /* Lincroft */
  226. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
  227. .driver_data = (kernel_ulong_t)&gpio_lincroft,
  228. },
  229. {
  230. /* Penwell AON */
  231. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
  232. .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
  233. },
  234. {
  235. /* Penwell Core */
  236. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
  237. .driver_data = (kernel_ulong_t)&gpio_penwell_core,
  238. },
  239. {
  240. /* Cloverview Aon */
  241. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
  242. .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
  243. },
  244. {
  245. /* Cloverview Core */
  246. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
  247. .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
  248. },
  249. {
  250. /* Tangier */
  251. PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
  252. .driver_data = (kernel_ulong_t)&gpio_tangier,
  253. },
  254. { 0 }
  255. };
  256. MODULE_DEVICE_TABLE(pci, intel_gpio_ids);
  257. static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc)
  258. {
  259. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  260. struct intel_mid_gpio *priv = to_intel_gpio_priv(gc);
  261. struct irq_data *data = irq_desc_get_irq_data(desc);
  262. struct irq_chip *chip = irq_data_get_irq_chip(data);
  263. u32 base, gpio, mask;
  264. unsigned long pending;
  265. void __iomem *gedr;
  266. /* check GPIO controller to check which pin triggered the interrupt */
  267. for (base = 0; base < priv->chip.ngpio; base += 32) {
  268. gedr = gpio_reg(&priv->chip, base, GEDR);
  269. while ((pending = readl(gedr))) {
  270. gpio = __ffs(pending);
  271. mask = BIT(gpio);
  272. /* Clear before handling so we can't lose an edge */
  273. writel(mask, gedr);
  274. generic_handle_irq(irq_find_mapping(gc->irqdomain,
  275. base + gpio));
  276. }
  277. }
  278. chip->irq_eoi(data);
  279. }
  280. static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv)
  281. {
  282. void __iomem *reg;
  283. unsigned base;
  284. for (base = 0; base < priv->chip.ngpio; base += 32) {
  285. /* Clear the rising-edge detect register */
  286. reg = gpio_reg(&priv->chip, base, GRER);
  287. writel(0, reg);
  288. /* Clear the falling-edge detect register */
  289. reg = gpio_reg(&priv->chip, base, GFER);
  290. writel(0, reg);
  291. /* Clear the edge detect status register */
  292. reg = gpio_reg(&priv->chip, base, GEDR);
  293. writel(~0, reg);
  294. }
  295. }
  296. static int intel_gpio_runtime_idle(struct device *dev)
  297. {
  298. int err = pm_schedule_suspend(dev, 500);
  299. return err ?: -EBUSY;
  300. }
  301. static const struct dev_pm_ops intel_gpio_pm_ops = {
  302. SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
  303. };
  304. static int intel_gpio_probe(struct pci_dev *pdev,
  305. const struct pci_device_id *id)
  306. {
  307. void __iomem *base;
  308. struct intel_mid_gpio *priv;
  309. u32 gpio_base;
  310. u32 irq_base;
  311. int retval;
  312. struct intel_mid_gpio_ddata *ddata =
  313. (struct intel_mid_gpio_ddata *)id->driver_data;
  314. retval = pcim_enable_device(pdev);
  315. if (retval)
  316. return retval;
  317. retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
  318. if (retval) {
  319. dev_err(&pdev->dev, "I/O memory mapping error\n");
  320. return retval;
  321. }
  322. base = pcim_iomap_table(pdev)[1];
  323. irq_base = readl(base);
  324. gpio_base = readl(sizeof(u32) + base);
  325. /* release the IO mapping, since we already get the info from bar1 */
  326. pcim_iounmap_regions(pdev, 1 << 1);
  327. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  328. if (!priv) {
  329. dev_err(&pdev->dev, "can't allocate chip data\n");
  330. return -ENOMEM;
  331. }
  332. priv->reg_base = pcim_iomap_table(pdev)[0];
  333. priv->chip.label = dev_name(&pdev->dev);
  334. priv->chip.dev = &pdev->dev;
  335. priv->chip.request = intel_gpio_request;
  336. priv->chip.direction_input = intel_gpio_direction_input;
  337. priv->chip.direction_output = intel_gpio_direction_output;
  338. priv->chip.get = intel_gpio_get;
  339. priv->chip.set = intel_gpio_set;
  340. priv->chip.base = gpio_base;
  341. priv->chip.ngpio = ddata->ngpio;
  342. priv->chip.can_sleep = false;
  343. priv->pdev = pdev;
  344. spin_lock_init(&priv->lock);
  345. pci_set_drvdata(pdev, priv);
  346. retval = gpiochip_add(&priv->chip);
  347. if (retval) {
  348. dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
  349. return retval;
  350. }
  351. retval = gpiochip_irqchip_add(&priv->chip,
  352. &intel_mid_irqchip,
  353. irq_base,
  354. handle_simple_irq,
  355. IRQ_TYPE_NONE);
  356. if (retval) {
  357. dev_err(&pdev->dev,
  358. "could not connect irqchip to gpiochip\n");
  359. return retval;
  360. }
  361. intel_mid_irq_init_hw(priv);
  362. gpiochip_set_chained_irqchip(&priv->chip,
  363. &intel_mid_irqchip,
  364. pdev->irq,
  365. intel_mid_irq_handler);
  366. pm_runtime_put_noidle(&pdev->dev);
  367. pm_runtime_allow(&pdev->dev);
  368. return 0;
  369. }
  370. static struct pci_driver intel_gpio_driver = {
  371. .name = "intel_mid_gpio",
  372. .id_table = intel_gpio_ids,
  373. .probe = intel_gpio_probe,
  374. .driver = {
  375. .pm = &intel_gpio_pm_ops,
  376. },
  377. };
  378. static int __init intel_gpio_init(void)
  379. {
  380. return pci_register_driver(&intel_gpio_driver);
  381. }
  382. device_initcall(intel_gpio_init);