vf_pit_timer.c 5.1 KB

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  1. /*
  2. * Copyright 2012-2013 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version 2
  7. * of the License, or (at your option) any later version.
  8. */
  9. #include <linux/interrupt.h>
  10. #include <linux/clockchips.h>
  11. #include <linux/clk.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/sched_clock.h>
  15. /*
  16. * Each pit takes 0x10 Bytes register space
  17. */
  18. #define PITMCR 0x00
  19. #define PIT0_OFFSET 0x100
  20. #define PITn_OFFSET(n) (PIT0_OFFSET + 0x10 * (n))
  21. #define PITLDVAL 0x00
  22. #define PITCVAL 0x04
  23. #define PITTCTRL 0x08
  24. #define PITTFLG 0x0c
  25. #define PITMCR_MDIS (0x1 << 1)
  26. #define PITTCTRL_TEN (0x1 << 0)
  27. #define PITTCTRL_TIE (0x1 << 1)
  28. #define PITCTRL_CHN (0x1 << 2)
  29. #define PITTFLG_TIF 0x1
  30. static void __iomem *clksrc_base;
  31. static void __iomem *clkevt_base;
  32. static unsigned long cycle_per_jiffy;
  33. static inline void pit_timer_enable(void)
  34. {
  35. __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL);
  36. }
  37. static inline void pit_timer_disable(void)
  38. {
  39. __raw_writel(0, clkevt_base + PITTCTRL);
  40. }
  41. static inline void pit_irq_acknowledge(void)
  42. {
  43. __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
  44. }
  45. static u64 pit_read_sched_clock(void)
  46. {
  47. return ~__raw_readl(clksrc_base + PITCVAL);
  48. }
  49. static int __init pit_clocksource_init(unsigned long rate)
  50. {
  51. /* set the max load value and start the clock source counter */
  52. __raw_writel(0, clksrc_base + PITTCTRL);
  53. __raw_writel(~0UL, clksrc_base + PITLDVAL);
  54. __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL);
  55. sched_clock_register(pit_read_sched_clock, 32, rate);
  56. return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,
  57. 300, 32, clocksource_mmio_readl_down);
  58. }
  59. static int pit_set_next_event(unsigned long delta,
  60. struct clock_event_device *unused)
  61. {
  62. /*
  63. * set a new value to PITLDVAL register will not restart the timer,
  64. * to abort the current cycle and start a timer period with the new
  65. * value, the timer must be disabled and enabled again.
  66. * and the PITLAVAL should be set to delta minus one according to pit
  67. * hardware requirement.
  68. */
  69. pit_timer_disable();
  70. __raw_writel(delta - 1, clkevt_base + PITLDVAL);
  71. pit_timer_enable();
  72. return 0;
  73. }
  74. static void pit_set_mode(enum clock_event_mode mode,
  75. struct clock_event_device *evt)
  76. {
  77. switch (mode) {
  78. case CLOCK_EVT_MODE_PERIODIC:
  79. pit_set_next_event(cycle_per_jiffy, evt);
  80. break;
  81. case CLOCK_EVT_MODE_SHUTDOWN:
  82. case CLOCK_EVT_MODE_UNUSED:
  83. pit_timer_disable();
  84. break;
  85. default:
  86. break;
  87. }
  88. }
  89. static irqreturn_t pit_timer_interrupt(int irq, void *dev_id)
  90. {
  91. struct clock_event_device *evt = dev_id;
  92. pit_irq_acknowledge();
  93. /*
  94. * pit hardware doesn't support oneshot, it will generate an interrupt
  95. * and reload the counter value from PITLDVAL when PITCVAL reach zero,
  96. * and start the counter again. So software need to disable the timer
  97. * to stop the counter loop in ONESHOT mode.
  98. */
  99. if (likely(evt->mode == CLOCK_EVT_MODE_ONESHOT))
  100. pit_timer_disable();
  101. evt->event_handler(evt);
  102. return IRQ_HANDLED;
  103. }
  104. static struct clock_event_device clockevent_pit = {
  105. .name = "VF pit timer",
  106. .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  107. .set_mode = pit_set_mode,
  108. .set_next_event = pit_set_next_event,
  109. .rating = 300,
  110. };
  111. static struct irqaction pit_timer_irq = {
  112. .name = "VF pit timer",
  113. .flags = IRQF_TIMER | IRQF_IRQPOLL,
  114. .handler = pit_timer_interrupt,
  115. .dev_id = &clockevent_pit,
  116. };
  117. static int __init pit_clockevent_init(unsigned long rate, int irq)
  118. {
  119. __raw_writel(0, clkevt_base + PITTCTRL);
  120. __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG);
  121. BUG_ON(setup_irq(irq, &pit_timer_irq));
  122. clockevent_pit.cpumask = cpumask_of(0);
  123. clockevent_pit.irq = irq;
  124. /*
  125. * The value for the LDVAL register trigger is calculated as:
  126. * LDVAL trigger = (period / clock period) - 1
  127. * The pit is a 32-bit down count timer, when the conter value
  128. * reaches 0, it will generate an interrupt, thus the minimal
  129. * LDVAL trigger value is 1. And then the min_delta is
  130. * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.
  131. */
  132. clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff);
  133. return 0;
  134. }
  135. static void __init pit_timer_init(struct device_node *np)
  136. {
  137. struct clk *pit_clk;
  138. void __iomem *timer_base;
  139. unsigned long clk_rate;
  140. int irq;
  141. timer_base = of_iomap(np, 0);
  142. BUG_ON(!timer_base);
  143. /*
  144. * PIT0 and PIT1 can be chained to build a 64-bit timer,
  145. * so choose PIT2 as clocksource, PIT3 as clockevent device,
  146. * and leave PIT0 and PIT1 unused for anyone else who needs them.
  147. */
  148. clksrc_base = timer_base + PITn_OFFSET(2);
  149. clkevt_base = timer_base + PITn_OFFSET(3);
  150. irq = irq_of_parse_and_map(np, 0);
  151. BUG_ON(irq <= 0);
  152. pit_clk = of_clk_get(np, 0);
  153. BUG_ON(IS_ERR(pit_clk));
  154. BUG_ON(clk_prepare_enable(pit_clk));
  155. clk_rate = clk_get_rate(pit_clk);
  156. cycle_per_jiffy = clk_rate / (HZ);
  157. /* enable the pit module */
  158. __raw_writel(~PITMCR_MDIS, timer_base + PITMCR);
  159. BUG_ON(pit_clocksource_init(clk_rate));
  160. pit_clockevent_init(clk_rate, irq);
  161. }
  162. CLOCKSOURCE_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);