berlin2-pll.c 2.9 KB

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  1. /*
  2. * Copyright (c) 2014 Marvell Technology Group Ltd.
  3. *
  4. * Alexandre Belloni <alexandre.belloni@free-electrons.com>
  5. * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/clk-provider.h>
  20. #include <linux/io.h>
  21. #include <linux/kernel.h>
  22. #include <linux/of.h>
  23. #include <linux/of_address.h>
  24. #include <linux/slab.h>
  25. #include <asm/div64.h>
  26. #include "berlin2-div.h"
  27. #include "berlin2-pll.h"
  28. struct berlin2_pll {
  29. struct clk_hw hw;
  30. void __iomem *base;
  31. struct berlin2_pll_map map;
  32. };
  33. #define to_berlin2_pll(hw) container_of(hw, struct berlin2_pll, hw)
  34. #define SPLL_CTRL0 0x00
  35. #define SPLL_CTRL1 0x04
  36. #define SPLL_CTRL2 0x08
  37. #define SPLL_CTRL3 0x0c
  38. #define SPLL_CTRL4 0x10
  39. #define FBDIV_MASK 0x1ff
  40. #define RFDIV_MASK 0x1f
  41. #define DIVSEL_MASK 0xf
  42. /*
  43. * The output frequency formula for the pll is:
  44. * clkout = fbdiv / refdiv * parent / vcodiv
  45. */
  46. static unsigned long
  47. berlin2_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
  48. {
  49. struct berlin2_pll *pll = to_berlin2_pll(hw);
  50. struct berlin2_pll_map *map = &pll->map;
  51. u32 val, fbdiv, rfdiv, vcodivsel, vcodiv;
  52. u64 rate = parent_rate;
  53. val = readl_relaxed(pll->base + SPLL_CTRL0);
  54. fbdiv = (val >> map->fbdiv_shift) & FBDIV_MASK;
  55. rfdiv = (val >> map->rfdiv_shift) & RFDIV_MASK;
  56. if (rfdiv == 0) {
  57. pr_warn("%s has zero rfdiv\n", __clk_get_name(hw->clk));
  58. rfdiv = 1;
  59. }
  60. val = readl_relaxed(pll->base + SPLL_CTRL1);
  61. vcodivsel = (val >> map->divsel_shift) & DIVSEL_MASK;
  62. vcodiv = map->vcodiv[vcodivsel];
  63. if (vcodiv == 0) {
  64. pr_warn("%s has zero vcodiv (index %d)\n",
  65. __clk_get_name(hw->clk), vcodivsel);
  66. vcodiv = 1;
  67. }
  68. rate *= fbdiv * map->mult;
  69. do_div(rate, rfdiv * vcodiv);
  70. return (unsigned long)rate;
  71. }
  72. static const struct clk_ops berlin2_pll_ops = {
  73. .recalc_rate = berlin2_pll_recalc_rate,
  74. };
  75. struct clk * __init
  76. berlin2_pll_register(const struct berlin2_pll_map *map,
  77. void __iomem *base, const char *name,
  78. const char *parent_name, unsigned long flags)
  79. {
  80. struct clk_init_data init;
  81. struct berlin2_pll *pll;
  82. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  83. if (!pll)
  84. return ERR_PTR(-ENOMEM);
  85. /* copy pll_map to allow __initconst */
  86. memcpy(&pll->map, map, sizeof(*map));
  87. pll->base = base;
  88. pll->hw.init = &init;
  89. init.name = name;
  90. init.ops = &berlin2_pll_ops;
  91. init.parent_names = &parent_name;
  92. init.num_parents = 1;
  93. init.flags = flags;
  94. return clk_register(NULL, &pll->hw);
  95. }