tpm_tis.c 25 KB

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  1. /*
  2. * Copyright (C) 2005, 2006 IBM Corporation
  3. * Copyright (C) 2014 Intel Corporation
  4. *
  5. * Authors:
  6. * Leendert van Doorn <leendert@watson.ibm.com>
  7. * Kylene Hall <kjhall@us.ibm.com>
  8. *
  9. * Maintained by: <tpmdd-devel@lists.sourceforge.net>
  10. *
  11. * Device driver for TCG/TCPA TPM (trusted platform module).
  12. * Specifications at www.trustedcomputinggroup.org
  13. *
  14. * This device driver implements the TPM interface as defined in
  15. * the TCG TPM Interface Spec version 1.2, revision 1.0.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation, version 2 of the
  20. * License.
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/pnp.h>
  26. #include <linux/slab.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/wait.h>
  29. #include <linux/acpi.h>
  30. #include <linux/freezer.h>
  31. #include "tpm.h"
  32. enum tis_access {
  33. TPM_ACCESS_VALID = 0x80,
  34. TPM_ACCESS_ACTIVE_LOCALITY = 0x20,
  35. TPM_ACCESS_REQUEST_PENDING = 0x04,
  36. TPM_ACCESS_REQUEST_USE = 0x02,
  37. };
  38. enum tis_status {
  39. TPM_STS_VALID = 0x80,
  40. TPM_STS_COMMAND_READY = 0x40,
  41. TPM_STS_GO = 0x20,
  42. TPM_STS_DATA_AVAIL = 0x10,
  43. TPM_STS_DATA_EXPECT = 0x08,
  44. };
  45. enum tis_int_flags {
  46. TPM_GLOBAL_INT_ENABLE = 0x80000000,
  47. TPM_INTF_BURST_COUNT_STATIC = 0x100,
  48. TPM_INTF_CMD_READY_INT = 0x080,
  49. TPM_INTF_INT_EDGE_FALLING = 0x040,
  50. TPM_INTF_INT_EDGE_RISING = 0x020,
  51. TPM_INTF_INT_LEVEL_LOW = 0x010,
  52. TPM_INTF_INT_LEVEL_HIGH = 0x008,
  53. TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
  54. TPM_INTF_STS_VALID_INT = 0x002,
  55. TPM_INTF_DATA_AVAIL_INT = 0x001,
  56. };
  57. enum tis_defaults {
  58. TIS_MEM_BASE = 0xFED40000,
  59. TIS_MEM_LEN = 0x5000,
  60. TIS_SHORT_TIMEOUT = 750, /* ms */
  61. TIS_LONG_TIMEOUT = 2000, /* 2 sec */
  62. };
  63. /* Some timeout values are needed before it is known whether the chip is
  64. * TPM 1.0 or TPM 2.0.
  65. */
  66. #define TIS_TIMEOUT_A_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
  67. #define TIS_TIMEOUT_B_MAX max(TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
  68. #define TIS_TIMEOUT_C_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
  69. #define TIS_TIMEOUT_D_MAX max(TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
  70. #define TPM_ACCESS(l) (0x0000 | ((l) << 12))
  71. #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
  72. #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
  73. #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
  74. #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
  75. #define TPM_STS(l) (0x0018 | ((l) << 12))
  76. #define TPM_STS3(l) (0x001b | ((l) << 12))
  77. #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
  78. #define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
  79. #define TPM_RID(l) (0x0F04 | ((l) << 12))
  80. struct priv_data {
  81. bool irq_tested;
  82. };
  83. #if defined(CONFIG_PNP) && defined(CONFIG_ACPI)
  84. static int is_itpm(struct pnp_dev *dev)
  85. {
  86. struct acpi_device *acpi = pnp_acpi_device(dev);
  87. struct acpi_hardware_id *id;
  88. if (!acpi)
  89. return 0;
  90. list_for_each_entry(id, &acpi->pnp.ids, list) {
  91. if (!strcmp("INTC0102", id->id))
  92. return 1;
  93. }
  94. return 0;
  95. }
  96. #else
  97. static inline int is_itpm(struct pnp_dev *dev)
  98. {
  99. return 0;
  100. }
  101. #endif
  102. /* Before we attempt to access the TPM we must see that the valid bit is set.
  103. * The specification says that this bit is 0 at reset and remains 0 until the
  104. * 'TPM has gone through its self test and initialization and has established
  105. * correct values in the other bits.' */
  106. static int wait_startup(struct tpm_chip *chip, int l)
  107. {
  108. unsigned long stop = jiffies + chip->vendor.timeout_a;
  109. do {
  110. if (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  111. TPM_ACCESS_VALID)
  112. return 0;
  113. msleep(TPM_TIMEOUT);
  114. } while (time_before(jiffies, stop));
  115. return -1;
  116. }
  117. static int check_locality(struct tpm_chip *chip, int l)
  118. {
  119. if ((ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  120. (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID)) ==
  121. (TPM_ACCESS_ACTIVE_LOCALITY | TPM_ACCESS_VALID))
  122. return chip->vendor.locality = l;
  123. return -1;
  124. }
  125. static void release_locality(struct tpm_chip *chip, int l, int force)
  126. {
  127. if (force || (ioread8(chip->vendor.iobase + TPM_ACCESS(l)) &
  128. (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID)) ==
  129. (TPM_ACCESS_REQUEST_PENDING | TPM_ACCESS_VALID))
  130. iowrite8(TPM_ACCESS_ACTIVE_LOCALITY,
  131. chip->vendor.iobase + TPM_ACCESS(l));
  132. }
  133. static int request_locality(struct tpm_chip *chip, int l)
  134. {
  135. unsigned long stop, timeout;
  136. long rc;
  137. if (check_locality(chip, l) >= 0)
  138. return l;
  139. iowrite8(TPM_ACCESS_REQUEST_USE,
  140. chip->vendor.iobase + TPM_ACCESS(l));
  141. stop = jiffies + chip->vendor.timeout_a;
  142. if (chip->vendor.irq) {
  143. again:
  144. timeout = stop - jiffies;
  145. if ((long)timeout <= 0)
  146. return -1;
  147. rc = wait_event_interruptible_timeout(chip->vendor.int_queue,
  148. (check_locality
  149. (chip, l) >= 0),
  150. timeout);
  151. if (rc > 0)
  152. return l;
  153. if (rc == -ERESTARTSYS && freezing(current)) {
  154. clear_thread_flag(TIF_SIGPENDING);
  155. goto again;
  156. }
  157. } else {
  158. /* wait for burstcount */
  159. do {
  160. if (check_locality(chip, l) >= 0)
  161. return l;
  162. msleep(TPM_TIMEOUT);
  163. }
  164. while (time_before(jiffies, stop));
  165. }
  166. return -1;
  167. }
  168. static u8 tpm_tis_status(struct tpm_chip *chip)
  169. {
  170. return ioread8(chip->vendor.iobase +
  171. TPM_STS(chip->vendor.locality));
  172. }
  173. static void tpm_tis_ready(struct tpm_chip *chip)
  174. {
  175. /* this causes the current command to be aborted */
  176. iowrite8(TPM_STS_COMMAND_READY,
  177. chip->vendor.iobase + TPM_STS(chip->vendor.locality));
  178. }
  179. static int get_burstcount(struct tpm_chip *chip)
  180. {
  181. unsigned long stop;
  182. int burstcnt;
  183. /* wait for burstcount */
  184. /* which timeout value, spec has 2 answers (c & d) */
  185. stop = jiffies + chip->vendor.timeout_d;
  186. do {
  187. burstcnt = ioread8(chip->vendor.iobase +
  188. TPM_STS(chip->vendor.locality) + 1);
  189. burstcnt += ioread8(chip->vendor.iobase +
  190. TPM_STS(chip->vendor.locality) +
  191. 2) << 8;
  192. if (burstcnt)
  193. return burstcnt;
  194. msleep(TPM_TIMEOUT);
  195. } while (time_before(jiffies, stop));
  196. return -EBUSY;
  197. }
  198. static int recv_data(struct tpm_chip *chip, u8 *buf, size_t count)
  199. {
  200. int size = 0, burstcnt;
  201. while (size < count &&
  202. wait_for_tpm_stat(chip,
  203. TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  204. chip->vendor.timeout_c,
  205. &chip->vendor.read_queue, true)
  206. == 0) {
  207. burstcnt = get_burstcount(chip);
  208. for (; burstcnt > 0 && size < count; burstcnt--)
  209. buf[size++] = ioread8(chip->vendor.iobase +
  210. TPM_DATA_FIFO(chip->vendor.
  211. locality));
  212. }
  213. return size;
  214. }
  215. static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count)
  216. {
  217. int size = 0;
  218. int expected, status;
  219. if (count < TPM_HEADER_SIZE) {
  220. size = -EIO;
  221. goto out;
  222. }
  223. /* read first 10 bytes, including tag, paramsize, and result */
  224. if ((size =
  225. recv_data(chip, buf, TPM_HEADER_SIZE)) < TPM_HEADER_SIZE) {
  226. dev_err(chip->pdev, "Unable to read header\n");
  227. goto out;
  228. }
  229. expected = be32_to_cpu(*(__be32 *) (buf + 2));
  230. if (expected > count) {
  231. size = -EIO;
  232. goto out;
  233. }
  234. if ((size +=
  235. recv_data(chip, &buf[TPM_HEADER_SIZE],
  236. expected - TPM_HEADER_SIZE)) < expected) {
  237. dev_err(chip->pdev, "Unable to read remainder of result\n");
  238. size = -ETIME;
  239. goto out;
  240. }
  241. wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  242. &chip->vendor.int_queue, false);
  243. status = tpm_tis_status(chip);
  244. if (status & TPM_STS_DATA_AVAIL) { /* retry? */
  245. dev_err(chip->pdev, "Error left over data\n");
  246. size = -EIO;
  247. goto out;
  248. }
  249. out:
  250. tpm_tis_ready(chip);
  251. release_locality(chip, chip->vendor.locality, 0);
  252. return size;
  253. }
  254. static bool itpm;
  255. module_param(itpm, bool, 0444);
  256. MODULE_PARM_DESC(itpm, "Force iTPM workarounds (found on some Lenovo laptops)");
  257. /*
  258. * If interrupts are used (signaled by an irq set in the vendor structure)
  259. * tpm.c can skip polling for the data to be available as the interrupt is
  260. * waited for here
  261. */
  262. static int tpm_tis_send_data(struct tpm_chip *chip, u8 *buf, size_t len)
  263. {
  264. int rc, status, burstcnt;
  265. size_t count = 0;
  266. if (request_locality(chip, 0) < 0)
  267. return -EBUSY;
  268. status = tpm_tis_status(chip);
  269. if ((status & TPM_STS_COMMAND_READY) == 0) {
  270. tpm_tis_ready(chip);
  271. if (wait_for_tpm_stat
  272. (chip, TPM_STS_COMMAND_READY, chip->vendor.timeout_b,
  273. &chip->vendor.int_queue, false) < 0) {
  274. rc = -ETIME;
  275. goto out_err;
  276. }
  277. }
  278. while (count < len - 1) {
  279. burstcnt = get_burstcount(chip);
  280. for (; burstcnt > 0 && count < len - 1; burstcnt--) {
  281. iowrite8(buf[count], chip->vendor.iobase +
  282. TPM_DATA_FIFO(chip->vendor.locality));
  283. count++;
  284. }
  285. wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  286. &chip->vendor.int_queue, false);
  287. status = tpm_tis_status(chip);
  288. if (!itpm && (status & TPM_STS_DATA_EXPECT) == 0) {
  289. rc = -EIO;
  290. goto out_err;
  291. }
  292. }
  293. /* write last byte */
  294. iowrite8(buf[count],
  295. chip->vendor.iobase + TPM_DATA_FIFO(chip->vendor.locality));
  296. wait_for_tpm_stat(chip, TPM_STS_VALID, chip->vendor.timeout_c,
  297. &chip->vendor.int_queue, false);
  298. status = tpm_tis_status(chip);
  299. if ((status & TPM_STS_DATA_EXPECT) != 0) {
  300. rc = -EIO;
  301. goto out_err;
  302. }
  303. return 0;
  304. out_err:
  305. tpm_tis_ready(chip);
  306. release_locality(chip, chip->vendor.locality, 0);
  307. return rc;
  308. }
  309. static void disable_interrupts(struct tpm_chip *chip)
  310. {
  311. u32 intmask;
  312. intmask =
  313. ioread32(chip->vendor.iobase +
  314. TPM_INT_ENABLE(chip->vendor.locality));
  315. intmask &= ~TPM_GLOBAL_INT_ENABLE;
  316. iowrite32(intmask,
  317. chip->vendor.iobase +
  318. TPM_INT_ENABLE(chip->vendor.locality));
  319. free_irq(chip->vendor.irq, chip);
  320. chip->vendor.irq = 0;
  321. }
  322. /*
  323. * If interrupts are used (signaled by an irq set in the vendor structure)
  324. * tpm.c can skip polling for the data to be available as the interrupt is
  325. * waited for here
  326. */
  327. static int tpm_tis_send_main(struct tpm_chip *chip, u8 *buf, size_t len)
  328. {
  329. int rc;
  330. u32 ordinal;
  331. unsigned long dur;
  332. rc = tpm_tis_send_data(chip, buf, len);
  333. if (rc < 0)
  334. return rc;
  335. /* go and do it */
  336. iowrite8(TPM_STS_GO,
  337. chip->vendor.iobase + TPM_STS(chip->vendor.locality));
  338. if (chip->vendor.irq) {
  339. ordinal = be32_to_cpu(*((__be32 *) (buf + 6)));
  340. if (chip->flags & TPM_CHIP_FLAG_TPM2)
  341. dur = tpm2_calc_ordinal_duration(chip, ordinal);
  342. else
  343. dur = tpm_calc_ordinal_duration(chip, ordinal);
  344. if (wait_for_tpm_stat
  345. (chip, TPM_STS_DATA_AVAIL | TPM_STS_VALID, dur,
  346. &chip->vendor.read_queue, false) < 0) {
  347. rc = -ETIME;
  348. goto out_err;
  349. }
  350. }
  351. return len;
  352. out_err:
  353. tpm_tis_ready(chip);
  354. release_locality(chip, chip->vendor.locality, 0);
  355. return rc;
  356. }
  357. static int tpm_tis_send(struct tpm_chip *chip, u8 *buf, size_t len)
  358. {
  359. int rc, irq;
  360. struct priv_data *priv = chip->vendor.priv;
  361. if (!chip->vendor.irq || priv->irq_tested)
  362. return tpm_tis_send_main(chip, buf, len);
  363. /* Verify receipt of the expected IRQ */
  364. irq = chip->vendor.irq;
  365. chip->vendor.irq = 0;
  366. rc = tpm_tis_send_main(chip, buf, len);
  367. chip->vendor.irq = irq;
  368. if (!priv->irq_tested)
  369. msleep(1);
  370. if (!priv->irq_tested) {
  371. disable_interrupts(chip);
  372. dev_err(chip->pdev,
  373. FW_BUG "TPM interrupt not working, polling instead\n");
  374. }
  375. priv->irq_tested = true;
  376. return rc;
  377. }
  378. struct tis_vendor_timeout_override {
  379. u32 did_vid;
  380. unsigned long timeout_us[4];
  381. };
  382. static const struct tis_vendor_timeout_override vendor_timeout_overrides[] = {
  383. /* Atmel 3204 */
  384. { 0x32041114, { (TIS_SHORT_TIMEOUT*1000), (TIS_LONG_TIMEOUT*1000),
  385. (TIS_SHORT_TIMEOUT*1000), (TIS_SHORT_TIMEOUT*1000) } },
  386. };
  387. static bool tpm_tis_update_timeouts(struct tpm_chip *chip,
  388. unsigned long *timeout_cap)
  389. {
  390. int i;
  391. u32 did_vid;
  392. did_vid = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
  393. for (i = 0; i != ARRAY_SIZE(vendor_timeout_overrides); i++) {
  394. if (vendor_timeout_overrides[i].did_vid != did_vid)
  395. continue;
  396. memcpy(timeout_cap, vendor_timeout_overrides[i].timeout_us,
  397. sizeof(vendor_timeout_overrides[i].timeout_us));
  398. return true;
  399. }
  400. return false;
  401. }
  402. /*
  403. * Early probing for iTPM with STS_DATA_EXPECT flaw.
  404. * Try sending command without itpm flag set and if that
  405. * fails, repeat with itpm flag set.
  406. */
  407. static int probe_itpm(struct tpm_chip *chip)
  408. {
  409. int rc = 0;
  410. u8 cmd_getticks[] = {
  411. 0x00, 0xc1, 0x00, 0x00, 0x00, 0x0a,
  412. 0x00, 0x00, 0x00, 0xf1
  413. };
  414. size_t len = sizeof(cmd_getticks);
  415. bool rem_itpm = itpm;
  416. u16 vendor = ioread16(chip->vendor.iobase + TPM_DID_VID(0));
  417. /* probe only iTPMS */
  418. if (vendor != TPM_VID_INTEL)
  419. return 0;
  420. itpm = false;
  421. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  422. if (rc == 0)
  423. goto out;
  424. tpm_tis_ready(chip);
  425. release_locality(chip, chip->vendor.locality, 0);
  426. itpm = true;
  427. rc = tpm_tis_send_data(chip, cmd_getticks, len);
  428. if (rc == 0) {
  429. dev_info(chip->pdev, "Detected an iTPM.\n");
  430. rc = 1;
  431. } else
  432. rc = -EFAULT;
  433. out:
  434. itpm = rem_itpm;
  435. tpm_tis_ready(chip);
  436. release_locality(chip, chip->vendor.locality, 0);
  437. return rc;
  438. }
  439. static bool tpm_tis_req_canceled(struct tpm_chip *chip, u8 status)
  440. {
  441. switch (chip->vendor.manufacturer_id) {
  442. case TPM_VID_WINBOND:
  443. return ((status == TPM_STS_VALID) ||
  444. (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY)));
  445. case TPM_VID_STM:
  446. return (status == (TPM_STS_VALID | TPM_STS_COMMAND_READY));
  447. default:
  448. return (status == TPM_STS_COMMAND_READY);
  449. }
  450. }
  451. static const struct tpm_class_ops tpm_tis = {
  452. .status = tpm_tis_status,
  453. .recv = tpm_tis_recv,
  454. .send = tpm_tis_send,
  455. .cancel = tpm_tis_ready,
  456. .update_timeouts = tpm_tis_update_timeouts,
  457. .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  458. .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID,
  459. .req_canceled = tpm_tis_req_canceled,
  460. };
  461. static irqreturn_t tis_int_probe(int irq, void *dev_id)
  462. {
  463. struct tpm_chip *chip = dev_id;
  464. u32 interrupt;
  465. interrupt = ioread32(chip->vendor.iobase +
  466. TPM_INT_STATUS(chip->vendor.locality));
  467. if (interrupt == 0)
  468. return IRQ_NONE;
  469. chip->vendor.probed_irq = irq;
  470. /* Clear interrupts handled with TPM_EOI */
  471. iowrite32(interrupt,
  472. chip->vendor.iobase +
  473. TPM_INT_STATUS(chip->vendor.locality));
  474. return IRQ_HANDLED;
  475. }
  476. static irqreturn_t tis_int_handler(int dummy, void *dev_id)
  477. {
  478. struct tpm_chip *chip = dev_id;
  479. u32 interrupt;
  480. int i;
  481. interrupt = ioread32(chip->vendor.iobase +
  482. TPM_INT_STATUS(chip->vendor.locality));
  483. if (interrupt == 0)
  484. return IRQ_NONE;
  485. ((struct priv_data *)chip->vendor.priv)->irq_tested = true;
  486. if (interrupt & TPM_INTF_DATA_AVAIL_INT)
  487. wake_up_interruptible(&chip->vendor.read_queue);
  488. if (interrupt & TPM_INTF_LOCALITY_CHANGE_INT)
  489. for (i = 0; i < 5; i++)
  490. if (check_locality(chip, i) >= 0)
  491. break;
  492. if (interrupt &
  493. (TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_STS_VALID_INT |
  494. TPM_INTF_CMD_READY_INT))
  495. wake_up_interruptible(&chip->vendor.int_queue);
  496. /* Clear interrupts handled with TPM_EOI */
  497. iowrite32(interrupt,
  498. chip->vendor.iobase +
  499. TPM_INT_STATUS(chip->vendor.locality));
  500. ioread32(chip->vendor.iobase + TPM_INT_STATUS(chip->vendor.locality));
  501. return IRQ_HANDLED;
  502. }
  503. static bool interrupts = true;
  504. module_param(interrupts, bool, 0444);
  505. MODULE_PARM_DESC(interrupts, "Enable interrupts");
  506. static void tpm_tis_remove(struct tpm_chip *chip)
  507. {
  508. if (chip->flags & TPM_CHIP_FLAG_TPM2)
  509. tpm2_shutdown(chip, TPM2_SU_CLEAR);
  510. iowrite32(~TPM_GLOBAL_INT_ENABLE &
  511. ioread32(chip->vendor.iobase +
  512. TPM_INT_ENABLE(chip->vendor.
  513. locality)),
  514. chip->vendor.iobase +
  515. TPM_INT_ENABLE(chip->vendor.locality));
  516. release_locality(chip, chip->vendor.locality, 1);
  517. }
  518. static int tpm_tis_init(struct device *dev, acpi_handle acpi_dev_handle,
  519. resource_size_t start, resource_size_t len,
  520. unsigned int irq)
  521. {
  522. u32 vendor, intfcaps, intmask;
  523. int rc, i, irq_s, irq_e, probe;
  524. struct tpm_chip *chip;
  525. struct priv_data *priv;
  526. priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL);
  527. if (priv == NULL)
  528. return -ENOMEM;
  529. chip = tpmm_chip_alloc(dev, &tpm_tis);
  530. if (IS_ERR(chip))
  531. return PTR_ERR(chip);
  532. chip->vendor.priv = priv;
  533. #ifdef CONFIG_ACPI
  534. chip->acpi_dev_handle = acpi_dev_handle;
  535. #endif
  536. chip->vendor.iobase = devm_ioremap(dev, start, len);
  537. if (!chip->vendor.iobase)
  538. return -EIO;
  539. /* Maximum timeouts */
  540. chip->vendor.timeout_a = TIS_TIMEOUT_A_MAX;
  541. chip->vendor.timeout_b = TIS_TIMEOUT_B_MAX;
  542. chip->vendor.timeout_c = TIS_TIMEOUT_C_MAX;
  543. chip->vendor.timeout_d = TIS_TIMEOUT_D_MAX;
  544. if (wait_startup(chip, 0) != 0) {
  545. rc = -ENODEV;
  546. goto out_err;
  547. }
  548. if (request_locality(chip, 0) != 0) {
  549. rc = -ENODEV;
  550. goto out_err;
  551. }
  552. rc = tpm2_probe(chip);
  553. if (rc)
  554. goto out_err;
  555. vendor = ioread32(chip->vendor.iobase + TPM_DID_VID(0));
  556. chip->vendor.manufacturer_id = vendor;
  557. dev_info(dev, "%s TPM (device-id 0x%X, rev-id %d)\n",
  558. (chip->flags & TPM_CHIP_FLAG_TPM2) ? "2.0" : "1.2",
  559. vendor >> 16, ioread8(chip->vendor.iobase + TPM_RID(0)));
  560. if (!itpm) {
  561. probe = probe_itpm(chip);
  562. if (probe < 0) {
  563. rc = -ENODEV;
  564. goto out_err;
  565. }
  566. itpm = !!probe;
  567. }
  568. if (itpm)
  569. dev_info(dev, "Intel iTPM workaround enabled\n");
  570. /* Figure out the capabilities */
  571. intfcaps =
  572. ioread32(chip->vendor.iobase +
  573. TPM_INTF_CAPS(chip->vendor.locality));
  574. dev_dbg(dev, "TPM interface capabilities (0x%x):\n",
  575. intfcaps);
  576. if (intfcaps & TPM_INTF_BURST_COUNT_STATIC)
  577. dev_dbg(dev, "\tBurst Count Static\n");
  578. if (intfcaps & TPM_INTF_CMD_READY_INT)
  579. dev_dbg(dev, "\tCommand Ready Int Support\n");
  580. if (intfcaps & TPM_INTF_INT_EDGE_FALLING)
  581. dev_dbg(dev, "\tInterrupt Edge Falling\n");
  582. if (intfcaps & TPM_INTF_INT_EDGE_RISING)
  583. dev_dbg(dev, "\tInterrupt Edge Rising\n");
  584. if (intfcaps & TPM_INTF_INT_LEVEL_LOW)
  585. dev_dbg(dev, "\tInterrupt Level Low\n");
  586. if (intfcaps & TPM_INTF_INT_LEVEL_HIGH)
  587. dev_dbg(dev, "\tInterrupt Level High\n");
  588. if (intfcaps & TPM_INTF_LOCALITY_CHANGE_INT)
  589. dev_dbg(dev, "\tLocality Change Int Support\n");
  590. if (intfcaps & TPM_INTF_STS_VALID_INT)
  591. dev_dbg(dev, "\tSts Valid Int Support\n");
  592. if (intfcaps & TPM_INTF_DATA_AVAIL_INT)
  593. dev_dbg(dev, "\tData Avail Int Support\n");
  594. /* INTERRUPT Setup */
  595. init_waitqueue_head(&chip->vendor.read_queue);
  596. init_waitqueue_head(&chip->vendor.int_queue);
  597. intmask =
  598. ioread32(chip->vendor.iobase +
  599. TPM_INT_ENABLE(chip->vendor.locality));
  600. intmask |= TPM_INTF_CMD_READY_INT
  601. | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
  602. | TPM_INTF_STS_VALID_INT;
  603. iowrite32(intmask,
  604. chip->vendor.iobase +
  605. TPM_INT_ENABLE(chip->vendor.locality));
  606. if (interrupts)
  607. chip->vendor.irq = irq;
  608. if (interrupts && !chip->vendor.irq) {
  609. irq_s =
  610. ioread8(chip->vendor.iobase +
  611. TPM_INT_VECTOR(chip->vendor.locality));
  612. if (irq_s) {
  613. irq_e = irq_s;
  614. } else {
  615. irq_s = 3;
  616. irq_e = 15;
  617. }
  618. for (i = irq_s; i <= irq_e && chip->vendor.irq == 0; i++) {
  619. iowrite8(i, chip->vendor.iobase +
  620. TPM_INT_VECTOR(chip->vendor.locality));
  621. if (devm_request_irq
  622. (dev, i, tis_int_probe, IRQF_SHARED,
  623. chip->devname, chip) != 0) {
  624. dev_info(chip->pdev,
  625. "Unable to request irq: %d for probe\n",
  626. i);
  627. continue;
  628. }
  629. /* Clear all existing */
  630. iowrite32(ioread32
  631. (chip->vendor.iobase +
  632. TPM_INT_STATUS(chip->vendor.locality)),
  633. chip->vendor.iobase +
  634. TPM_INT_STATUS(chip->vendor.locality));
  635. /* Turn on */
  636. iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
  637. chip->vendor.iobase +
  638. TPM_INT_ENABLE(chip->vendor.locality));
  639. chip->vendor.probed_irq = 0;
  640. /* Generate Interrupts */
  641. if (chip->flags & TPM_CHIP_FLAG_TPM2)
  642. tpm2_gen_interrupt(chip);
  643. else
  644. tpm_gen_interrupt(chip);
  645. chip->vendor.irq = chip->vendor.probed_irq;
  646. /* free_irq will call into tis_int_probe;
  647. clear all irqs we haven't seen while doing
  648. tpm_gen_interrupt */
  649. iowrite32(ioread32
  650. (chip->vendor.iobase +
  651. TPM_INT_STATUS(chip->vendor.locality)),
  652. chip->vendor.iobase +
  653. TPM_INT_STATUS(chip->vendor.locality));
  654. /* Turn off */
  655. iowrite32(intmask,
  656. chip->vendor.iobase +
  657. TPM_INT_ENABLE(chip->vendor.locality));
  658. }
  659. }
  660. if (chip->vendor.irq) {
  661. iowrite8(chip->vendor.irq,
  662. chip->vendor.iobase +
  663. TPM_INT_VECTOR(chip->vendor.locality));
  664. if (devm_request_irq
  665. (dev, chip->vendor.irq, tis_int_handler, IRQF_SHARED,
  666. chip->devname, chip) != 0) {
  667. dev_info(chip->pdev,
  668. "Unable to request irq: %d for use\n",
  669. chip->vendor.irq);
  670. chip->vendor.irq = 0;
  671. } else {
  672. /* Clear all existing */
  673. iowrite32(ioread32
  674. (chip->vendor.iobase +
  675. TPM_INT_STATUS(chip->vendor.locality)),
  676. chip->vendor.iobase +
  677. TPM_INT_STATUS(chip->vendor.locality));
  678. /* Turn on */
  679. iowrite32(intmask | TPM_GLOBAL_INT_ENABLE,
  680. chip->vendor.iobase +
  681. TPM_INT_ENABLE(chip->vendor.locality));
  682. }
  683. }
  684. if (chip->flags & TPM_CHIP_FLAG_TPM2) {
  685. chip->vendor.timeout_a = msecs_to_jiffies(TPM2_TIMEOUT_A);
  686. chip->vendor.timeout_b = msecs_to_jiffies(TPM2_TIMEOUT_B);
  687. chip->vendor.timeout_c = msecs_to_jiffies(TPM2_TIMEOUT_C);
  688. chip->vendor.timeout_d = msecs_to_jiffies(TPM2_TIMEOUT_D);
  689. chip->vendor.duration[TPM_SHORT] =
  690. msecs_to_jiffies(TPM2_DURATION_SHORT);
  691. chip->vendor.duration[TPM_MEDIUM] =
  692. msecs_to_jiffies(TPM2_DURATION_MEDIUM);
  693. chip->vendor.duration[TPM_LONG] =
  694. msecs_to_jiffies(TPM2_DURATION_LONG);
  695. rc = tpm2_do_selftest(chip);
  696. if (rc == TPM2_RC_INITIALIZE) {
  697. dev_warn(dev, "Firmware has not started TPM\n");
  698. rc = tpm2_startup(chip, TPM2_SU_CLEAR);
  699. if (!rc)
  700. rc = tpm2_do_selftest(chip);
  701. }
  702. if (rc) {
  703. dev_err(dev, "TPM self test failed\n");
  704. if (rc > 0)
  705. rc = -ENODEV;
  706. goto out_err;
  707. }
  708. } else {
  709. if (tpm_get_timeouts(chip)) {
  710. dev_err(dev, "Could not get TPM timeouts and durations\n");
  711. rc = -ENODEV;
  712. goto out_err;
  713. }
  714. if (tpm_do_selftest(chip)) {
  715. dev_err(dev, "TPM self test failed\n");
  716. rc = -ENODEV;
  717. goto out_err;
  718. }
  719. }
  720. return tpm_chip_register(chip);
  721. out_err:
  722. tpm_tis_remove(chip);
  723. return rc;
  724. }
  725. #ifdef CONFIG_PM_SLEEP
  726. static void tpm_tis_reenable_interrupts(struct tpm_chip *chip)
  727. {
  728. u32 intmask;
  729. /* reenable interrupts that device may have lost or
  730. BIOS/firmware may have disabled */
  731. iowrite8(chip->vendor.irq, chip->vendor.iobase +
  732. TPM_INT_VECTOR(chip->vendor.locality));
  733. intmask =
  734. ioread32(chip->vendor.iobase +
  735. TPM_INT_ENABLE(chip->vendor.locality));
  736. intmask |= TPM_INTF_CMD_READY_INT
  737. | TPM_INTF_LOCALITY_CHANGE_INT | TPM_INTF_DATA_AVAIL_INT
  738. | TPM_INTF_STS_VALID_INT | TPM_GLOBAL_INT_ENABLE;
  739. iowrite32(intmask,
  740. chip->vendor.iobase + TPM_INT_ENABLE(chip->vendor.locality));
  741. }
  742. static int tpm_tis_resume(struct device *dev)
  743. {
  744. struct tpm_chip *chip = dev_get_drvdata(dev);
  745. int ret;
  746. if (chip->vendor.irq)
  747. tpm_tis_reenable_interrupts(chip);
  748. ret = tpm_pm_resume(dev);
  749. if (ret)
  750. return ret;
  751. /* TPM 1.2 requires self-test on resume. This function actually returns
  752. * an error code but for unknown reason it isn't handled.
  753. */
  754. if (!(chip->flags & TPM_CHIP_FLAG_TPM2))
  755. tpm_do_selftest(chip);
  756. return 0;
  757. }
  758. #endif
  759. static SIMPLE_DEV_PM_OPS(tpm_tis_pm, tpm_pm_suspend, tpm_tis_resume);
  760. #ifdef CONFIG_PNP
  761. static int tpm_tis_pnp_init(struct pnp_dev *pnp_dev,
  762. const struct pnp_device_id *pnp_id)
  763. {
  764. resource_size_t start, len;
  765. unsigned int irq = 0;
  766. acpi_handle acpi_dev_handle = NULL;
  767. start = pnp_mem_start(pnp_dev, 0);
  768. len = pnp_mem_len(pnp_dev, 0);
  769. if (pnp_irq_valid(pnp_dev, 0))
  770. irq = pnp_irq(pnp_dev, 0);
  771. else
  772. interrupts = false;
  773. if (is_itpm(pnp_dev))
  774. itpm = true;
  775. #ifdef CONFIG_ACPI
  776. if (pnp_acpi_device(pnp_dev))
  777. acpi_dev_handle = pnp_acpi_device(pnp_dev)->handle;
  778. #endif
  779. return tpm_tis_init(&pnp_dev->dev, acpi_dev_handle, start, len, irq);
  780. }
  781. static struct pnp_device_id tpm_pnp_tbl[] = {
  782. {"PNP0C31", 0}, /* TPM */
  783. {"ATM1200", 0}, /* Atmel */
  784. {"IFX0102", 0}, /* Infineon */
  785. {"BCM0101", 0}, /* Broadcom */
  786. {"BCM0102", 0}, /* Broadcom */
  787. {"NSC1200", 0}, /* National */
  788. {"ICO0102", 0}, /* Intel */
  789. /* Add new here */
  790. {"", 0}, /* User Specified */
  791. {"", 0} /* Terminator */
  792. };
  793. MODULE_DEVICE_TABLE(pnp, tpm_pnp_tbl);
  794. static void tpm_tis_pnp_remove(struct pnp_dev *dev)
  795. {
  796. struct tpm_chip *chip = pnp_get_drvdata(dev);
  797. tpm_chip_unregister(chip);
  798. tpm_tis_remove(chip);
  799. }
  800. static struct pnp_driver tis_pnp_driver = {
  801. .name = "tpm_tis",
  802. .id_table = tpm_pnp_tbl,
  803. .probe = tpm_tis_pnp_init,
  804. .remove = tpm_tis_pnp_remove,
  805. .driver = {
  806. .pm = &tpm_tis_pm,
  807. },
  808. };
  809. #define TIS_HID_USR_IDX sizeof(tpm_pnp_tbl)/sizeof(struct pnp_device_id) -2
  810. module_param_string(hid, tpm_pnp_tbl[TIS_HID_USR_IDX].id,
  811. sizeof(tpm_pnp_tbl[TIS_HID_USR_IDX].id), 0444);
  812. MODULE_PARM_DESC(hid, "Set additional specific HID for this driver to probe");
  813. #endif
  814. static struct platform_driver tis_drv = {
  815. .driver = {
  816. .name = "tpm_tis",
  817. .pm = &tpm_tis_pm,
  818. },
  819. };
  820. static struct platform_device *pdev;
  821. static bool force;
  822. module_param(force, bool, 0444);
  823. MODULE_PARM_DESC(force, "Force device probe rather than using ACPI entry");
  824. static int __init init_tis(void)
  825. {
  826. int rc;
  827. #ifdef CONFIG_PNP
  828. if (!force)
  829. return pnp_register_driver(&tis_pnp_driver);
  830. #endif
  831. rc = platform_driver_register(&tis_drv);
  832. if (rc < 0)
  833. return rc;
  834. pdev = platform_device_register_simple("tpm_tis", -1, NULL, 0);
  835. if (IS_ERR(pdev)) {
  836. rc = PTR_ERR(pdev);
  837. goto err_dev;
  838. }
  839. rc = tpm_tis_init(&pdev->dev, NULL, TIS_MEM_BASE, TIS_MEM_LEN, 0);
  840. if (rc)
  841. goto err_init;
  842. return 0;
  843. err_init:
  844. platform_device_unregister(pdev);
  845. err_dev:
  846. platform_driver_unregister(&tis_drv);
  847. return rc;
  848. }
  849. static void __exit cleanup_tis(void)
  850. {
  851. struct tpm_chip *chip;
  852. #ifdef CONFIG_PNP
  853. if (!force) {
  854. pnp_unregister_driver(&tis_pnp_driver);
  855. return;
  856. }
  857. #endif
  858. chip = dev_get_drvdata(&pdev->dev);
  859. tpm_chip_unregister(chip);
  860. tpm_tis_remove(chip);
  861. platform_device_unregister(pdev);
  862. platform_driver_unregister(&tis_drv);
  863. }
  864. module_init(init_tis);
  865. module_exit(cleanup_tis);
  866. MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
  867. MODULE_DESCRIPTION("TPM Driver");
  868. MODULE_VERSION("2.0");
  869. MODULE_LICENSE("GPL");