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CHIP-linux-l...
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arch
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s390
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kernel
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reipl.S

reipl.S 4.8 KB
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  1. /*
    2. 

  2.  *    Copyright IBM Corp 2000, 2011
    3. 

  3.  *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
    4. 

  4.  *		 Denis Joseph Barrow,
    5. 

  5.  */
    6. 

  6. 

  7. #include <linux/linkage.h>
    8. 

  8. #include <asm/asm-offsets.h>
    9. 

  9. #include <asm/sigp.h>
    10. 

  10. 

  11. #
    12. 

  12. # store_status
    13. 

  13. #
    14. 

  14. # Prerequisites to run this function:
    15. 

  15. # - Prefix register is set to zero
    16. 

  16. # - Original prefix register is stored in "dump_prefix_page"
    17. 

  17. # - Lowcore protection is off
    18. 

  18. #
    19. 

  19. ENTRY(store_status)
    20. 

  20. 	/* Save register one and load save area base */
    21. 

  21. 	stg	%r1,__LC_SAVE_AREA_RESTART
    22. 

  22. 	lghi	%r1,SAVE_AREA_BASE
    23. 

  23. 	/* General purpose registers */
    24. 

  24. 	stmg	%r0,%r15,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    25. 

  25. 	lg	%r2,__LC_SAVE_AREA_RESTART
    26. 

  26. 	stg	%r2,__LC_GPREGS_SAVE_AREA-SAVE_AREA_BASE+8(%r1)
    27. 

  27. 	/* Control registers */
    28. 

  28. 	stctg	%c0,%c15,__LC_CREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    29. 

  29. 	/* Access registers */
    30. 

  30. 	stam	%a0,%a15,__LC_AREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    31. 

  31. 	/* Floating point registers */
    32. 

  32. 	std	%f0, 0x00 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    33. 

  33. 	std	%f1, 0x08 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    34. 

  34. 	std	%f2, 0x10 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    35. 

  35. 	std	%f3, 0x18 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    36. 

  36. 	std	%f4, 0x20 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    37. 

  37. 	std	%f5, 0x28 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    38. 

  38. 	std	%f6, 0x30 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    39. 

  39. 	std	%f7, 0x38 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    40. 

  40. 	std	%f8, 0x40 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    41. 

  41. 	std	%f9, 0x48 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    42. 

  42. 	std	%f10,0x50 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    43. 

  43. 	std	%f11,0x58 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    44. 

  44. 	std	%f12,0x60 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    45. 

  45. 	std	%f13,0x68 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    46. 

  46. 	std	%f14,0x70 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    47. 

  47. 	std	%f15,0x78 + __LC_FPREGS_SAVE_AREA-SAVE_AREA_BASE(%r1)
    48. 

  48. 	/* Floating point control register */
    49. 

  49. 	stfpc	__LC_FP_CREG_SAVE_AREA-SAVE_AREA_BASE(%r1)
    50. 

  50. 	/* CPU timer */
    51. 

  51. 	stpt	__LC_CPU_TIMER_SAVE_AREA-SAVE_AREA_BASE(%r1)
    52. 

  52. 	/* Saved prefix register */
    53. 

  53. 	larl	%r2,dump_prefix_page
    54. 

  54. 	mvc	__LC_PREFIX_SAVE_AREA-SAVE_AREA_BASE(4,%r1),0(%r2)
    55. 

  55. 	/* Clock comparator - seven bytes */
    56. 

  56. 	larl	%r2,.Lclkcmp
    57. 

  57. 	stckc	0(%r2)
    58. 

  58. 	mvc	__LC_CLOCK_COMP_SAVE_AREA-SAVE_AREA_BASE + 1(7,%r1),1(%r2)
    59. 

  59. 	/* Program status word */
    60. 

  60. 	epsw	%r2,%r3
    61. 

  61. 	st	%r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 0(%r1)
    62. 

  62. 	st	%r3,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 4(%r1)
    63. 

  63. 	larl	%r2,store_status
    64. 

  64. 	stg	%r2,__LC_PSW_SAVE_AREA-SAVE_AREA_BASE + 8(%r1)
    65. 

  65. 	br	%r14
    66. 

  66. 

  67. 	.section .bss
    68. 

  68. 	.align	8
    69. 

  69. .Lclkcmp:	.quad	0x0000000000000000
    70. 

  70. 	.previous
    71. 

  71. 

  72. #
    73. 

  73. # do_reipl_asm
    74. 

  74. # Parameter: r2 = schid of reipl device
    75. 

  75. #
    76. 

  76. 

  77. ENTRY(do_reipl_asm)
    78. 

  78. 		basr	%r13,0
    79. 

  79. .Lpg0:		lpswe	.Lnewpsw-.Lpg0(%r13)
    80. 

  80. .Lpg1:		brasl	%r14,store_status
    81. 

  81. 

  82. 		lctlg	%c6,%c6,.Lall-.Lpg0(%r13)
    83. 

  83. 		lgr	%r1,%r2
    84. 

  84. 		mvc	__LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
    85. 

  85. 		stsch	.Lschib-.Lpg0(%r13)
    86. 

  86. 		oi	.Lschib+5-.Lpg0(%r13),0x84
    87. 

  87. .Lecs:		xi	.Lschib+27-.Lpg0(%r13),0x01
    88. 

  88. 		msch	.Lschib-.Lpg0(%r13)
    89. 

  89. 		lghi	%r0,5
    90. 

  90. .Lssch:		ssch	.Liplorb-.Lpg0(%r13)
    91. 

  91. 		jz	.L001
    92. 

  92. 		brct	%r0,.Lssch
    93. 

  93. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    94. 

  94. .L001:		mvc	__LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
    95. 

  95. .Ltpi:		lpswe	.Lwaitpsw-.Lpg0(%r13)
    96. 

  96. .Lcont:		c	%r1,__LC_SUBCHANNEL_ID
    97. 

  97. 		jnz	.Ltpi
    98. 

  98. 		clc	__LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
    99. 

  99. 		jnz	.Ltpi
    100. 

  100. 		tsch	.Liplirb-.Lpg0(%r13)
    101. 

  101. 		tm	.Liplirb+9-.Lpg0(%r13),0xbf
    102. 

  102. 		jz	.L002
    103. 

  103. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    104. 

  104. .L002:		tm	.Liplirb+8-.Lpg0(%r13),0xf3
    105. 

  105. 		jz	.L003
    106. 

  106. 		bas	%r14,.Ldisab-.Lpg0(%r13)
    107. 

  107. .L003:		st	%r1,__LC_SUBCHANNEL_ID
    108. 

  108. 		lhi	%r1,0		 # mode 0 = esa
    109. 

  109. 		slr	%r0,%r0		 # set cpuid to zero
    110. 

  110. 		sigp	%r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode
    111. 

  111. 		lpsw	0
    112. 

  112. .Ldisab:	sll	%r14,1
    113. 

  113. 		srl	%r14,1		 # need to kill hi bit to avoid specification exceptions.
    114. 

  114. 		st	%r14,.Ldispsw+12-.Lpg0(%r13)
    115. 

  115. 		lpswe	.Ldispsw-.Lpg0(%r13)
    116. 

  116. 		.align	8
    117. 

  117. .Lall:		.quad	0x00000000ff000000
    118. 

  118. 		.align	16
    119. 

  119. /*
    120. 

  120.  * These addresses have to be 31 bit otherwise
    121. 

  121.  * the sigp will throw a specifcation exception
    122. 

  122.  * when switching to ESA mode as bit 31 be set
    123. 

  123.  * in the ESA psw.
    124. 

  124.  * Bit 31 of the addresses has to be 0 for the
    125. 

  125.  * 31bit lpswe instruction a fact they appear to have
    126. 

  126.  * omitted from the pop.
    127. 

  127.  */
    128. 

  128. .Lnewpsw:	.quad	0x0000000080000000
    129. 

  129. 		.quad	.Lpg1
    130. 

  130. .Lpcnew:	.quad	0x0000000080000000
    131. 

  131. 		.quad	.Lecs
    132. 

  132. .Lionew:	.quad	0x0000000080000000
    133. 

  133. 		.quad	.Lcont
    134. 

  134. .Lwaitpsw:	.quad	0x0202000080000000
    135. 

  135. 		.quad	.Ltpi
    136. 

  136. .Ldispsw:	.quad	0x0002000080000000
    137. 

  137. 		.quad	0x0000000000000000
    138. 

  138. .Liplccws:	.long	0x02000000,0x60000018
    139. 

  139. 		.long	0x08000008,0x20000001
    140. 

  140. .Liplorb:	.long	0x0049504c,0x0040ff80
    141. 

  141. 		.long	0x00000000+.Liplccws
    142. 

  142. .Lschib:	.long	0x00000000,0x00000000
    143. 

  143. 		.long	0x00000000,0x00000000
    144. 

  144. 		.long	0x00000000,0x00000000
    145. 

  145. 		.long	0x00000000,0x00000000
    146. 

  146. 		.long	0x00000000,0x00000000
    147. 

  147. 		.long	0x00000000,0x00000000
    148. 

  148. .Liplirb:	.long	0x00000000,0x00000000
    149. 

  149. 		.long	0x00000000,0x00000000
    150. 

  150. 		.long	0x00000000,0x00000000
    151. 

  151. 		.long	0x00000000,0x00000000
    152. 

  152. 		.long	0x00000000,0x00000000
    153. 

  153. 		.long	0x00000000,0x00000000
    154. 

  154. 		.long	0x00000000,0x00000000
    155. 

  155. 		.long	0x00000000,0x00000000
    156. 

  156.