wakeup.c 6.0 KB

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  1. /*
  2. * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
  3. * reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the NetLogic
  9. * license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or without
  12. * modification, are permitted provided that the following conditions
  13. * are met:
  14. *
  15. * 1. Redistributions of source code must retain the above copyright
  16. * notice, this list of conditions and the following disclaimer.
  17. * 2. Redistributions in binary form must reproduce the above copyright
  18. * notice, this list of conditions and the following disclaimer in
  19. * the documentation and/or other materials provided with the
  20. * distribution.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25. * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31. * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32. * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/threads.h>
  36. #include <asm/asm.h>
  37. #include <asm/asm-offsets.h>
  38. #include <asm/mipsregs.h>
  39. #include <asm/addrspace.h>
  40. #include <asm/string.h>
  41. #include <asm/netlogic/haldefs.h>
  42. #include <asm/netlogic/common.h>
  43. #include <asm/netlogic/mips-extns.h>
  44. #include <asm/netlogic/xlp-hal/iomap.h>
  45. #include <asm/netlogic/xlp-hal/xlp.h>
  46. #include <asm/netlogic/xlp-hal/pic.h>
  47. #include <asm/netlogic/xlp-hal/sys.h>
  48. static int xlp_wakeup_core(uint64_t sysbase, int node, int core)
  49. {
  50. uint32_t coremask, value;
  51. int count, resetreg;
  52. coremask = (1 << core);
  53. /* Enable CPU clock in case of 8xx/3xx */
  54. if (!cpu_is_xlpii()) {
  55. value = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
  56. value &= ~coremask;
  57. nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, value);
  58. }
  59. /* On 9XX, mark coherent first */
  60. if (cpu_is_xlp9xx()) {
  61. value = nlm_read_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE);
  62. value &= ~coremask;
  63. nlm_write_sys_reg(sysbase, SYS_9XX_CPU_NONCOHERENT_MODE, value);
  64. }
  65. /* Remove CPU Reset */
  66. resetreg = cpu_is_xlp9xx() ? SYS_9XX_CPU_RESET : SYS_CPU_RESET;
  67. value = nlm_read_sys_reg(sysbase, resetreg);
  68. value &= ~coremask;
  69. nlm_write_sys_reg(sysbase, resetreg, value);
  70. /* We are done on 9XX */
  71. if (cpu_is_xlp9xx())
  72. return 1;
  73. /* Poll for CPU to mark itself coherent on other type of XLP */
  74. count = 100000;
  75. do {
  76. value = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
  77. } while ((value & coremask) != 0 && --count > 0);
  78. return count != 0;
  79. }
  80. static int wait_for_cpus(int cpu, int bootcpu)
  81. {
  82. volatile uint32_t *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
  83. int i, count, notready;
  84. count = 0x800000;
  85. do {
  86. notready = nlm_threads_per_core;
  87. for (i = 0; i < nlm_threads_per_core; i++)
  88. if (cpu_ready[cpu + i] || (cpu + i) == bootcpu)
  89. --notready;
  90. } while (notready != 0 && --count > 0);
  91. return count != 0;
  92. }
  93. static void xlp_enable_secondary_cores(const cpumask_t *wakeup_mask)
  94. {
  95. struct nlm_soc_info *nodep;
  96. uint64_t syspcibase, fusebase;
  97. uint32_t syscoremask, mask, fusemask;
  98. int core, n, cpu, ncores;
  99. for (n = 0; n < NLM_NR_NODES; n++) {
  100. if (n != 0) {
  101. /* check if node exists and is online */
  102. if (cpu_is_xlp9xx()) {
  103. int b = xlp9xx_get_socbus(n);
  104. pr_info("Node %d SoC PCI bus %d.\n", n, b);
  105. if (b == 0)
  106. break;
  107. } else {
  108. syspcibase = nlm_get_sys_pcibase(n);
  109. if (nlm_read_reg(syspcibase, 0) == 0xffffffff)
  110. break;
  111. }
  112. nlm_node_init(n);
  113. }
  114. /* read cores in reset from SYS */
  115. nodep = nlm_get_node(n);
  116. if (cpu_is_xlp9xx()) {
  117. fusebase = nlm_get_fuse_regbase(n);
  118. fusemask = nlm_read_reg(fusebase, FUSE_9XX_DEVCFG6);
  119. switch (read_c0_prid() & PRID_IMP_MASK) {
  120. case PRID_IMP_NETLOGIC_XLP5XX:
  121. mask = 0xff;
  122. break;
  123. case PRID_IMP_NETLOGIC_XLP9XX:
  124. default:
  125. mask = 0xfffff;
  126. break;
  127. }
  128. } else {
  129. fusemask = nlm_read_sys_reg(nodep->sysbase,
  130. SYS_EFUSE_DEVICE_CFG_STATUS0);
  131. switch (read_c0_prid() & PRID_IMP_MASK) {
  132. case PRID_IMP_NETLOGIC_XLP3XX:
  133. mask = 0xf;
  134. break;
  135. case PRID_IMP_NETLOGIC_XLP2XX:
  136. mask = 0x3;
  137. break;
  138. case PRID_IMP_NETLOGIC_XLP8XX:
  139. default:
  140. mask = 0xff;
  141. break;
  142. }
  143. }
  144. /*
  145. * Fused out cores are set in the fusemask, and the remaining
  146. * cores are renumbered to range 0 .. nactive-1
  147. */
  148. syscoremask = (1 << hweight32(~fusemask & mask)) - 1;
  149. pr_info("Node %d - SYS/FUSE coremask %x\n", n, syscoremask);
  150. ncores = nlm_cores_per_node();
  151. for (core = 0; core < ncores; core++) {
  152. /* we will be on node 0 core 0 */
  153. if (n == 0 && core == 0)
  154. continue;
  155. /* see if the core exists */
  156. if ((syscoremask & (1 << core)) == 0)
  157. continue;
  158. /* see if at least the first hw thread is enabled */
  159. cpu = (n * ncores + core) * NLM_THREADS_PER_CORE;
  160. if (!cpumask_test_cpu(cpu, wakeup_mask))
  161. continue;
  162. /* wake up the core */
  163. if (!xlp_wakeup_core(nodep->sysbase, n, core))
  164. continue;
  165. /* core is up */
  166. nodep->coremask |= 1u << core;
  167. /* spin until the hw threads sets their ready */
  168. if (!wait_for_cpus(cpu, 0))
  169. pr_err("Node %d : timeout core %d\n", n, core);
  170. }
  171. }
  172. }
  173. void xlp_wakeup_secondary_cpus()
  174. {
  175. /*
  176. * In case of u-boot, the secondaries are in reset
  177. * first wakeup core 0 threads
  178. */
  179. xlp_boot_core0_siblings();
  180. if (!wait_for_cpus(0, 0))
  181. pr_err("Node 0 : timeout core 0\n");
  182. /* now get other cores out of reset */
  183. xlp_enable_secondary_cores(&nlm_cpumask);
  184. }