c-r4k.c 45 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  7. * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
  8. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  9. */
  10. #include <linux/cpu_pm.h>
  11. #include <linux/hardirq.h>
  12. #include <linux/init.h>
  13. #include <linux/highmem.h>
  14. #include <linux/kernel.h>
  15. #include <linux/linkage.h>
  16. #include <linux/preempt.h>
  17. #include <linux/sched.h>
  18. #include <linux/smp.h>
  19. #include <linux/mm.h>
  20. #include <linux/module.h>
  21. #include <linux/bitops.h>
  22. #include <asm/bcache.h>
  23. #include <asm/bootinfo.h>
  24. #include <asm/cache.h>
  25. #include <asm/cacheops.h>
  26. #include <asm/cpu.h>
  27. #include <asm/cpu-features.h>
  28. #include <asm/cpu-type.h>
  29. #include <asm/io.h>
  30. #include <asm/page.h>
  31. #include <asm/pgtable.h>
  32. #include <asm/r4kcache.h>
  33. #include <asm/sections.h>
  34. #include <asm/mmu_context.h>
  35. #include <asm/war.h>
  36. #include <asm/cacheflush.h> /* for run_uncached() */
  37. #include <asm/traps.h>
  38. #include <asm/dma-coherence.h>
  39. /*
  40. * Special Variant of smp_call_function for use by cache functions:
  41. *
  42. * o No return value
  43. * o collapses to normal function call on UP kernels
  44. * o collapses to normal function call on systems with a single shared
  45. * primary cache.
  46. * o doesn't disable interrupts on the local CPU
  47. */
  48. static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
  49. {
  50. preempt_disable();
  51. #ifndef CONFIG_MIPS_MT_SMP
  52. smp_call_function(func, info, 1);
  53. #endif
  54. func(info);
  55. preempt_enable();
  56. }
  57. #if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
  58. #define cpu_has_safe_index_cacheops 0
  59. #else
  60. #define cpu_has_safe_index_cacheops 1
  61. #endif
  62. /*
  63. * Must die.
  64. */
  65. static unsigned long icache_size __read_mostly;
  66. static unsigned long dcache_size __read_mostly;
  67. static unsigned long scache_size __read_mostly;
  68. /*
  69. * Dummy cache handling routines for machines without boardcaches
  70. */
  71. static void cache_noop(void) {}
  72. static struct bcache_ops no_sc_ops = {
  73. .bc_enable = (void *)cache_noop,
  74. .bc_disable = (void *)cache_noop,
  75. .bc_wback_inv = (void *)cache_noop,
  76. .bc_inv = (void *)cache_noop
  77. };
  78. struct bcache_ops *bcops = &no_sc_ops;
  79. #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  80. #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  81. #define R4600_HIT_CACHEOP_WAR_IMPL \
  82. do { \
  83. if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
  84. *(volatile unsigned long *)CKSEG1; \
  85. if (R4600_V1_HIT_CACHEOP_WAR) \
  86. __asm__ __volatile__("nop;nop;nop;nop"); \
  87. } while (0)
  88. static void (*r4k_blast_dcache_page)(unsigned long addr);
  89. static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
  90. {
  91. R4600_HIT_CACHEOP_WAR_IMPL;
  92. blast_dcache32_page(addr);
  93. }
  94. static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
  95. {
  96. blast_dcache64_page(addr);
  97. }
  98. static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
  99. {
  100. blast_dcache128_page(addr);
  101. }
  102. static void r4k_blast_dcache_page_setup(void)
  103. {
  104. unsigned long dc_lsize = cpu_dcache_line_size();
  105. switch (dc_lsize) {
  106. case 0:
  107. r4k_blast_dcache_page = (void *)cache_noop;
  108. break;
  109. case 16:
  110. r4k_blast_dcache_page = blast_dcache16_page;
  111. break;
  112. case 32:
  113. r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
  114. break;
  115. case 64:
  116. r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
  117. break;
  118. case 128:
  119. r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
  120. break;
  121. default:
  122. break;
  123. }
  124. }
  125. #ifndef CONFIG_EVA
  126. #define r4k_blast_dcache_user_page r4k_blast_dcache_page
  127. #else
  128. static void (*r4k_blast_dcache_user_page)(unsigned long addr);
  129. static void r4k_blast_dcache_user_page_setup(void)
  130. {
  131. unsigned long dc_lsize = cpu_dcache_line_size();
  132. if (dc_lsize == 0)
  133. r4k_blast_dcache_user_page = (void *)cache_noop;
  134. else if (dc_lsize == 16)
  135. r4k_blast_dcache_user_page = blast_dcache16_user_page;
  136. else if (dc_lsize == 32)
  137. r4k_blast_dcache_user_page = blast_dcache32_user_page;
  138. else if (dc_lsize == 64)
  139. r4k_blast_dcache_user_page = blast_dcache64_user_page;
  140. }
  141. #endif
  142. static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
  143. static void r4k_blast_dcache_page_indexed_setup(void)
  144. {
  145. unsigned long dc_lsize = cpu_dcache_line_size();
  146. if (dc_lsize == 0)
  147. r4k_blast_dcache_page_indexed = (void *)cache_noop;
  148. else if (dc_lsize == 16)
  149. r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
  150. else if (dc_lsize == 32)
  151. r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
  152. else if (dc_lsize == 64)
  153. r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
  154. else if (dc_lsize == 128)
  155. r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
  156. }
  157. void (* r4k_blast_dcache)(void);
  158. EXPORT_SYMBOL(r4k_blast_dcache);
  159. static void r4k_blast_dcache_setup(void)
  160. {
  161. unsigned long dc_lsize = cpu_dcache_line_size();
  162. if (dc_lsize == 0)
  163. r4k_blast_dcache = (void *)cache_noop;
  164. else if (dc_lsize == 16)
  165. r4k_blast_dcache = blast_dcache16;
  166. else if (dc_lsize == 32)
  167. r4k_blast_dcache = blast_dcache32;
  168. else if (dc_lsize == 64)
  169. r4k_blast_dcache = blast_dcache64;
  170. else if (dc_lsize == 128)
  171. r4k_blast_dcache = blast_dcache128;
  172. }
  173. /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
  174. #define JUMP_TO_ALIGN(order) \
  175. __asm__ __volatile__( \
  176. "b\t1f\n\t" \
  177. ".align\t" #order "\n\t" \
  178. "1:\n\t" \
  179. )
  180. #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
  181. #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
  182. static inline void blast_r4600_v1_icache32(void)
  183. {
  184. unsigned long flags;
  185. local_irq_save(flags);
  186. blast_icache32();
  187. local_irq_restore(flags);
  188. }
  189. static inline void tx49_blast_icache32(void)
  190. {
  191. unsigned long start = INDEX_BASE;
  192. unsigned long end = start + current_cpu_data.icache.waysize;
  193. unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
  194. unsigned long ws_end = current_cpu_data.icache.ways <<
  195. current_cpu_data.icache.waybit;
  196. unsigned long ws, addr;
  197. CACHE32_UNROLL32_ALIGN2;
  198. /* I'm in even chunk. blast odd chunks */
  199. for (ws = 0; ws < ws_end; ws += ws_inc)
  200. for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
  201. cache32_unroll32(addr|ws, Index_Invalidate_I);
  202. CACHE32_UNROLL32_ALIGN;
  203. /* I'm in odd chunk. blast even chunks */
  204. for (ws = 0; ws < ws_end; ws += ws_inc)
  205. for (addr = start; addr < end; addr += 0x400 * 2)
  206. cache32_unroll32(addr|ws, Index_Invalidate_I);
  207. }
  208. static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
  209. {
  210. unsigned long flags;
  211. local_irq_save(flags);
  212. blast_icache32_page_indexed(page);
  213. local_irq_restore(flags);
  214. }
  215. static inline void tx49_blast_icache32_page_indexed(unsigned long page)
  216. {
  217. unsigned long indexmask = current_cpu_data.icache.waysize - 1;
  218. unsigned long start = INDEX_BASE + (page & indexmask);
  219. unsigned long end = start + PAGE_SIZE;
  220. unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
  221. unsigned long ws_end = current_cpu_data.icache.ways <<
  222. current_cpu_data.icache.waybit;
  223. unsigned long ws, addr;
  224. CACHE32_UNROLL32_ALIGN2;
  225. /* I'm in even chunk. blast odd chunks */
  226. for (ws = 0; ws < ws_end; ws += ws_inc)
  227. for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
  228. cache32_unroll32(addr|ws, Index_Invalidate_I);
  229. CACHE32_UNROLL32_ALIGN;
  230. /* I'm in odd chunk. blast even chunks */
  231. for (ws = 0; ws < ws_end; ws += ws_inc)
  232. for (addr = start; addr < end; addr += 0x400 * 2)
  233. cache32_unroll32(addr|ws, Index_Invalidate_I);
  234. }
  235. static void (* r4k_blast_icache_page)(unsigned long addr);
  236. static void r4k_blast_icache_page_setup(void)
  237. {
  238. unsigned long ic_lsize = cpu_icache_line_size();
  239. if (ic_lsize == 0)
  240. r4k_blast_icache_page = (void *)cache_noop;
  241. else if (ic_lsize == 16)
  242. r4k_blast_icache_page = blast_icache16_page;
  243. else if (ic_lsize == 32 && current_cpu_type() == CPU_LOONGSON2)
  244. r4k_blast_icache_page = loongson2_blast_icache32_page;
  245. else if (ic_lsize == 32)
  246. r4k_blast_icache_page = blast_icache32_page;
  247. else if (ic_lsize == 64)
  248. r4k_blast_icache_page = blast_icache64_page;
  249. else if (ic_lsize == 128)
  250. r4k_blast_icache_page = blast_icache128_page;
  251. }
  252. #ifndef CONFIG_EVA
  253. #define r4k_blast_icache_user_page r4k_blast_icache_page
  254. #else
  255. static void (*r4k_blast_icache_user_page)(unsigned long addr);
  256. static void r4k_blast_icache_user_page_setup(void)
  257. {
  258. unsigned long ic_lsize = cpu_icache_line_size();
  259. if (ic_lsize == 0)
  260. r4k_blast_icache_user_page = (void *)cache_noop;
  261. else if (ic_lsize == 16)
  262. r4k_blast_icache_user_page = blast_icache16_user_page;
  263. else if (ic_lsize == 32)
  264. r4k_blast_icache_user_page = blast_icache32_user_page;
  265. else if (ic_lsize == 64)
  266. r4k_blast_icache_user_page = blast_icache64_user_page;
  267. }
  268. #endif
  269. static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
  270. static void r4k_blast_icache_page_indexed_setup(void)
  271. {
  272. unsigned long ic_lsize = cpu_icache_line_size();
  273. if (ic_lsize == 0)
  274. r4k_blast_icache_page_indexed = (void *)cache_noop;
  275. else if (ic_lsize == 16)
  276. r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
  277. else if (ic_lsize == 32) {
  278. if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
  279. r4k_blast_icache_page_indexed =
  280. blast_icache32_r4600_v1_page_indexed;
  281. else if (TX49XX_ICACHE_INDEX_INV_WAR)
  282. r4k_blast_icache_page_indexed =
  283. tx49_blast_icache32_page_indexed;
  284. else if (current_cpu_type() == CPU_LOONGSON2)
  285. r4k_blast_icache_page_indexed =
  286. loongson2_blast_icache32_page_indexed;
  287. else
  288. r4k_blast_icache_page_indexed =
  289. blast_icache32_page_indexed;
  290. } else if (ic_lsize == 64)
  291. r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
  292. }
  293. void (* r4k_blast_icache)(void);
  294. EXPORT_SYMBOL(r4k_blast_icache);
  295. static void r4k_blast_icache_setup(void)
  296. {
  297. unsigned long ic_lsize = cpu_icache_line_size();
  298. if (ic_lsize == 0)
  299. r4k_blast_icache = (void *)cache_noop;
  300. else if (ic_lsize == 16)
  301. r4k_blast_icache = blast_icache16;
  302. else if (ic_lsize == 32) {
  303. if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
  304. r4k_blast_icache = blast_r4600_v1_icache32;
  305. else if (TX49XX_ICACHE_INDEX_INV_WAR)
  306. r4k_blast_icache = tx49_blast_icache32;
  307. else if (current_cpu_type() == CPU_LOONGSON2)
  308. r4k_blast_icache = loongson2_blast_icache32;
  309. else
  310. r4k_blast_icache = blast_icache32;
  311. } else if (ic_lsize == 64)
  312. r4k_blast_icache = blast_icache64;
  313. else if (ic_lsize == 128)
  314. r4k_blast_icache = blast_icache128;
  315. }
  316. static void (* r4k_blast_scache_page)(unsigned long addr);
  317. static void r4k_blast_scache_page_setup(void)
  318. {
  319. unsigned long sc_lsize = cpu_scache_line_size();
  320. if (scache_size == 0)
  321. r4k_blast_scache_page = (void *)cache_noop;
  322. else if (sc_lsize == 16)
  323. r4k_blast_scache_page = blast_scache16_page;
  324. else if (sc_lsize == 32)
  325. r4k_blast_scache_page = blast_scache32_page;
  326. else if (sc_lsize == 64)
  327. r4k_blast_scache_page = blast_scache64_page;
  328. else if (sc_lsize == 128)
  329. r4k_blast_scache_page = blast_scache128_page;
  330. }
  331. static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
  332. static void r4k_blast_scache_page_indexed_setup(void)
  333. {
  334. unsigned long sc_lsize = cpu_scache_line_size();
  335. if (scache_size == 0)
  336. r4k_blast_scache_page_indexed = (void *)cache_noop;
  337. else if (sc_lsize == 16)
  338. r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
  339. else if (sc_lsize == 32)
  340. r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
  341. else if (sc_lsize == 64)
  342. r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
  343. else if (sc_lsize == 128)
  344. r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
  345. }
  346. static void (* r4k_blast_scache)(void);
  347. static void r4k_blast_scache_setup(void)
  348. {
  349. unsigned long sc_lsize = cpu_scache_line_size();
  350. if (scache_size == 0)
  351. r4k_blast_scache = (void *)cache_noop;
  352. else if (sc_lsize == 16)
  353. r4k_blast_scache = blast_scache16;
  354. else if (sc_lsize == 32)
  355. r4k_blast_scache = blast_scache32;
  356. else if (sc_lsize == 64)
  357. r4k_blast_scache = blast_scache64;
  358. else if (sc_lsize == 128)
  359. r4k_blast_scache = blast_scache128;
  360. }
  361. static inline void local_r4k___flush_cache_all(void * args)
  362. {
  363. switch (current_cpu_type()) {
  364. case CPU_LOONGSON2:
  365. case CPU_LOONGSON3:
  366. case CPU_R4000SC:
  367. case CPU_R4000MC:
  368. case CPU_R4400SC:
  369. case CPU_R4400MC:
  370. case CPU_R10000:
  371. case CPU_R12000:
  372. case CPU_R14000:
  373. case CPU_R16000:
  374. /*
  375. * These caches are inclusive caches, that is, if something
  376. * is not cached in the S-cache, we know it also won't be
  377. * in one of the primary caches.
  378. */
  379. r4k_blast_scache();
  380. break;
  381. default:
  382. r4k_blast_dcache();
  383. r4k_blast_icache();
  384. break;
  385. }
  386. }
  387. static void r4k___flush_cache_all(void)
  388. {
  389. r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
  390. }
  391. static inline int has_valid_asid(const struct mm_struct *mm)
  392. {
  393. #ifdef CONFIG_MIPS_MT_SMP
  394. int i;
  395. for_each_online_cpu(i)
  396. if (cpu_context(i, mm))
  397. return 1;
  398. return 0;
  399. #else
  400. return cpu_context(smp_processor_id(), mm);
  401. #endif
  402. }
  403. static void r4k__flush_cache_vmap(void)
  404. {
  405. r4k_blast_dcache();
  406. }
  407. static void r4k__flush_cache_vunmap(void)
  408. {
  409. r4k_blast_dcache();
  410. }
  411. static inline void local_r4k_flush_cache_range(void * args)
  412. {
  413. struct vm_area_struct *vma = args;
  414. int exec = vma->vm_flags & VM_EXEC;
  415. if (!(has_valid_asid(vma->vm_mm)))
  416. return;
  417. r4k_blast_dcache();
  418. if (exec)
  419. r4k_blast_icache();
  420. }
  421. static void r4k_flush_cache_range(struct vm_area_struct *vma,
  422. unsigned long start, unsigned long end)
  423. {
  424. int exec = vma->vm_flags & VM_EXEC;
  425. if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
  426. r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
  427. }
  428. static inline void local_r4k_flush_cache_mm(void * args)
  429. {
  430. struct mm_struct *mm = args;
  431. if (!has_valid_asid(mm))
  432. return;
  433. /*
  434. * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
  435. * only flush the primary caches but R1x000 behave sane ...
  436. * R4000SC and R4400SC indexed S-cache ops also invalidate primary
  437. * caches, so we can bail out early.
  438. */
  439. if (current_cpu_type() == CPU_R4000SC ||
  440. current_cpu_type() == CPU_R4000MC ||
  441. current_cpu_type() == CPU_R4400SC ||
  442. current_cpu_type() == CPU_R4400MC) {
  443. r4k_blast_scache();
  444. return;
  445. }
  446. r4k_blast_dcache();
  447. }
  448. static void r4k_flush_cache_mm(struct mm_struct *mm)
  449. {
  450. if (!cpu_has_dc_aliases)
  451. return;
  452. r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
  453. }
  454. struct flush_cache_page_args {
  455. struct vm_area_struct *vma;
  456. unsigned long addr;
  457. unsigned long pfn;
  458. };
  459. static inline void local_r4k_flush_cache_page(void *args)
  460. {
  461. struct flush_cache_page_args *fcp_args = args;
  462. struct vm_area_struct *vma = fcp_args->vma;
  463. unsigned long addr = fcp_args->addr;
  464. struct page *page = pfn_to_page(fcp_args->pfn);
  465. int exec = vma->vm_flags & VM_EXEC;
  466. struct mm_struct *mm = vma->vm_mm;
  467. int map_coherent = 0;
  468. pgd_t *pgdp;
  469. pud_t *pudp;
  470. pmd_t *pmdp;
  471. pte_t *ptep;
  472. void *vaddr;
  473. /*
  474. * If ownes no valid ASID yet, cannot possibly have gotten
  475. * this page into the cache.
  476. */
  477. if (!has_valid_asid(mm))
  478. return;
  479. addr &= PAGE_MASK;
  480. pgdp = pgd_offset(mm, addr);
  481. pudp = pud_offset(pgdp, addr);
  482. pmdp = pmd_offset(pudp, addr);
  483. ptep = pte_offset(pmdp, addr);
  484. /*
  485. * If the page isn't marked valid, the page cannot possibly be
  486. * in the cache.
  487. */
  488. if (!(pte_present(*ptep)))
  489. return;
  490. if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
  491. vaddr = NULL;
  492. else {
  493. /*
  494. * Use kmap_coherent or kmap_atomic to do flushes for
  495. * another ASID than the current one.
  496. */
  497. map_coherent = (cpu_has_dc_aliases &&
  498. page_mapped(page) && !Page_dcache_dirty(page));
  499. if (map_coherent)
  500. vaddr = kmap_coherent(page, addr);
  501. else
  502. vaddr = kmap_atomic(page);
  503. addr = (unsigned long)vaddr;
  504. }
  505. if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
  506. vaddr ? r4k_blast_dcache_page(addr) :
  507. r4k_blast_dcache_user_page(addr);
  508. if (exec && !cpu_icache_snoops_remote_store)
  509. r4k_blast_scache_page(addr);
  510. }
  511. if (exec) {
  512. if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
  513. int cpu = smp_processor_id();
  514. if (cpu_context(cpu, mm) != 0)
  515. drop_mmu_context(mm, cpu);
  516. } else
  517. vaddr ? r4k_blast_icache_page(addr) :
  518. r4k_blast_icache_user_page(addr);
  519. }
  520. if (vaddr) {
  521. if (map_coherent)
  522. kunmap_coherent();
  523. else
  524. kunmap_atomic(vaddr);
  525. }
  526. }
  527. static void r4k_flush_cache_page(struct vm_area_struct *vma,
  528. unsigned long addr, unsigned long pfn)
  529. {
  530. struct flush_cache_page_args args;
  531. args.vma = vma;
  532. args.addr = addr;
  533. args.pfn = pfn;
  534. r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
  535. }
  536. static inline void local_r4k_flush_data_cache_page(void * addr)
  537. {
  538. r4k_blast_dcache_page((unsigned long) addr);
  539. }
  540. static void r4k_flush_data_cache_page(unsigned long addr)
  541. {
  542. if (in_atomic())
  543. local_r4k_flush_data_cache_page((void *)addr);
  544. else
  545. r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
  546. }
  547. struct flush_icache_range_args {
  548. unsigned long start;
  549. unsigned long end;
  550. };
  551. static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
  552. {
  553. if (!cpu_has_ic_fills_f_dc) {
  554. if (end - start >= dcache_size) {
  555. r4k_blast_dcache();
  556. } else {
  557. R4600_HIT_CACHEOP_WAR_IMPL;
  558. protected_blast_dcache_range(start, end);
  559. }
  560. }
  561. if (end - start > icache_size)
  562. r4k_blast_icache();
  563. else {
  564. switch (boot_cpu_type()) {
  565. case CPU_LOONGSON2:
  566. protected_loongson2_blast_icache_range(start, end);
  567. break;
  568. default:
  569. protected_blast_icache_range(start, end);
  570. break;
  571. }
  572. }
  573. #ifdef CONFIG_EVA
  574. /*
  575. * Due to all possible segment mappings, there might cache aliases
  576. * caused by the bootloader being in non-EVA mode, and the CPU switching
  577. * to EVA during early kernel init. It's best to flush the scache
  578. * to avoid having secondary cores fetching stale data and lead to
  579. * kernel crashes.
  580. */
  581. bc_wback_inv(start, (end - start));
  582. __sync();
  583. #endif
  584. }
  585. static inline void local_r4k_flush_icache_range_ipi(void *args)
  586. {
  587. struct flush_icache_range_args *fir_args = args;
  588. unsigned long start = fir_args->start;
  589. unsigned long end = fir_args->end;
  590. local_r4k_flush_icache_range(start, end);
  591. }
  592. static void r4k_flush_icache_range(unsigned long start, unsigned long end)
  593. {
  594. struct flush_icache_range_args args;
  595. args.start = start;
  596. args.end = end;
  597. r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
  598. instruction_hazard();
  599. }
  600. #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
  601. static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
  602. {
  603. /* Catch bad driver code */
  604. BUG_ON(size == 0);
  605. preempt_disable();
  606. if (cpu_has_inclusive_pcaches) {
  607. if (size >= scache_size)
  608. r4k_blast_scache();
  609. else
  610. blast_scache_range(addr, addr + size);
  611. preempt_enable();
  612. __sync();
  613. return;
  614. }
  615. /*
  616. * Either no secondary cache or the available caches don't have the
  617. * subset property so we have to flush the primary caches
  618. * explicitly
  619. */
  620. if (cpu_has_safe_index_cacheops && size >= dcache_size) {
  621. r4k_blast_dcache();
  622. } else {
  623. R4600_HIT_CACHEOP_WAR_IMPL;
  624. blast_dcache_range(addr, addr + size);
  625. }
  626. preempt_enable();
  627. bc_wback_inv(addr, size);
  628. __sync();
  629. }
  630. static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
  631. {
  632. /* Catch bad driver code */
  633. BUG_ON(size == 0);
  634. preempt_disable();
  635. if (cpu_has_inclusive_pcaches) {
  636. if (size >= scache_size)
  637. r4k_blast_scache();
  638. else {
  639. /*
  640. * There is no clearly documented alignment requirement
  641. * for the cache instruction on MIPS processors and
  642. * some processors, among them the RM5200 and RM7000
  643. * QED processors will throw an address error for cache
  644. * hit ops with insufficient alignment. Solved by
  645. * aligning the address to cache line size.
  646. */
  647. blast_inv_scache_range(addr, addr + size);
  648. }
  649. preempt_enable();
  650. __sync();
  651. return;
  652. }
  653. if (cpu_has_safe_index_cacheops && size >= dcache_size) {
  654. r4k_blast_dcache();
  655. } else {
  656. R4600_HIT_CACHEOP_WAR_IMPL;
  657. blast_inv_dcache_range(addr, addr + size);
  658. }
  659. preempt_enable();
  660. bc_inv(addr, size);
  661. __sync();
  662. }
  663. #endif /* CONFIG_DMA_NONCOHERENT || CONFIG_DMA_MAYBE_COHERENT */
  664. /*
  665. * While we're protected against bad userland addresses we don't care
  666. * very much about what happens in that case. Usually a segmentation
  667. * fault will dump the process later on anyway ...
  668. */
  669. static void local_r4k_flush_cache_sigtramp(void * arg)
  670. {
  671. unsigned long ic_lsize = cpu_icache_line_size();
  672. unsigned long dc_lsize = cpu_dcache_line_size();
  673. unsigned long sc_lsize = cpu_scache_line_size();
  674. unsigned long addr = (unsigned long) arg;
  675. R4600_HIT_CACHEOP_WAR_IMPL;
  676. if (dc_lsize)
  677. protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
  678. if (!cpu_icache_snoops_remote_store && scache_size)
  679. protected_writeback_scache_line(addr & ~(sc_lsize - 1));
  680. if (ic_lsize)
  681. protected_flush_icache_line(addr & ~(ic_lsize - 1));
  682. if (MIPS4K_ICACHE_REFILL_WAR) {
  683. __asm__ __volatile__ (
  684. ".set push\n\t"
  685. ".set noat\n\t"
  686. ".set "MIPS_ISA_LEVEL"\n\t"
  687. #ifdef CONFIG_32BIT
  688. "la $at,1f\n\t"
  689. #endif
  690. #ifdef CONFIG_64BIT
  691. "dla $at,1f\n\t"
  692. #endif
  693. "cache %0,($at)\n\t"
  694. "nop; nop; nop\n"
  695. "1:\n\t"
  696. ".set pop"
  697. :
  698. : "i" (Hit_Invalidate_I));
  699. }
  700. if (MIPS_CACHE_SYNC_WAR)
  701. __asm__ __volatile__ ("sync");
  702. }
  703. static void r4k_flush_cache_sigtramp(unsigned long addr)
  704. {
  705. r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
  706. }
  707. static void r4k_flush_icache_all(void)
  708. {
  709. if (cpu_has_vtag_icache)
  710. r4k_blast_icache();
  711. }
  712. struct flush_kernel_vmap_range_args {
  713. unsigned long vaddr;
  714. int size;
  715. };
  716. static inline void local_r4k_flush_kernel_vmap_range(void *args)
  717. {
  718. struct flush_kernel_vmap_range_args *vmra = args;
  719. unsigned long vaddr = vmra->vaddr;
  720. int size = vmra->size;
  721. /*
  722. * Aliases only affect the primary caches so don't bother with
  723. * S-caches or T-caches.
  724. */
  725. if (cpu_has_safe_index_cacheops && size >= dcache_size)
  726. r4k_blast_dcache();
  727. else {
  728. R4600_HIT_CACHEOP_WAR_IMPL;
  729. blast_dcache_range(vaddr, vaddr + size);
  730. }
  731. }
  732. static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
  733. {
  734. struct flush_kernel_vmap_range_args args;
  735. args.vaddr = (unsigned long) vaddr;
  736. args.size = size;
  737. r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
  738. }
  739. static inline void rm7k_erratum31(void)
  740. {
  741. const unsigned long ic_lsize = 32;
  742. unsigned long addr;
  743. /* RM7000 erratum #31. The icache is screwed at startup. */
  744. write_c0_taglo(0);
  745. write_c0_taghi(0);
  746. for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
  747. __asm__ __volatile__ (
  748. ".set push\n\t"
  749. ".set noreorder\n\t"
  750. ".set mips3\n\t"
  751. "cache\t%1, 0(%0)\n\t"
  752. "cache\t%1, 0x1000(%0)\n\t"
  753. "cache\t%1, 0x2000(%0)\n\t"
  754. "cache\t%1, 0x3000(%0)\n\t"
  755. "cache\t%2, 0(%0)\n\t"
  756. "cache\t%2, 0x1000(%0)\n\t"
  757. "cache\t%2, 0x2000(%0)\n\t"
  758. "cache\t%2, 0x3000(%0)\n\t"
  759. "cache\t%1, 0(%0)\n\t"
  760. "cache\t%1, 0x1000(%0)\n\t"
  761. "cache\t%1, 0x2000(%0)\n\t"
  762. "cache\t%1, 0x3000(%0)\n\t"
  763. ".set pop\n"
  764. :
  765. : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
  766. }
  767. }
  768. static inline int alias_74k_erratum(struct cpuinfo_mips *c)
  769. {
  770. unsigned int imp = c->processor_id & PRID_IMP_MASK;
  771. unsigned int rev = c->processor_id & PRID_REV_MASK;
  772. int present = 0;
  773. /*
  774. * Early versions of the 74K do not update the cache tags on a
  775. * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
  776. * aliases. In this case it is better to treat the cache as always
  777. * having aliases. Also disable the synonym tag update feature
  778. * where available. In this case no opportunistic tag update will
  779. * happen where a load causes a virtual address miss but a physical
  780. * address hit during a D-cache look-up.
  781. */
  782. switch (imp) {
  783. case PRID_IMP_74K:
  784. if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
  785. present = 1;
  786. if (rev == PRID_REV_ENCODE_332(2, 4, 0))
  787. write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
  788. break;
  789. case PRID_IMP_1074K:
  790. if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
  791. present = 1;
  792. write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
  793. }
  794. break;
  795. default:
  796. BUG();
  797. }
  798. return present;
  799. }
  800. static void b5k_instruction_hazard(void)
  801. {
  802. __sync();
  803. __sync();
  804. __asm__ __volatile__(
  805. " nop; nop; nop; nop; nop; nop; nop; nop\n"
  806. " nop; nop; nop; nop; nop; nop; nop; nop\n"
  807. " nop; nop; nop; nop; nop; nop; nop; nop\n"
  808. " nop; nop; nop; nop; nop; nop; nop; nop\n"
  809. : : : "memory");
  810. }
  811. static char *way_string[] = { NULL, "direct mapped", "2-way",
  812. "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
  813. };
  814. static void probe_pcache(void)
  815. {
  816. struct cpuinfo_mips *c = &current_cpu_data;
  817. unsigned int config = read_c0_config();
  818. unsigned int prid = read_c0_prid();
  819. int has_74k_erratum = 0;
  820. unsigned long config1;
  821. unsigned int lsize;
  822. switch (current_cpu_type()) {
  823. case CPU_R4600: /* QED style two way caches? */
  824. case CPU_R4700:
  825. case CPU_R5000:
  826. case CPU_NEVADA:
  827. icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
  828. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  829. c->icache.ways = 2;
  830. c->icache.waybit = __ffs(icache_size/2);
  831. dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
  832. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  833. c->dcache.ways = 2;
  834. c->dcache.waybit= __ffs(dcache_size/2);
  835. c->options |= MIPS_CPU_CACHE_CDEX_P;
  836. break;
  837. case CPU_R5432:
  838. case CPU_R5500:
  839. icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
  840. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  841. c->icache.ways = 2;
  842. c->icache.waybit= 0;
  843. dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
  844. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  845. c->dcache.ways = 2;
  846. c->dcache.waybit = 0;
  847. c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
  848. break;
  849. case CPU_TX49XX:
  850. icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
  851. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  852. c->icache.ways = 4;
  853. c->icache.waybit= 0;
  854. dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
  855. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  856. c->dcache.ways = 4;
  857. c->dcache.waybit = 0;
  858. c->options |= MIPS_CPU_CACHE_CDEX_P;
  859. c->options |= MIPS_CPU_PREFETCH;
  860. break;
  861. case CPU_R4000PC:
  862. case CPU_R4000SC:
  863. case CPU_R4000MC:
  864. case CPU_R4400PC:
  865. case CPU_R4400SC:
  866. case CPU_R4400MC:
  867. case CPU_R4300:
  868. icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
  869. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  870. c->icache.ways = 1;
  871. c->icache.waybit = 0; /* doesn't matter */
  872. dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
  873. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  874. c->dcache.ways = 1;
  875. c->dcache.waybit = 0; /* does not matter */
  876. c->options |= MIPS_CPU_CACHE_CDEX_P;
  877. break;
  878. case CPU_R10000:
  879. case CPU_R12000:
  880. case CPU_R14000:
  881. case CPU_R16000:
  882. icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
  883. c->icache.linesz = 64;
  884. c->icache.ways = 2;
  885. c->icache.waybit = 0;
  886. dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
  887. c->dcache.linesz = 32;
  888. c->dcache.ways = 2;
  889. c->dcache.waybit = 0;
  890. c->options |= MIPS_CPU_PREFETCH;
  891. break;
  892. case CPU_VR4133:
  893. write_c0_config(config & ~VR41_CONF_P4K);
  894. case CPU_VR4131:
  895. /* Workaround for cache instruction bug of VR4131 */
  896. if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
  897. c->processor_id == 0x0c82U) {
  898. config |= 0x00400000U;
  899. if (c->processor_id == 0x0c80U)
  900. config |= VR41_CONF_BP;
  901. write_c0_config(config);
  902. } else
  903. c->options |= MIPS_CPU_CACHE_CDEX_P;
  904. icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
  905. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  906. c->icache.ways = 2;
  907. c->icache.waybit = __ffs(icache_size/2);
  908. dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
  909. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  910. c->dcache.ways = 2;
  911. c->dcache.waybit = __ffs(dcache_size/2);
  912. break;
  913. case CPU_VR41XX:
  914. case CPU_VR4111:
  915. case CPU_VR4121:
  916. case CPU_VR4122:
  917. case CPU_VR4181:
  918. case CPU_VR4181A:
  919. icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
  920. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  921. c->icache.ways = 1;
  922. c->icache.waybit = 0; /* doesn't matter */
  923. dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
  924. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  925. c->dcache.ways = 1;
  926. c->dcache.waybit = 0; /* does not matter */
  927. c->options |= MIPS_CPU_CACHE_CDEX_P;
  928. break;
  929. case CPU_RM7000:
  930. rm7k_erratum31();
  931. icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
  932. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  933. c->icache.ways = 4;
  934. c->icache.waybit = __ffs(icache_size / c->icache.ways);
  935. dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
  936. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  937. c->dcache.ways = 4;
  938. c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
  939. c->options |= MIPS_CPU_CACHE_CDEX_P;
  940. c->options |= MIPS_CPU_PREFETCH;
  941. break;
  942. case CPU_LOONGSON2:
  943. icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
  944. c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
  945. if (prid & 0x3)
  946. c->icache.ways = 4;
  947. else
  948. c->icache.ways = 2;
  949. c->icache.waybit = 0;
  950. dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
  951. c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
  952. if (prid & 0x3)
  953. c->dcache.ways = 4;
  954. else
  955. c->dcache.ways = 2;
  956. c->dcache.waybit = 0;
  957. break;
  958. case CPU_LOONGSON3:
  959. config1 = read_c0_config1();
  960. lsize = (config1 >> 19) & 7;
  961. if (lsize)
  962. c->icache.linesz = 2 << lsize;
  963. else
  964. c->icache.linesz = 0;
  965. c->icache.sets = 64 << ((config1 >> 22) & 7);
  966. c->icache.ways = 1 + ((config1 >> 16) & 7);
  967. icache_size = c->icache.sets *
  968. c->icache.ways *
  969. c->icache.linesz;
  970. c->icache.waybit = 0;
  971. lsize = (config1 >> 10) & 7;
  972. if (lsize)
  973. c->dcache.linesz = 2 << lsize;
  974. else
  975. c->dcache.linesz = 0;
  976. c->dcache.sets = 64 << ((config1 >> 13) & 7);
  977. c->dcache.ways = 1 + ((config1 >> 7) & 7);
  978. dcache_size = c->dcache.sets *
  979. c->dcache.ways *
  980. c->dcache.linesz;
  981. c->dcache.waybit = 0;
  982. break;
  983. case CPU_CAVIUM_OCTEON3:
  984. /* For now lie about the number of ways. */
  985. c->icache.linesz = 128;
  986. c->icache.sets = 16;
  987. c->icache.ways = 8;
  988. c->icache.flags |= MIPS_CACHE_VTAG;
  989. icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
  990. c->dcache.linesz = 128;
  991. c->dcache.ways = 8;
  992. c->dcache.sets = 8;
  993. dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
  994. c->options |= MIPS_CPU_PREFETCH;
  995. break;
  996. default:
  997. if (!(config & MIPS_CONF_M))
  998. panic("Don't know how to probe P-caches on this cpu.");
  999. /*
  1000. * So we seem to be a MIPS32 or MIPS64 CPU
  1001. * So let's probe the I-cache ...
  1002. */
  1003. config1 = read_c0_config1();
  1004. lsize = (config1 >> 19) & 7;
  1005. /* IL == 7 is reserved */
  1006. if (lsize == 7)
  1007. panic("Invalid icache line size");
  1008. c->icache.linesz = lsize ? 2 << lsize : 0;
  1009. c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
  1010. c->icache.ways = 1 + ((config1 >> 16) & 7);
  1011. icache_size = c->icache.sets *
  1012. c->icache.ways *
  1013. c->icache.linesz;
  1014. c->icache.waybit = __ffs(icache_size/c->icache.ways);
  1015. if (config & 0x8) /* VI bit */
  1016. c->icache.flags |= MIPS_CACHE_VTAG;
  1017. /*
  1018. * Now probe the MIPS32 / MIPS64 data cache.
  1019. */
  1020. c->dcache.flags = 0;
  1021. lsize = (config1 >> 10) & 7;
  1022. /* DL == 7 is reserved */
  1023. if (lsize == 7)
  1024. panic("Invalid dcache line size");
  1025. c->dcache.linesz = lsize ? 2 << lsize : 0;
  1026. c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
  1027. c->dcache.ways = 1 + ((config1 >> 7) & 7);
  1028. dcache_size = c->dcache.sets *
  1029. c->dcache.ways *
  1030. c->dcache.linesz;
  1031. c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
  1032. c->options |= MIPS_CPU_PREFETCH;
  1033. break;
  1034. }
  1035. /*
  1036. * Processor configuration sanity check for the R4000SC erratum
  1037. * #5. With page sizes larger than 32kB there is no possibility
  1038. * to get a VCE exception anymore so we don't care about this
  1039. * misconfiguration. The case is rather theoretical anyway;
  1040. * presumably no vendor is shipping his hardware in the "bad"
  1041. * configuration.
  1042. */
  1043. if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
  1044. (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
  1045. !(config & CONF_SC) && c->icache.linesz != 16 &&
  1046. PAGE_SIZE <= 0x8000)
  1047. panic("Improper R4000SC processor configuration detected");
  1048. /* compute a couple of other cache variables */
  1049. c->icache.waysize = icache_size / c->icache.ways;
  1050. c->dcache.waysize = dcache_size / c->dcache.ways;
  1051. c->icache.sets = c->icache.linesz ?
  1052. icache_size / (c->icache.linesz * c->icache.ways) : 0;
  1053. c->dcache.sets = c->dcache.linesz ?
  1054. dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
  1055. /*
  1056. * R1x000 P-caches are odd in a positive way. They're 32kB 2-way
  1057. * virtually indexed so normally would suffer from aliases. So
  1058. * normally they'd suffer from aliases but magic in the hardware deals
  1059. * with that for us so we don't need to take care ourselves.
  1060. */
  1061. switch (current_cpu_type()) {
  1062. case CPU_20KC:
  1063. case CPU_25KF:
  1064. case CPU_SB1:
  1065. case CPU_SB1A:
  1066. case CPU_XLR:
  1067. c->dcache.flags |= MIPS_CACHE_PINDEX;
  1068. break;
  1069. case CPU_R10000:
  1070. case CPU_R12000:
  1071. case CPU_R14000:
  1072. case CPU_R16000:
  1073. break;
  1074. case CPU_74K:
  1075. case CPU_1074K:
  1076. has_74k_erratum = alias_74k_erratum(c);
  1077. /* Fall through. */
  1078. case CPU_M14KC:
  1079. case CPU_M14KEC:
  1080. case CPU_24K:
  1081. case CPU_34K:
  1082. case CPU_1004K:
  1083. case CPU_INTERAPTIV:
  1084. case CPU_P5600:
  1085. case CPU_PROAPTIV:
  1086. case CPU_M5150:
  1087. case CPU_QEMU_GENERIC:
  1088. if (!(read_c0_config7() & MIPS_CONF7_IAR) &&
  1089. (c->icache.waysize > PAGE_SIZE))
  1090. c->icache.flags |= MIPS_CACHE_ALIASES;
  1091. if (!has_74k_erratum && (read_c0_config7() & MIPS_CONF7_AR)) {
  1092. /*
  1093. * Effectively physically indexed dcache,
  1094. * thus no virtual aliases.
  1095. */
  1096. c->dcache.flags |= MIPS_CACHE_PINDEX;
  1097. break;
  1098. }
  1099. default:
  1100. if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE)
  1101. c->dcache.flags |= MIPS_CACHE_ALIASES;
  1102. }
  1103. switch (current_cpu_type()) {
  1104. case CPU_20KC:
  1105. /*
  1106. * Some older 20Kc chips doesn't have the 'VI' bit in
  1107. * the config register.
  1108. */
  1109. c->icache.flags |= MIPS_CACHE_VTAG;
  1110. break;
  1111. case CPU_ALCHEMY:
  1112. c->icache.flags |= MIPS_CACHE_IC_F_DC;
  1113. break;
  1114. case CPU_LOONGSON2:
  1115. /*
  1116. * LOONGSON2 has 4 way icache, but when using indexed cache op,
  1117. * one op will act on all 4 ways
  1118. */
  1119. c->icache.ways = 1;
  1120. }
  1121. printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
  1122. icache_size >> 10,
  1123. c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
  1124. way_string[c->icache.ways], c->icache.linesz);
  1125. printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
  1126. dcache_size >> 10, way_string[c->dcache.ways],
  1127. (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
  1128. (c->dcache.flags & MIPS_CACHE_ALIASES) ?
  1129. "cache aliases" : "no aliases",
  1130. c->dcache.linesz);
  1131. }
  1132. /*
  1133. * If you even _breathe_ on this function, look at the gcc output and make sure
  1134. * it does not pop things on and off the stack for the cache sizing loop that
  1135. * executes in KSEG1 space or else you will crash and burn badly. You have
  1136. * been warned.
  1137. */
  1138. static int probe_scache(void)
  1139. {
  1140. unsigned long flags, addr, begin, end, pow2;
  1141. unsigned int config = read_c0_config();
  1142. struct cpuinfo_mips *c = &current_cpu_data;
  1143. if (config & CONF_SC)
  1144. return 0;
  1145. begin = (unsigned long) &_stext;
  1146. begin &= ~((4 * 1024 * 1024) - 1);
  1147. end = begin + (4 * 1024 * 1024);
  1148. /*
  1149. * This is such a bitch, you'd think they would make it easy to do
  1150. * this. Away you daemons of stupidity!
  1151. */
  1152. local_irq_save(flags);
  1153. /* Fill each size-multiple cache line with a valid tag. */
  1154. pow2 = (64 * 1024);
  1155. for (addr = begin; addr < end; addr = (begin + pow2)) {
  1156. unsigned long *p = (unsigned long *) addr;
  1157. __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
  1158. pow2 <<= 1;
  1159. }
  1160. /* Load first line with zero (therefore invalid) tag. */
  1161. write_c0_taglo(0);
  1162. write_c0_taghi(0);
  1163. __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
  1164. cache_op(Index_Store_Tag_I, begin);
  1165. cache_op(Index_Store_Tag_D, begin);
  1166. cache_op(Index_Store_Tag_SD, begin);
  1167. /* Now search for the wrap around point. */
  1168. pow2 = (128 * 1024);
  1169. for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
  1170. cache_op(Index_Load_Tag_SD, addr);
  1171. __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
  1172. if (!read_c0_taglo())
  1173. break;
  1174. pow2 <<= 1;
  1175. }
  1176. local_irq_restore(flags);
  1177. addr -= begin;
  1178. scache_size = addr;
  1179. c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
  1180. c->scache.ways = 1;
  1181. c->scache.waybit = 0; /* does not matter */
  1182. return 1;
  1183. }
  1184. static void __init loongson2_sc_init(void)
  1185. {
  1186. struct cpuinfo_mips *c = &current_cpu_data;
  1187. scache_size = 512*1024;
  1188. c->scache.linesz = 32;
  1189. c->scache.ways = 4;
  1190. c->scache.waybit = 0;
  1191. c->scache.waysize = scache_size / (c->scache.ways);
  1192. c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
  1193. pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
  1194. scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
  1195. c->options |= MIPS_CPU_INCLUSIVE_CACHES;
  1196. }
  1197. static void __init loongson3_sc_init(void)
  1198. {
  1199. struct cpuinfo_mips *c = &current_cpu_data;
  1200. unsigned int config2, lsize;
  1201. config2 = read_c0_config2();
  1202. lsize = (config2 >> 4) & 15;
  1203. if (lsize)
  1204. c->scache.linesz = 2 << lsize;
  1205. else
  1206. c->scache.linesz = 0;
  1207. c->scache.sets = 64 << ((config2 >> 8) & 15);
  1208. c->scache.ways = 1 + (config2 & 15);
  1209. scache_size = c->scache.sets *
  1210. c->scache.ways *
  1211. c->scache.linesz;
  1212. /* Loongson-3 has 4 cores, 1MB scache for each. scaches are shared */
  1213. scache_size *= 4;
  1214. c->scache.waybit = 0;
  1215. pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
  1216. scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
  1217. if (scache_size)
  1218. c->options |= MIPS_CPU_INCLUSIVE_CACHES;
  1219. return;
  1220. }
  1221. extern int r5k_sc_init(void);
  1222. extern int rm7k_sc_init(void);
  1223. extern int mips_sc_init(void);
  1224. static void setup_scache(void)
  1225. {
  1226. struct cpuinfo_mips *c = &current_cpu_data;
  1227. unsigned int config = read_c0_config();
  1228. int sc_present = 0;
  1229. /*
  1230. * Do the probing thing on R4000SC and R4400SC processors. Other
  1231. * processors don't have a S-cache that would be relevant to the
  1232. * Linux memory management.
  1233. */
  1234. switch (current_cpu_type()) {
  1235. case CPU_R4000SC:
  1236. case CPU_R4000MC:
  1237. case CPU_R4400SC:
  1238. case CPU_R4400MC:
  1239. sc_present = run_uncached(probe_scache);
  1240. if (sc_present)
  1241. c->options |= MIPS_CPU_CACHE_CDEX_S;
  1242. break;
  1243. case CPU_R10000:
  1244. case CPU_R12000:
  1245. case CPU_R14000:
  1246. case CPU_R16000:
  1247. scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
  1248. c->scache.linesz = 64 << ((config >> 13) & 1);
  1249. c->scache.ways = 2;
  1250. c->scache.waybit= 0;
  1251. sc_present = 1;
  1252. break;
  1253. case CPU_R5000:
  1254. case CPU_NEVADA:
  1255. #ifdef CONFIG_R5000_CPU_SCACHE
  1256. r5k_sc_init();
  1257. #endif
  1258. return;
  1259. case CPU_RM7000:
  1260. #ifdef CONFIG_RM7000_CPU_SCACHE
  1261. rm7k_sc_init();
  1262. #endif
  1263. return;
  1264. case CPU_LOONGSON2:
  1265. loongson2_sc_init();
  1266. return;
  1267. case CPU_LOONGSON3:
  1268. loongson3_sc_init();
  1269. return;
  1270. case CPU_CAVIUM_OCTEON3:
  1271. case CPU_XLP:
  1272. /* don't need to worry about L2, fully coherent */
  1273. return;
  1274. default:
  1275. if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
  1276. MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
  1277. MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
  1278. #ifdef CONFIG_MIPS_CPU_SCACHE
  1279. if (mips_sc_init ()) {
  1280. scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
  1281. printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
  1282. scache_size >> 10,
  1283. way_string[c->scache.ways], c->scache.linesz);
  1284. }
  1285. #else
  1286. if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  1287. panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  1288. #endif
  1289. return;
  1290. }
  1291. sc_present = 0;
  1292. }
  1293. if (!sc_present)
  1294. return;
  1295. /* compute a couple of other cache variables */
  1296. c->scache.waysize = scache_size / c->scache.ways;
  1297. c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
  1298. printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
  1299. scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
  1300. c->options |= MIPS_CPU_INCLUSIVE_CACHES;
  1301. }
  1302. void au1x00_fixup_config_od(void)
  1303. {
  1304. /*
  1305. * c0_config.od (bit 19) was write only (and read as 0)
  1306. * on the early revisions of Alchemy SOCs. It disables the bus
  1307. * transaction overlapping and needs to be set to fix various errata.
  1308. */
  1309. switch (read_c0_prid()) {
  1310. case 0x00030100: /* Au1000 DA */
  1311. case 0x00030201: /* Au1000 HA */
  1312. case 0x00030202: /* Au1000 HB */
  1313. case 0x01030200: /* Au1500 AB */
  1314. /*
  1315. * Au1100 errata actually keeps silence about this bit, so we set it
  1316. * just in case for those revisions that require it to be set according
  1317. * to the (now gone) cpu table.
  1318. */
  1319. case 0x02030200: /* Au1100 AB */
  1320. case 0x02030201: /* Au1100 BA */
  1321. case 0x02030202: /* Au1100 BC */
  1322. set_c0_config(1 << 19);
  1323. break;
  1324. }
  1325. }
  1326. /* CP0 hazard avoidance. */
  1327. #define NXP_BARRIER() \
  1328. __asm__ __volatile__( \
  1329. ".set noreorder\n\t" \
  1330. "nop; nop; nop; nop; nop; nop;\n\t" \
  1331. ".set reorder\n\t")
  1332. static void nxp_pr4450_fixup_config(void)
  1333. {
  1334. unsigned long config0;
  1335. config0 = read_c0_config();
  1336. /* clear all three cache coherency fields */
  1337. config0 &= ~(0x7 | (7 << 25) | (7 << 28));
  1338. config0 |= (((_page_cachable_default >> _CACHE_SHIFT) << 0) |
  1339. ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
  1340. ((_page_cachable_default >> _CACHE_SHIFT) << 28));
  1341. write_c0_config(config0);
  1342. NXP_BARRIER();
  1343. }
  1344. static int cca = -1;
  1345. static int __init cca_setup(char *str)
  1346. {
  1347. get_option(&str, &cca);
  1348. return 0;
  1349. }
  1350. early_param("cca", cca_setup);
  1351. static void coherency_setup(void)
  1352. {
  1353. if (cca < 0 || cca > 7)
  1354. cca = read_c0_config() & CONF_CM_CMASK;
  1355. _page_cachable_default = cca << _CACHE_SHIFT;
  1356. pr_debug("Using cache attribute %d\n", cca);
  1357. change_c0_config(CONF_CM_CMASK, cca);
  1358. /*
  1359. * c0_status.cu=0 specifies that updates by the sc instruction use
  1360. * the coherency mode specified by the TLB; 1 means cachable
  1361. * coherent update on write will be used. Not all processors have
  1362. * this bit and; some wire it to zero, others like Toshiba had the
  1363. * silly idea of putting something else there ...
  1364. */
  1365. switch (current_cpu_type()) {
  1366. case CPU_R4000PC:
  1367. case CPU_R4000SC:
  1368. case CPU_R4000MC:
  1369. case CPU_R4400PC:
  1370. case CPU_R4400SC:
  1371. case CPU_R4400MC:
  1372. clear_c0_config(CONF_CU);
  1373. break;
  1374. /*
  1375. * We need to catch the early Alchemy SOCs with
  1376. * the write-only co_config.od bit and set it back to one on:
  1377. * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB
  1378. */
  1379. case CPU_ALCHEMY:
  1380. au1x00_fixup_config_od();
  1381. break;
  1382. case PRID_IMP_PR4450:
  1383. nxp_pr4450_fixup_config();
  1384. break;
  1385. }
  1386. }
  1387. static void r4k_cache_error_setup(void)
  1388. {
  1389. extern char __weak except_vec2_generic;
  1390. extern char __weak except_vec2_sb1;
  1391. switch (current_cpu_type()) {
  1392. case CPU_SB1:
  1393. case CPU_SB1A:
  1394. set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
  1395. break;
  1396. default:
  1397. set_uncached_handler(0x100, &except_vec2_generic, 0x80);
  1398. break;
  1399. }
  1400. }
  1401. void r4k_cache_init(void)
  1402. {
  1403. extern void build_clear_page(void);
  1404. extern void build_copy_page(void);
  1405. struct cpuinfo_mips *c = &current_cpu_data;
  1406. probe_pcache();
  1407. setup_scache();
  1408. r4k_blast_dcache_page_setup();
  1409. r4k_blast_dcache_page_indexed_setup();
  1410. r4k_blast_dcache_setup();
  1411. r4k_blast_icache_page_setup();
  1412. r4k_blast_icache_page_indexed_setup();
  1413. r4k_blast_icache_setup();
  1414. r4k_blast_scache_page_setup();
  1415. r4k_blast_scache_page_indexed_setup();
  1416. r4k_blast_scache_setup();
  1417. #ifdef CONFIG_EVA
  1418. r4k_blast_dcache_user_page_setup();
  1419. r4k_blast_icache_user_page_setup();
  1420. #endif
  1421. /*
  1422. * Some MIPS32 and MIPS64 processors have physically indexed caches.
  1423. * This code supports virtually indexed processors and will be
  1424. * unnecessarily inefficient on physically indexed processors.
  1425. */
  1426. if (c->dcache.linesz)
  1427. shm_align_mask = max_t( unsigned long,
  1428. c->dcache.sets * c->dcache.linesz - 1,
  1429. PAGE_SIZE - 1);
  1430. else
  1431. shm_align_mask = PAGE_SIZE-1;
  1432. __flush_cache_vmap = r4k__flush_cache_vmap;
  1433. __flush_cache_vunmap = r4k__flush_cache_vunmap;
  1434. flush_cache_all = cache_noop;
  1435. __flush_cache_all = r4k___flush_cache_all;
  1436. flush_cache_mm = r4k_flush_cache_mm;
  1437. flush_cache_page = r4k_flush_cache_page;
  1438. flush_cache_range = r4k_flush_cache_range;
  1439. __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
  1440. flush_cache_sigtramp = r4k_flush_cache_sigtramp;
  1441. flush_icache_all = r4k_flush_icache_all;
  1442. local_flush_data_cache_page = local_r4k_flush_data_cache_page;
  1443. flush_data_cache_page = r4k_flush_data_cache_page;
  1444. flush_icache_range = r4k_flush_icache_range;
  1445. local_flush_icache_range = local_r4k_flush_icache_range;
  1446. #if defined(CONFIG_DMA_NONCOHERENT) || defined(CONFIG_DMA_MAYBE_COHERENT)
  1447. if (coherentio) {
  1448. _dma_cache_wback_inv = (void *)cache_noop;
  1449. _dma_cache_wback = (void *)cache_noop;
  1450. _dma_cache_inv = (void *)cache_noop;
  1451. } else {
  1452. _dma_cache_wback_inv = r4k_dma_cache_wback_inv;
  1453. _dma_cache_wback = r4k_dma_cache_wback_inv;
  1454. _dma_cache_inv = r4k_dma_cache_inv;
  1455. }
  1456. #endif
  1457. build_clear_page();
  1458. build_copy_page();
  1459. /*
  1460. * We want to run CMP kernels on core with and without coherent
  1461. * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
  1462. * or not to flush caches.
  1463. */
  1464. local_r4k___flush_cache_all(NULL);
  1465. coherency_setup();
  1466. board_cache_error_setup = r4k_cache_error_setup;
  1467. /*
  1468. * Per-CPU overrides
  1469. */
  1470. switch (current_cpu_type()) {
  1471. case CPU_BMIPS4350:
  1472. case CPU_BMIPS4380:
  1473. /* No IPI is needed because all CPUs share the same D$ */
  1474. flush_data_cache_page = r4k_blast_dcache_page;
  1475. break;
  1476. case CPU_BMIPS5000:
  1477. /* We lose our superpowers if L2 is disabled */
  1478. if (c->scache.flags & MIPS_CACHE_NOT_PRESENT)
  1479. break;
  1480. /* I$ fills from D$ just by emptying the write buffers */
  1481. flush_cache_page = (void *)b5k_instruction_hazard;
  1482. flush_cache_range = (void *)b5k_instruction_hazard;
  1483. flush_cache_sigtramp = (void *)b5k_instruction_hazard;
  1484. local_flush_data_cache_page = (void *)b5k_instruction_hazard;
  1485. flush_data_cache_page = (void *)b5k_instruction_hazard;
  1486. flush_icache_range = (void *)b5k_instruction_hazard;
  1487. local_flush_icache_range = (void *)b5k_instruction_hazard;
  1488. /* Cache aliases are handled in hardware; allow HIGHMEM */
  1489. current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES;
  1490. /* Optimization: an L2 flush implicitly flushes the L1 */
  1491. current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES;
  1492. break;
  1493. }
  1494. }
  1495. static int r4k_cache_pm_notifier(struct notifier_block *self, unsigned long cmd,
  1496. void *v)
  1497. {
  1498. switch (cmd) {
  1499. case CPU_PM_ENTER_FAILED:
  1500. case CPU_PM_EXIT:
  1501. coherency_setup();
  1502. break;
  1503. }
  1504. return NOTIFY_OK;
  1505. }
  1506. static struct notifier_block r4k_cache_pm_notifier_block = {
  1507. .notifier_call = r4k_cache_pm_notifier,
  1508. };
  1509. int __init r4k_cache_init_pm(void)
  1510. {
  1511. return cpu_pm_register_notifier(&r4k_cache_pm_notifier_block);
  1512. }
  1513. arch_initcall(r4k_cache_init_pm);