dev-usb.c 6.0 KB

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  1. /*
  2. * Atheros AR7XXX/AR9XXX USB Host Controller device
  3. *
  4. * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  5. * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  6. *
  7. * Parts of this file are based on Atheros' 2.6.15 BSP
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License version 2 as published
  11. * by the Free Software Foundation.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/irq.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/usb/ehci_pdriver.h>
  20. #include <linux/usb/ohci_pdriver.h>
  21. #include <asm/mach-ath79/ath79.h>
  22. #include <asm/mach-ath79/ar71xx_regs.h>
  23. #include "common.h"
  24. #include "dev-usb.h"
  25. static u64 ath79_usb_dmamask = DMA_BIT_MASK(32);
  26. static struct usb_ohci_pdata ath79_ohci_pdata = {
  27. };
  28. static struct usb_ehci_pdata ath79_ehci_pdata_v1 = {
  29. .has_synopsys_hc_bug = 1,
  30. };
  31. static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
  32. .caps_offset = 0x100,
  33. .has_tt = 1,
  34. };
  35. static void __init ath79_usb_register(const char *name, int id,
  36. unsigned long base, unsigned long size,
  37. int irq, const void *data,
  38. size_t data_size)
  39. {
  40. struct resource res[2];
  41. struct platform_device *pdev;
  42. memset(res, 0, sizeof(res));
  43. res[0].flags = IORESOURCE_MEM;
  44. res[0].start = base;
  45. res[0].end = base + size - 1;
  46. res[1].flags = IORESOURCE_IRQ;
  47. res[1].start = irq;
  48. res[1].end = irq;
  49. pdev = platform_device_register_resndata(NULL, name, id,
  50. res, ARRAY_SIZE(res),
  51. data, data_size);
  52. if (IS_ERR(pdev)) {
  53. pr_err("ath79: unable to register USB at %08lx, err=%d\n",
  54. base, (int) PTR_ERR(pdev));
  55. return;
  56. }
  57. pdev->dev.dma_mask = &ath79_usb_dmamask;
  58. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  59. }
  60. #define AR71XX_USB_RESET_MASK (AR71XX_RESET_USB_HOST | \
  61. AR71XX_RESET_USB_PHY | \
  62. AR71XX_RESET_USB_OHCI_DLL)
  63. static void __init ath79_usb_setup(void)
  64. {
  65. void __iomem *usb_ctrl_base;
  66. ath79_device_reset_set(AR71XX_USB_RESET_MASK);
  67. mdelay(1000);
  68. ath79_device_reset_clear(AR71XX_USB_RESET_MASK);
  69. usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
  70. /* Turning on the Buff and Desc swap bits */
  71. __raw_writel(0xf0000, usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG);
  72. /* WAR for HW bug. Here it adjusts the duration between two SOFS */
  73. __raw_writel(0x20c00, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
  74. iounmap(usb_ctrl_base);
  75. mdelay(900);
  76. ath79_usb_register("ohci-platform", -1,
  77. AR71XX_OHCI_BASE, AR71XX_OHCI_SIZE,
  78. ATH79_MISC_IRQ(6),
  79. &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
  80. ath79_usb_register("ehci-platform", -1,
  81. AR71XX_EHCI_BASE, AR71XX_EHCI_SIZE,
  82. ATH79_CPU_IRQ(3),
  83. &ath79_ehci_pdata_v1, sizeof(ath79_ehci_pdata_v1));
  84. }
  85. static void __init ar7240_usb_setup(void)
  86. {
  87. void __iomem *usb_ctrl_base;
  88. ath79_device_reset_clear(AR7240_RESET_OHCI_DLL);
  89. ath79_device_reset_set(AR7240_RESET_USB_HOST);
  90. mdelay(1000);
  91. ath79_device_reset_set(AR7240_RESET_OHCI_DLL);
  92. ath79_device_reset_clear(AR7240_RESET_USB_HOST);
  93. usb_ctrl_base = ioremap(AR7240_USB_CTRL_BASE, AR7240_USB_CTRL_SIZE);
  94. /* WAR for HW bug. Here it adjusts the duration between two SOFS */
  95. __raw_writel(0x3, usb_ctrl_base + AR71XX_USB_CTRL_REG_FLADJ);
  96. iounmap(usb_ctrl_base);
  97. ath79_usb_register("ohci-platform", -1,
  98. AR7240_OHCI_BASE, AR7240_OHCI_SIZE,
  99. ATH79_CPU_IRQ(3),
  100. &ath79_ohci_pdata, sizeof(ath79_ohci_pdata));
  101. }
  102. static void __init ar724x_usb_setup(void)
  103. {
  104. ath79_device_reset_set(AR724X_RESET_USBSUS_OVERRIDE);
  105. mdelay(10);
  106. ath79_device_reset_clear(AR724X_RESET_USB_HOST);
  107. mdelay(10);
  108. ath79_device_reset_clear(AR724X_RESET_USB_PHY);
  109. mdelay(10);
  110. ath79_usb_register("ehci-platform", -1,
  111. AR724X_EHCI_BASE, AR724X_EHCI_SIZE,
  112. ATH79_CPU_IRQ(3),
  113. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  114. }
  115. static void __init ar913x_usb_setup(void)
  116. {
  117. ath79_device_reset_set(AR913X_RESET_USBSUS_OVERRIDE);
  118. mdelay(10);
  119. ath79_device_reset_clear(AR913X_RESET_USB_HOST);
  120. mdelay(10);
  121. ath79_device_reset_clear(AR913X_RESET_USB_PHY);
  122. mdelay(10);
  123. ath79_usb_register("ehci-platform", -1,
  124. AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
  125. ATH79_CPU_IRQ(3),
  126. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  127. }
  128. static void __init ar933x_usb_setup(void)
  129. {
  130. ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
  131. mdelay(10);
  132. ath79_device_reset_clear(AR933X_RESET_USB_HOST);
  133. mdelay(10);
  134. ath79_device_reset_clear(AR933X_RESET_USB_PHY);
  135. mdelay(10);
  136. ath79_usb_register("ehci-platform", -1,
  137. AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
  138. ATH79_CPU_IRQ(3),
  139. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  140. }
  141. static void __init ar934x_usb_setup(void)
  142. {
  143. u32 bootstrap;
  144. bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
  145. if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
  146. return;
  147. ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
  148. udelay(1000);
  149. ath79_device_reset_clear(AR934X_RESET_USB_PHY);
  150. udelay(1000);
  151. ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
  152. udelay(1000);
  153. ath79_device_reset_clear(AR934X_RESET_USB_HOST);
  154. udelay(1000);
  155. ath79_usb_register("ehci-platform", -1,
  156. AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
  157. ATH79_CPU_IRQ(3),
  158. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  159. }
  160. static void __init qca955x_usb_setup(void)
  161. {
  162. ath79_usb_register("ehci-platform", 0,
  163. QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
  164. ATH79_IP3_IRQ(0),
  165. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  166. ath79_usb_register("ehci-platform", 1,
  167. QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,
  168. ATH79_IP3_IRQ(1),
  169. &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  170. }
  171. void __init ath79_register_usb(void)
  172. {
  173. if (soc_is_ar71xx())
  174. ath79_usb_setup();
  175. else if (soc_is_ar7240())
  176. ar7240_usb_setup();
  177. else if (soc_is_ar7241() || soc_is_ar7242())
  178. ar724x_usb_setup();
  179. else if (soc_is_ar913x())
  180. ar913x_usb_setup();
  181. else if (soc_is_ar933x())
  182. ar933x_usb_setup();
  183. else if (soc_is_ar934x())
  184. ar934x_usb_setup();
  185. else if (soc_is_qca955x())
  186. qca955x_usb_setup();
  187. else
  188. BUG();
  189. }