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- NVIDIA Tegra20 SFLASH controller.
- Required properties:
- - compatible : should be "nvidia,tegra20-sflash".
- - reg: Should contain SFLASH registers location and length.
- - interrupts: Should contain SFLASH interrupts.
- - clocks : Must contain one entry, for the module clock.
- See ../clocks/clock-bindings.txt for details.
- - resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
- - reset-names : Must include the following entries:
- - spi
- - dmas : Must contain an entry for each entry in clock-names.
- See ../dma/dma.txt for details.
- - dma-names : Must include the following entries:
- - rx
- - tx
- Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
- Example:
- spi@7000c380 {
- compatible = "nvidia,tegra20-sflash";
- reg = <0x7000c380 0x80>;
- interrupts = <0 39 0x04>;
- spi-max-frequency = <25000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&tegra_car 43>;
- resets = <&tegra_car 43>;
- reset-names = "spi";
- dmas = <&apbdma 11>, <&apbdma 11>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
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