coda.txt 1002 B

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  1. Chips&Media Coda multi-standard codec IP
  2. ========================================
  3. Coda codec IPs are present in i.MX SoCs in various versions,
  4. called VPU (Video Processing Unit).
  5. Required properties:
  6. - compatible : should be "fsl,<chip>-src" for i.MX SoCs:
  7. (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
  8. (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
  9. (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
  10. - reg: should be register base and length as documented in the
  11. SoC reference manual
  12. - interrupts : Should contain the VPU interrupt. For CODA960,
  13. a second interrupt is needed for the MJPEG unit.
  14. - clocks : Should contain the ahb and per clocks, in the order
  15. determined by the clock-names property.
  16. - clock-names : Should be "ahb", "per"
  17. - iram : phandle pointing to the SRAM device node
  18. Example:
  19. vpu: vpu@63ff4000 {
  20. compatible = "fsl,imx53-vpu";
  21. reg = <0x63ff4000 0x1000>;
  22. interrupts = <9>;
  23. clocks = <&clks 63>, <&clks 63>;
  24. clock-names = "ahb", "per";
  25. iram = <&ocram>;
  26. };