imx25-clock.txt 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162
  1. * Clock bindings for Freescale i.MX25
  2. Required properties:
  3. - compatible: Should be "fsl,imx25-ccm"
  4. - reg: Address and length of the register set
  5. - interrupts: Should contain CCM interrupt
  6. - #clock-cells: Should be <1>
  7. The clock consumer should specify the desired clock by having the clock
  8. ID in its "clocks" phandle cell. The following is a full list of i.MX25
  9. clocks and IDs.
  10. Clock ID
  11. ---------------------------
  12. dummy 0
  13. osc 1
  14. mpll 2
  15. upll 3
  16. mpll_cpu_3_4 4
  17. cpu_sel 5
  18. cpu 6
  19. ahb 7
  20. usb_div 8
  21. ipg 9
  22. per0_sel 10
  23. per1_sel 11
  24. per2_sel 12
  25. per3_sel 13
  26. per4_sel 14
  27. per5_sel 15
  28. per6_sel 16
  29. per7_sel 17
  30. per8_sel 18
  31. per9_sel 19
  32. per10_sel 20
  33. per11_sel 21
  34. per12_sel 22
  35. per13_sel 23
  36. per14_sel 24
  37. per15_sel 25
  38. per0 26
  39. per1 27
  40. per2 28
  41. per3 29
  42. per4 30
  43. per5 31
  44. per6 32
  45. per7 33
  46. per8 34
  47. per9 35
  48. per10 36
  49. per11 37
  50. per12 38
  51. per13 39
  52. per14 40
  53. per15 41
  54. csi_ipg_per 42
  55. epit_ipg_per 43
  56. esai_ipg_per 44
  57. esdhc1_ipg_per 45
  58. esdhc2_ipg_per 46
  59. gpt_ipg_per 47
  60. i2c_ipg_per 48
  61. lcdc_ipg_per 49
  62. nfc_ipg_per 50
  63. owire_ipg_per 51
  64. pwm_ipg_per 52
  65. sim1_ipg_per 53
  66. sim2_ipg_per 54
  67. ssi1_ipg_per 55
  68. ssi2_ipg_per 56
  69. uart_ipg_per 57
  70. ata_ahb 58
  71. reserved 59
  72. csi_ahb 60
  73. emi_ahb 61
  74. esai_ahb 62
  75. esdhc1_ahb 63
  76. esdhc2_ahb 64
  77. fec_ahb 65
  78. lcdc_ahb 66
  79. rtic_ahb 67
  80. sdma_ahb 68
  81. slcdc_ahb 69
  82. usbotg_ahb 70
  83. reserved 71
  84. reserved 72
  85. reserved 73
  86. reserved 74
  87. can1_ipg 75
  88. can2_ipg 76
  89. csi_ipg 77
  90. cspi1_ipg 78
  91. cspi2_ipg 79
  92. cspi3_ipg 80
  93. dryice_ipg 81
  94. ect_ipg 82
  95. epit1_ipg 83
  96. epit2_ipg 84
  97. reserved 85
  98. esdhc1_ipg 86
  99. esdhc2_ipg 87
  100. fec_ipg 88
  101. reserved 89
  102. reserved 90
  103. reserved 91
  104. gpt1_ipg 92
  105. gpt2_ipg 93
  106. gpt3_ipg 94
  107. gpt4_ipg 95
  108. reserved 96
  109. reserved 97
  110. reserved 98
  111. iim_ipg 99
  112. reserved 100
  113. reserved 101
  114. kpp_ipg 102
  115. lcdc_ipg 103
  116. reserved 104
  117. pwm1_ipg 105
  118. pwm2_ipg 106
  119. pwm3_ipg 107
  120. pwm4_ipg 108
  121. rngb_ipg 109
  122. reserved 110
  123. scc_ipg 111
  124. sdma_ipg 112
  125. sim1_ipg 113
  126. sim2_ipg 114
  127. slcdc_ipg 115
  128. spba_ipg 116
  129. ssi1_ipg 117
  130. ssi2_ipg 118
  131. tsc_ipg 119
  132. uart1_ipg 120
  133. uart2_ipg 121
  134. uart3_ipg 122
  135. uart4_ipg 123
  136. uart5_ipg 124
  137. reserved 125
  138. wdt_ipg 126
  139. cko_div 127
  140. cko_sel 128
  141. cko 129
  142. Examples:
  143. clks: ccm@53f80000 {
  144. compatible = "fsl,imx25-ccm";
  145. reg = <0x53f80000 0x4000>;
  146. interrupts = <31>;
  147. };
  148. uart1: serial@43f90000 {
  149. compatible = "fsl,imx25-uart", "fsl,imx21-uart";
  150. reg = <0x43f90000 0x4000>;
  151. interrupts = <45>;
  152. clocks = <&clks 79>, <&clks 50>;
  153. clock-names = "ipg", "per";
  154. status = "disabled";
  155. };