arm_vgic.h 9.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352
  1. /*
  2. * Copyright (C) 2012 ARM Ltd.
  3. * Author: Marc Zyngier <marc.zyngier@arm.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  17. */
  18. #ifndef __ASM_ARM_KVM_VGIC_H
  19. #define __ASM_ARM_KVM_VGIC_H
  20. #include <linux/kernel.h>
  21. #include <linux/kvm.h>
  22. #include <linux/irqreturn.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/types.h>
  25. #include <kvm/iodev.h>
  26. #define VGIC_NR_IRQS_LEGACY 256
  27. #define VGIC_NR_SGIS 16
  28. #define VGIC_NR_PPIS 16
  29. #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
  30. #define VGIC_V2_MAX_LRS (1 << 6)
  31. #define VGIC_V3_MAX_LRS 16
  32. #define VGIC_MAX_IRQS 1024
  33. #define VGIC_V2_MAX_CPUS 8
  34. /* Sanity checks... */
  35. #if (KVM_MAX_VCPUS > 255)
  36. #error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now
  37. #endif
  38. #if (VGIC_NR_IRQS_LEGACY & 31)
  39. #error "VGIC_NR_IRQS must be a multiple of 32"
  40. #endif
  41. #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
  42. #error "VGIC_NR_IRQS must be <= 1024"
  43. #endif
  44. /*
  45. * The GIC distributor registers describing interrupts have two parts:
  46. * - 32 per-CPU interrupts (SGI + PPI)
  47. * - a bunch of shared interrupts (SPI)
  48. */
  49. struct vgic_bitmap {
  50. /*
  51. * - One UL per VCPU for private interrupts (assumes UL is at
  52. * least 32 bits)
  53. * - As many UL as necessary for shared interrupts.
  54. *
  55. * The private interrupts are accessed via the "private"
  56. * field, one UL per vcpu (the state for vcpu n is in
  57. * private[n]). The shared interrupts are accessed via the
  58. * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
  59. */
  60. unsigned long *private;
  61. unsigned long *shared;
  62. };
  63. struct vgic_bytemap {
  64. /*
  65. * - 8 u32 per VCPU for private interrupts
  66. * - As many u32 as necessary for shared interrupts.
  67. *
  68. * The private interrupts are accessed via the "private"
  69. * field, (the state for vcpu n is in private[n*8] to
  70. * private[n*8 + 7]). The shared interrupts are accessed via
  71. * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
  72. * shared[(n-32)/4] word).
  73. */
  74. u32 *private;
  75. u32 *shared;
  76. };
  77. struct kvm_vcpu;
  78. enum vgic_type {
  79. VGIC_V2, /* Good ol' GICv2 */
  80. VGIC_V3, /* New fancy GICv3 */
  81. };
  82. #define LR_STATE_PENDING (1 << 0)
  83. #define LR_STATE_ACTIVE (1 << 1)
  84. #define LR_STATE_MASK (3 << 0)
  85. #define LR_EOI_INT (1 << 2)
  86. struct vgic_lr {
  87. u16 irq;
  88. u8 source;
  89. u8 state;
  90. };
  91. struct vgic_vmcr {
  92. u32 ctlr;
  93. u32 abpr;
  94. u32 bpr;
  95. u32 pmr;
  96. };
  97. struct vgic_ops {
  98. struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
  99. void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
  100. void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
  101. u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
  102. u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
  103. void (*clear_eisr)(struct kvm_vcpu *vcpu);
  104. u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
  105. void (*enable_underflow)(struct kvm_vcpu *vcpu);
  106. void (*disable_underflow)(struct kvm_vcpu *vcpu);
  107. void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
  108. void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
  109. void (*enable)(struct kvm_vcpu *vcpu);
  110. };
  111. struct vgic_params {
  112. /* vgic type */
  113. enum vgic_type type;
  114. /* Physical address of vgic virtual cpu interface */
  115. phys_addr_t vcpu_base;
  116. /* Number of list registers */
  117. u32 nr_lr;
  118. /* Interrupt number */
  119. unsigned int maint_irq;
  120. /* Virtual control interface base address */
  121. void __iomem *vctrl_base;
  122. int max_gic_vcpus;
  123. /* Only needed for the legacy KVM_CREATE_IRQCHIP */
  124. bool can_emulate_gicv2;
  125. };
  126. struct vgic_vm_ops {
  127. bool (*queue_sgi)(struct kvm_vcpu *, int irq);
  128. void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
  129. int (*init_model)(struct kvm *);
  130. int (*map_resources)(struct kvm *, const struct vgic_params *);
  131. };
  132. struct vgic_io_device {
  133. gpa_t addr;
  134. int len;
  135. const struct vgic_io_range *reg_ranges;
  136. struct kvm_vcpu *redist_vcpu;
  137. struct kvm_io_device dev;
  138. };
  139. struct vgic_dist {
  140. spinlock_t lock;
  141. bool in_kernel;
  142. bool ready;
  143. /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
  144. u32 vgic_model;
  145. int nr_cpus;
  146. int nr_irqs;
  147. /* Virtual control interface mapping */
  148. void __iomem *vctrl_base;
  149. /* Distributor and vcpu interface mapping in the guest */
  150. phys_addr_t vgic_dist_base;
  151. /* GICv2 and GICv3 use different mapped register blocks */
  152. union {
  153. phys_addr_t vgic_cpu_base;
  154. phys_addr_t vgic_redist_base;
  155. };
  156. /* Distributor enabled */
  157. u32 enabled;
  158. /* Interrupt enabled (one bit per IRQ) */
  159. struct vgic_bitmap irq_enabled;
  160. /* Level-triggered interrupt external input is asserted */
  161. struct vgic_bitmap irq_level;
  162. /*
  163. * Interrupt state is pending on the distributor
  164. */
  165. struct vgic_bitmap irq_pending;
  166. /*
  167. * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
  168. * interrupts. Essentially holds the state of the flip-flop in
  169. * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
  170. * Once set, it is only cleared for level-triggered interrupts on
  171. * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
  172. */
  173. struct vgic_bitmap irq_soft_pend;
  174. /* Level-triggered interrupt queued on VCPU interface */
  175. struct vgic_bitmap irq_queued;
  176. /* Interrupt was active when unqueue from VCPU interface */
  177. struct vgic_bitmap irq_active;
  178. /* Interrupt priority. Not used yet. */
  179. struct vgic_bytemap irq_priority;
  180. /* Level/edge triggered */
  181. struct vgic_bitmap irq_cfg;
  182. /*
  183. * Source CPU per SGI and target CPU:
  184. *
  185. * Each byte represent a SGI observable on a VCPU, each bit of
  186. * this byte indicating if the corresponding VCPU has
  187. * generated this interrupt. This is a GICv2 feature only.
  188. *
  189. * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
  190. * the SGIs observable on VCPUn.
  191. */
  192. u8 *irq_sgi_sources;
  193. /*
  194. * Target CPU for each SPI:
  195. *
  196. * Array of available SPI, each byte indicating the target
  197. * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
  198. */
  199. u8 *irq_spi_cpu;
  200. /*
  201. * Reverse lookup of irq_spi_cpu for faster compute pending:
  202. *
  203. * Array of bitmaps, one per VCPU, describing if IRQn is
  204. * routed to a particular VCPU.
  205. */
  206. struct vgic_bitmap *irq_spi_target;
  207. /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
  208. u32 *irq_spi_mpidr;
  209. /* Bitmap indicating which CPU has something pending */
  210. unsigned long *irq_pending_on_cpu;
  211. /* Bitmap indicating which CPU has active IRQs */
  212. unsigned long *irq_active_on_cpu;
  213. struct vgic_vm_ops vm_ops;
  214. struct vgic_io_device dist_iodev;
  215. struct vgic_io_device *redist_iodevs;
  216. };
  217. struct vgic_v2_cpu_if {
  218. u32 vgic_hcr;
  219. u32 vgic_vmcr;
  220. u32 vgic_misr; /* Saved only */
  221. u64 vgic_eisr; /* Saved only */
  222. u64 vgic_elrsr; /* Saved only */
  223. u32 vgic_apr;
  224. u32 vgic_lr[VGIC_V2_MAX_LRS];
  225. };
  226. struct vgic_v3_cpu_if {
  227. #ifdef CONFIG_ARM_GIC_V3
  228. u32 vgic_hcr;
  229. u32 vgic_vmcr;
  230. u32 vgic_sre; /* Restored only, change ignored */
  231. u32 vgic_misr; /* Saved only */
  232. u32 vgic_eisr; /* Saved only */
  233. u32 vgic_elrsr; /* Saved only */
  234. u32 vgic_ap0r[4];
  235. u32 vgic_ap1r[4];
  236. u64 vgic_lr[VGIC_V3_MAX_LRS];
  237. #endif
  238. };
  239. struct vgic_cpu {
  240. /* per IRQ to LR mapping */
  241. u8 *vgic_irq_lr_map;
  242. /* Pending/active/both interrupts on this VCPU */
  243. DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
  244. DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS);
  245. DECLARE_BITMAP( pend_act_percpu, VGIC_NR_PRIVATE_IRQS);
  246. /* Pending/active/both shared interrupts, dynamically sized */
  247. unsigned long *pending_shared;
  248. unsigned long *active_shared;
  249. unsigned long *pend_act_shared;
  250. /* Bitmap of used/free list registers */
  251. DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
  252. /* Number of list registers on this CPU */
  253. int nr_lr;
  254. /* CPU vif control registers for world switch */
  255. union {
  256. struct vgic_v2_cpu_if vgic_v2;
  257. struct vgic_v3_cpu_if vgic_v3;
  258. };
  259. };
  260. #define LR_EMPTY 0xff
  261. #define INT_STATUS_EOI (1 << 0)
  262. #define INT_STATUS_UNDERFLOW (1 << 1)
  263. struct kvm;
  264. struct kvm_vcpu;
  265. int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
  266. int kvm_vgic_hyp_init(void);
  267. int kvm_vgic_map_resources(struct kvm *kvm);
  268. int kvm_vgic_get_max_vcpus(void);
  269. int kvm_vgic_create(struct kvm *kvm, u32 type);
  270. void kvm_vgic_destroy(struct kvm *kvm);
  271. void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
  272. void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
  273. void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
  274. int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
  275. bool level);
  276. void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
  277. int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
  278. int kvm_vgic_vcpu_active_irq(struct kvm_vcpu *vcpu);
  279. #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
  280. #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
  281. #define vgic_ready(k) ((k)->arch.vgic.ready)
  282. int vgic_v2_probe(struct device_node *vgic_node,
  283. const struct vgic_ops **ops,
  284. const struct vgic_params **params);
  285. #ifdef CONFIG_ARM_GIC_V3
  286. int vgic_v3_probe(struct device_node *vgic_node,
  287. const struct vgic_ops **ops,
  288. const struct vgic_params **params);
  289. #else
  290. static inline int vgic_v3_probe(struct device_node *vgic_node,
  291. const struct vgic_ops **ops,
  292. const struct vgic_params **params)
  293. {
  294. return -ENODEV;
  295. }
  296. #endif
  297. #endif