vnic_dev.c 16 KB

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  1. /*
  2. * Copyright 2014 Cisco Systems, Inc. All rights reserved.
  3. *
  4. * This program is free software; you may redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  9. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  10. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  11. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  12. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  13. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  14. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  15. * SOFTWARE.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/errno.h>
  19. #include <linux/types.h>
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include <linux/if_ether.h>
  23. #include <linux/slab.h>
  24. #include "vnic_resource.h"
  25. #include "vnic_devcmd.h"
  26. #include "vnic_dev.h"
  27. #include "vnic_stats.h"
  28. #include "vnic_wq.h"
  29. #define VNIC_DVCMD_TMO 10000 /* Devcmd Timeout value */
  30. #define VNIC_NOTIFY_INTR_MASK 0x0000ffff00000000ULL
  31. struct devcmd2_controller {
  32. struct vnic_wq_ctrl __iomem *wq_ctrl;
  33. struct vnic_dev_ring results_ring;
  34. struct vnic_wq wq;
  35. struct vnic_devcmd2 *cmd_ring;
  36. struct devcmd2_result *result;
  37. u16 next_result;
  38. u16 result_size;
  39. int color;
  40. };
  41. struct vnic_res {
  42. void __iomem *vaddr;
  43. unsigned int count;
  44. };
  45. struct vnic_dev {
  46. void *priv;
  47. struct pci_dev *pdev;
  48. struct vnic_res res[RES_TYPE_MAX];
  49. enum vnic_dev_intr_mode intr_mode;
  50. struct vnic_devcmd __iomem *devcmd;
  51. struct vnic_devcmd_notify *notify;
  52. struct vnic_devcmd_notify notify_copy;
  53. dma_addr_t notify_pa;
  54. u32 *linkstatus;
  55. dma_addr_t linkstatus_pa;
  56. struct vnic_stats *stats;
  57. dma_addr_t stats_pa;
  58. struct vnic_devcmd_fw_info *fw_info;
  59. dma_addr_t fw_info_pa;
  60. u64 args[VNIC_DEVCMD_NARGS];
  61. struct devcmd2_controller *devcmd2;
  62. int (*devcmd_rtn)(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  63. int wait);
  64. };
  65. #define VNIC_MAX_RES_HDR_SIZE \
  66. (sizeof(struct vnic_resource_header) + \
  67. sizeof(struct vnic_resource) * RES_TYPE_MAX)
  68. #define VNIC_RES_STRIDE 128
  69. void *svnic_dev_priv(struct vnic_dev *vdev)
  70. {
  71. return vdev->priv;
  72. }
  73. static int vnic_dev_discover_res(struct vnic_dev *vdev,
  74. struct vnic_dev_bar *bar, unsigned int num_bars)
  75. {
  76. struct vnic_resource_header __iomem *rh;
  77. struct vnic_resource __iomem *r;
  78. u8 type;
  79. if (num_bars == 0)
  80. return -EINVAL;
  81. if (bar->len < VNIC_MAX_RES_HDR_SIZE) {
  82. pr_err("vNIC BAR0 res hdr length error\n");
  83. return -EINVAL;
  84. }
  85. rh = bar->vaddr;
  86. if (!rh) {
  87. pr_err("vNIC BAR0 res hdr not mem-mapped\n");
  88. return -EINVAL;
  89. }
  90. if (ioread32(&rh->magic) != VNIC_RES_MAGIC ||
  91. ioread32(&rh->version) != VNIC_RES_VERSION) {
  92. pr_err("vNIC BAR0 res magic/version error exp (%lx/%lx) curr (%x/%x)\n",
  93. VNIC_RES_MAGIC, VNIC_RES_VERSION,
  94. ioread32(&rh->magic), ioread32(&rh->version));
  95. return -EINVAL;
  96. }
  97. r = (struct vnic_resource __iomem *)(rh + 1);
  98. while ((type = ioread8(&r->type)) != RES_TYPE_EOL) {
  99. u8 bar_num = ioread8(&r->bar);
  100. u32 bar_offset = ioread32(&r->bar_offset);
  101. u32 count = ioread32(&r->count);
  102. u32 len;
  103. r++;
  104. if (bar_num >= num_bars)
  105. continue;
  106. if (!bar[bar_num].len || !bar[bar_num].vaddr)
  107. continue;
  108. switch (type) {
  109. case RES_TYPE_WQ:
  110. case RES_TYPE_RQ:
  111. case RES_TYPE_CQ:
  112. case RES_TYPE_INTR_CTRL:
  113. /* each count is stride bytes long */
  114. len = count * VNIC_RES_STRIDE;
  115. if (len + bar_offset > bar->len) {
  116. pr_err("vNIC BAR0 resource %d out-of-bounds, offset 0x%x + size 0x%x > bar len 0x%lx\n",
  117. type, bar_offset,
  118. len,
  119. bar->len);
  120. return -EINVAL;
  121. }
  122. break;
  123. case RES_TYPE_INTR_PBA_LEGACY:
  124. case RES_TYPE_DEVCMD:
  125. case RES_TYPE_DEVCMD2:
  126. len = count;
  127. break;
  128. default:
  129. continue;
  130. }
  131. vdev->res[type].count = count;
  132. vdev->res[type].vaddr = (char __iomem *)bar->vaddr + bar_offset;
  133. }
  134. return 0;
  135. }
  136. unsigned int svnic_dev_get_res_count(struct vnic_dev *vdev,
  137. enum vnic_res_type type)
  138. {
  139. return vdev->res[type].count;
  140. }
  141. void __iomem *svnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
  142. unsigned int index)
  143. {
  144. if (!vdev->res[type].vaddr)
  145. return NULL;
  146. switch (type) {
  147. case RES_TYPE_WQ:
  148. case RES_TYPE_RQ:
  149. case RES_TYPE_CQ:
  150. case RES_TYPE_INTR_CTRL:
  151. return (char __iomem *)vdev->res[type].vaddr +
  152. index * VNIC_RES_STRIDE;
  153. default:
  154. return (char __iomem *)vdev->res[type].vaddr;
  155. }
  156. }
  157. unsigned int svnic_dev_desc_ring_size(struct vnic_dev_ring *ring,
  158. unsigned int desc_count,
  159. unsigned int desc_size)
  160. {
  161. /* The base address of the desc rings must be 512 byte aligned.
  162. * Descriptor count is aligned to groups of 32 descriptors. A
  163. * count of 0 means the maximum 4096 descriptors. Descriptor
  164. * size is aligned to 16 bytes.
  165. */
  166. unsigned int count_align = 32;
  167. unsigned int desc_align = 16;
  168. ring->base_align = 512;
  169. if (desc_count == 0)
  170. desc_count = 4096;
  171. ring->desc_count = ALIGN(desc_count, count_align);
  172. ring->desc_size = ALIGN(desc_size, desc_align);
  173. ring->size = ring->desc_count * ring->desc_size;
  174. ring->size_unaligned = ring->size + ring->base_align;
  175. return ring->size_unaligned;
  176. }
  177. void svnic_dev_clear_desc_ring(struct vnic_dev_ring *ring)
  178. {
  179. memset(ring->descs, 0, ring->size);
  180. }
  181. int svnic_dev_alloc_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring,
  182. unsigned int desc_count, unsigned int desc_size)
  183. {
  184. svnic_dev_desc_ring_size(ring, desc_count, desc_size);
  185. ring->descs_unaligned = pci_alloc_consistent(vdev->pdev,
  186. ring->size_unaligned,
  187. &ring->base_addr_unaligned);
  188. if (!ring->descs_unaligned) {
  189. pr_err("Failed to allocate ring (size=%d), aborting\n",
  190. (int)ring->size);
  191. return -ENOMEM;
  192. }
  193. ring->base_addr = ALIGN(ring->base_addr_unaligned,
  194. ring->base_align);
  195. ring->descs = (u8 *)ring->descs_unaligned +
  196. (ring->base_addr - ring->base_addr_unaligned);
  197. svnic_dev_clear_desc_ring(ring);
  198. ring->desc_avail = ring->desc_count - 1;
  199. return 0;
  200. }
  201. void svnic_dev_free_desc_ring(struct vnic_dev *vdev, struct vnic_dev_ring *ring)
  202. {
  203. if (ring->descs) {
  204. pci_free_consistent(vdev->pdev,
  205. ring->size_unaligned,
  206. ring->descs_unaligned,
  207. ring->base_addr_unaligned);
  208. ring->descs = NULL;
  209. }
  210. }
  211. static int _svnic_dev_cmd2(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  212. int wait)
  213. {
  214. struct devcmd2_controller *dc2c = vdev->devcmd2;
  215. struct devcmd2_result *result = dc2c->result + dc2c->next_result;
  216. unsigned int i;
  217. int delay;
  218. int err;
  219. u32 posted;
  220. u32 new_posted;
  221. posted = ioread32(&dc2c->wq_ctrl->posted_index);
  222. if (posted == 0xFFFFFFFF) { /* check for hardware gone */
  223. /* Hardware surprise removal: return error */
  224. return -ENODEV;
  225. }
  226. new_posted = (posted + 1) % DEVCMD2_RING_SIZE;
  227. dc2c->cmd_ring[posted].cmd = cmd;
  228. dc2c->cmd_ring[posted].flags = 0;
  229. if ((_CMD_FLAGS(cmd) & _CMD_FLAGS_NOWAIT))
  230. dc2c->cmd_ring[posted].flags |= DEVCMD2_FNORESULT;
  231. if (_CMD_DIR(cmd) & _CMD_DIR_WRITE) {
  232. for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
  233. dc2c->cmd_ring[posted].args[i] = vdev->args[i];
  234. }
  235. /* Adding write memory barrier prevents compiler and/or CPU
  236. * reordering, thus avoiding descriptor posting before
  237. * descriptor is initialized. Otherwise, hardware can read
  238. * stale descriptor fields.
  239. */
  240. wmb();
  241. iowrite32(new_posted, &dc2c->wq_ctrl->posted_index);
  242. if (dc2c->cmd_ring[posted].flags & DEVCMD2_FNORESULT)
  243. return 0;
  244. for (delay = 0; delay < wait; delay++) {
  245. udelay(100);
  246. if (result->color == dc2c->color) {
  247. dc2c->next_result++;
  248. if (dc2c->next_result == dc2c->result_size) {
  249. dc2c->next_result = 0;
  250. dc2c->color = dc2c->color ? 0 : 1;
  251. }
  252. if (result->error) {
  253. err = (int) result->error;
  254. if (err != ERR_ECMDUNKNOWN ||
  255. cmd != CMD_CAPABILITY)
  256. pr_err("Error %d devcmd %d\n",
  257. err, _CMD_N(cmd));
  258. return err;
  259. }
  260. if (_CMD_DIR(cmd) & _CMD_DIR_READ) {
  261. /*
  262. * Adding the rmb() prevents the compiler
  263. * and/or CPU from reordering the reads which
  264. * would potentially result in reading stale
  265. * values.
  266. */
  267. rmb();
  268. for (i = 0; i < VNIC_DEVCMD_NARGS; i++)
  269. vdev->args[i] = result->results[i];
  270. }
  271. return 0;
  272. }
  273. }
  274. pr_err("Timed out devcmd %d\n", _CMD_N(cmd));
  275. return -ETIMEDOUT;
  276. }
  277. static int svnic_dev_init_devcmd2(struct vnic_dev *vdev)
  278. {
  279. struct devcmd2_controller *dc2c = NULL;
  280. unsigned int fetch_idx;
  281. int ret;
  282. void __iomem *p;
  283. if (vdev->devcmd2)
  284. return 0;
  285. p = svnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
  286. if (!p)
  287. return -ENODEV;
  288. dc2c = kzalloc(sizeof(*dc2c), GFP_ATOMIC);
  289. if (!dc2c)
  290. return -ENOMEM;
  291. vdev->devcmd2 = dc2c;
  292. dc2c->color = 1;
  293. dc2c->result_size = DEVCMD2_RING_SIZE;
  294. ret = vnic_wq_devcmd2_alloc(vdev,
  295. &dc2c->wq,
  296. DEVCMD2_RING_SIZE,
  297. DEVCMD2_DESC_SIZE);
  298. if (ret)
  299. goto err_free_devcmd2;
  300. fetch_idx = ioread32(&dc2c->wq.ctrl->fetch_index);
  301. if (fetch_idx == 0xFFFFFFFF) { /* check for hardware gone */
  302. /* Hardware surprise removal: reset fetch_index */
  303. fetch_idx = 0;
  304. }
  305. /*
  306. * Don't change fetch_index ever and
  307. * set posted_index same as fetch_index
  308. * when setting up the WQ for devcmd2.
  309. */
  310. vnic_wq_init_start(&dc2c->wq, 0, fetch_idx, fetch_idx, 0, 0);
  311. svnic_wq_enable(&dc2c->wq);
  312. ret = svnic_dev_alloc_desc_ring(vdev,
  313. &dc2c->results_ring,
  314. DEVCMD2_RING_SIZE,
  315. DEVCMD2_DESC_SIZE);
  316. if (ret)
  317. goto err_free_wq;
  318. dc2c->result = (struct devcmd2_result *) dc2c->results_ring.descs;
  319. dc2c->cmd_ring = (struct vnic_devcmd2 *) dc2c->wq.ring.descs;
  320. dc2c->wq_ctrl = dc2c->wq.ctrl;
  321. vdev->args[0] = (u64) dc2c->results_ring.base_addr | VNIC_PADDR_TARGET;
  322. vdev->args[1] = DEVCMD2_RING_SIZE;
  323. ret = _svnic_dev_cmd2(vdev, CMD_INITIALIZE_DEVCMD2, VNIC_DVCMD_TMO);
  324. if (ret < 0)
  325. goto err_free_desc_ring;
  326. vdev->devcmd_rtn = &_svnic_dev_cmd2;
  327. pr_info("DEVCMD2 Initialized.\n");
  328. return ret;
  329. err_free_desc_ring:
  330. svnic_dev_free_desc_ring(vdev, &dc2c->results_ring);
  331. err_free_wq:
  332. svnic_wq_disable(&dc2c->wq);
  333. svnic_wq_free(&dc2c->wq);
  334. err_free_devcmd2:
  335. kfree(dc2c);
  336. vdev->devcmd2 = NULL;
  337. return ret;
  338. } /* end of svnic_dev_init_devcmd2 */
  339. static void vnic_dev_deinit_devcmd2(struct vnic_dev *vdev)
  340. {
  341. struct devcmd2_controller *dc2c = vdev->devcmd2;
  342. vdev->devcmd2 = NULL;
  343. vdev->devcmd_rtn = NULL;
  344. svnic_dev_free_desc_ring(vdev, &dc2c->results_ring);
  345. svnic_wq_disable(&dc2c->wq);
  346. svnic_wq_free(&dc2c->wq);
  347. kfree(dc2c);
  348. }
  349. int svnic_dev_cmd(struct vnic_dev *vdev, enum vnic_devcmd_cmd cmd,
  350. u64 *a0, u64 *a1, int wait)
  351. {
  352. int err;
  353. memset(vdev->args, 0, sizeof(vdev->args));
  354. vdev->args[0] = *a0;
  355. vdev->args[1] = *a1;
  356. err = (*vdev->devcmd_rtn)(vdev, cmd, wait);
  357. *a0 = vdev->args[0];
  358. *a1 = vdev->args[1];
  359. return err;
  360. }
  361. int svnic_dev_fw_info(struct vnic_dev *vdev,
  362. struct vnic_devcmd_fw_info **fw_info)
  363. {
  364. u64 a0, a1 = 0;
  365. int wait = VNIC_DVCMD_TMO;
  366. int err = 0;
  367. if (!vdev->fw_info) {
  368. vdev->fw_info = pci_alloc_consistent(vdev->pdev,
  369. sizeof(struct vnic_devcmd_fw_info),
  370. &vdev->fw_info_pa);
  371. if (!vdev->fw_info)
  372. return -ENOMEM;
  373. a0 = vdev->fw_info_pa;
  374. /* only get fw_info once and cache it */
  375. err = svnic_dev_cmd(vdev, CMD_MCPU_FW_INFO, &a0, &a1, wait);
  376. }
  377. *fw_info = vdev->fw_info;
  378. return err;
  379. }
  380. int svnic_dev_spec(struct vnic_dev *vdev, unsigned int offset,
  381. unsigned int size, void *value)
  382. {
  383. u64 a0, a1;
  384. int wait = VNIC_DVCMD_TMO;
  385. int err;
  386. a0 = offset;
  387. a1 = size;
  388. err = svnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);
  389. switch (size) {
  390. case 1:
  391. *(u8 *)value = (u8)a0;
  392. break;
  393. case 2:
  394. *(u16 *)value = (u16)a0;
  395. break;
  396. case 4:
  397. *(u32 *)value = (u32)a0;
  398. break;
  399. case 8:
  400. *(u64 *)value = a0;
  401. break;
  402. default:
  403. BUG();
  404. break;
  405. }
  406. return err;
  407. }
  408. int svnic_dev_stats_clear(struct vnic_dev *vdev)
  409. {
  410. u64 a0 = 0, a1 = 0;
  411. int wait = VNIC_DVCMD_TMO;
  412. return svnic_dev_cmd(vdev, CMD_STATS_CLEAR, &a0, &a1, wait);
  413. }
  414. int svnic_dev_stats_dump(struct vnic_dev *vdev, struct vnic_stats **stats)
  415. {
  416. u64 a0, a1;
  417. int wait = VNIC_DVCMD_TMO;
  418. if (!vdev->stats) {
  419. vdev->stats = pci_alloc_consistent(vdev->pdev,
  420. sizeof(struct vnic_stats), &vdev->stats_pa);
  421. if (!vdev->stats)
  422. return -ENOMEM;
  423. }
  424. *stats = vdev->stats;
  425. a0 = vdev->stats_pa;
  426. a1 = sizeof(struct vnic_stats);
  427. return svnic_dev_cmd(vdev, CMD_STATS_DUMP, &a0, &a1, wait);
  428. }
  429. int svnic_dev_close(struct vnic_dev *vdev)
  430. {
  431. u64 a0 = 0, a1 = 0;
  432. int wait = VNIC_DVCMD_TMO;
  433. return svnic_dev_cmd(vdev, CMD_CLOSE, &a0, &a1, wait);
  434. }
  435. int svnic_dev_enable_wait(struct vnic_dev *vdev)
  436. {
  437. u64 a0 = 0, a1 = 0;
  438. int wait = VNIC_DVCMD_TMO;
  439. int err = 0;
  440. err = svnic_dev_cmd(vdev, CMD_ENABLE_WAIT, &a0, &a1, wait);
  441. if (err == ERR_ECMDUNKNOWN)
  442. return svnic_dev_cmd(vdev, CMD_ENABLE, &a0, &a1, wait);
  443. return err;
  444. }
  445. int svnic_dev_disable(struct vnic_dev *vdev)
  446. {
  447. u64 a0 = 0, a1 = 0;
  448. int wait = VNIC_DVCMD_TMO;
  449. return svnic_dev_cmd(vdev, CMD_DISABLE, &a0, &a1, wait);
  450. }
  451. int svnic_dev_open(struct vnic_dev *vdev, int arg)
  452. {
  453. u64 a0 = (u32)arg, a1 = 0;
  454. int wait = VNIC_DVCMD_TMO;
  455. return svnic_dev_cmd(vdev, CMD_OPEN, &a0, &a1, wait);
  456. }
  457. int svnic_dev_open_done(struct vnic_dev *vdev, int *done)
  458. {
  459. u64 a0 = 0, a1 = 0;
  460. int wait = VNIC_DVCMD_TMO;
  461. int err;
  462. *done = 0;
  463. err = svnic_dev_cmd(vdev, CMD_OPEN_STATUS, &a0, &a1, wait);
  464. if (err)
  465. return err;
  466. *done = (a0 == 0);
  467. return 0;
  468. }
  469. int svnic_dev_notify_set(struct vnic_dev *vdev, u16 intr)
  470. {
  471. u64 a0, a1;
  472. int wait = VNIC_DVCMD_TMO;
  473. if (!vdev->notify) {
  474. vdev->notify = pci_alloc_consistent(vdev->pdev,
  475. sizeof(struct vnic_devcmd_notify),
  476. &vdev->notify_pa);
  477. if (!vdev->notify)
  478. return -ENOMEM;
  479. }
  480. a0 = vdev->notify_pa;
  481. a1 = ((u64)intr << 32) & VNIC_NOTIFY_INTR_MASK;
  482. a1 += sizeof(struct vnic_devcmd_notify);
  483. return svnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
  484. }
  485. void svnic_dev_notify_unset(struct vnic_dev *vdev)
  486. {
  487. u64 a0, a1;
  488. int wait = VNIC_DVCMD_TMO;
  489. a0 = 0; /* paddr = 0 to unset notify buffer */
  490. a1 = VNIC_NOTIFY_INTR_MASK; /* intr num = -1 to unreg for intr */
  491. a1 += sizeof(struct vnic_devcmd_notify);
  492. svnic_dev_cmd(vdev, CMD_NOTIFY, &a0, &a1, wait);
  493. }
  494. static int vnic_dev_notify_ready(struct vnic_dev *vdev)
  495. {
  496. u32 *words;
  497. unsigned int nwords = sizeof(struct vnic_devcmd_notify) / 4;
  498. unsigned int i;
  499. u32 csum;
  500. if (!vdev->notify)
  501. return 0;
  502. do {
  503. csum = 0;
  504. memcpy(&vdev->notify_copy, vdev->notify,
  505. sizeof(struct vnic_devcmd_notify));
  506. words = (u32 *)&vdev->notify_copy;
  507. for (i = 1; i < nwords; i++)
  508. csum += words[i];
  509. } while (csum != words[0]);
  510. return 1;
  511. }
  512. int svnic_dev_init(struct vnic_dev *vdev, int arg)
  513. {
  514. u64 a0 = (u32)arg, a1 = 0;
  515. int wait = VNIC_DVCMD_TMO;
  516. return svnic_dev_cmd(vdev, CMD_INIT, &a0, &a1, wait);
  517. }
  518. int svnic_dev_link_status(struct vnic_dev *vdev)
  519. {
  520. if (vdev->linkstatus)
  521. return *vdev->linkstatus;
  522. if (!vnic_dev_notify_ready(vdev))
  523. return 0;
  524. return vdev->notify_copy.link_state;
  525. }
  526. u32 svnic_dev_link_down_cnt(struct vnic_dev *vdev)
  527. {
  528. if (!vnic_dev_notify_ready(vdev))
  529. return 0;
  530. return vdev->notify_copy.link_down_cnt;
  531. }
  532. void svnic_dev_set_intr_mode(struct vnic_dev *vdev,
  533. enum vnic_dev_intr_mode intr_mode)
  534. {
  535. vdev->intr_mode = intr_mode;
  536. }
  537. enum vnic_dev_intr_mode svnic_dev_get_intr_mode(struct vnic_dev *vdev)
  538. {
  539. return vdev->intr_mode;
  540. }
  541. void svnic_dev_unregister(struct vnic_dev *vdev)
  542. {
  543. if (vdev) {
  544. if (vdev->notify)
  545. pci_free_consistent(vdev->pdev,
  546. sizeof(struct vnic_devcmd_notify),
  547. vdev->notify,
  548. vdev->notify_pa);
  549. if (vdev->linkstatus)
  550. pci_free_consistent(vdev->pdev,
  551. sizeof(u32),
  552. vdev->linkstatus,
  553. vdev->linkstatus_pa);
  554. if (vdev->stats)
  555. pci_free_consistent(vdev->pdev,
  556. sizeof(struct vnic_stats),
  557. vdev->stats, vdev->stats_pa);
  558. if (vdev->fw_info)
  559. pci_free_consistent(vdev->pdev,
  560. sizeof(struct vnic_devcmd_fw_info),
  561. vdev->fw_info, vdev->fw_info_pa);
  562. if (vdev->devcmd2)
  563. vnic_dev_deinit_devcmd2(vdev);
  564. kfree(vdev);
  565. }
  566. }
  567. struct vnic_dev *svnic_dev_alloc_discover(struct vnic_dev *vdev,
  568. void *priv,
  569. struct pci_dev *pdev,
  570. struct vnic_dev_bar *bar,
  571. unsigned int num_bars)
  572. {
  573. if (!vdev) {
  574. vdev = kzalloc(sizeof(struct vnic_dev), GFP_ATOMIC);
  575. if (!vdev)
  576. return NULL;
  577. }
  578. vdev->priv = priv;
  579. vdev->pdev = pdev;
  580. if (vnic_dev_discover_res(vdev, bar, num_bars))
  581. goto err_out;
  582. return vdev;
  583. err_out:
  584. svnic_dev_unregister(vdev);
  585. return NULL;
  586. } /* end of svnic_dev_alloc_discover */
  587. /*
  588. * fallback option is left to keep the interface common for other vnics.
  589. */
  590. int svnic_dev_cmd_init(struct vnic_dev *vdev, int fallback)
  591. {
  592. int err = -ENODEV;
  593. void __iomem *p;
  594. p = svnic_dev_get_res(vdev, RES_TYPE_DEVCMD2, 0);
  595. if (p)
  596. err = svnic_dev_init_devcmd2(vdev);
  597. else
  598. pr_err("DEVCMD2 resource not found.\n");
  599. return err;
  600. } /* end of svnic_dev_cmd_init */