pinctrl-armada-370.c 14 KB

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  1. /*
  2. * Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
  3. *
  4. * Copyright (C) 2012 Marvell
  5. *
  6. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/err.h>
  14. #include <linux/init.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/of.h>
  20. #include <linux/of_device.h>
  21. #include <linux/pinctrl/pinctrl.h>
  22. #include "pinctrl-mvebu.h"
  23. static void __iomem *mpp_base;
  24. static int armada_370_mpp_ctrl_get(unsigned pid, unsigned long *config)
  25. {
  26. return default_mpp_ctrl_get(mpp_base, pid, config);
  27. }
  28. static int armada_370_mpp_ctrl_set(unsigned pid, unsigned long config)
  29. {
  30. return default_mpp_ctrl_set(mpp_base, pid, config);
  31. }
  32. static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
  33. MPP_MODE(0,
  34. MPP_FUNCTION(0x0, "gpio", NULL),
  35. MPP_FUNCTION(0x1, "uart0", "rxd")),
  36. MPP_MODE(1,
  37. MPP_FUNCTION(0x0, "gpo", NULL),
  38. MPP_FUNCTION(0x1, "uart0", "txd")),
  39. MPP_MODE(2,
  40. MPP_FUNCTION(0x0, "gpio", NULL),
  41. MPP_FUNCTION(0x1, "i2c0", "sck"),
  42. MPP_FUNCTION(0x2, "uart0", "txd")),
  43. MPP_MODE(3,
  44. MPP_FUNCTION(0x0, "gpio", NULL),
  45. MPP_FUNCTION(0x1, "i2c0", "sda"),
  46. MPP_FUNCTION(0x2, "uart0", "rxd")),
  47. MPP_MODE(4,
  48. MPP_FUNCTION(0x0, "gpio", NULL),
  49. MPP_FUNCTION(0x1, "vdd", "cpu-pd")),
  50. MPP_MODE(5,
  51. MPP_FUNCTION(0x0, "gpo", NULL),
  52. MPP_FUNCTION(0x1, "ge0", "txclkout"),
  53. MPP_FUNCTION(0x2, "uart1", "txd"),
  54. MPP_FUNCTION(0x4, "spi1", "sck"),
  55. MPP_FUNCTION(0x5, "audio", "mclk")),
  56. MPP_MODE(6,
  57. MPP_FUNCTION(0x0, "gpio", NULL),
  58. MPP_FUNCTION(0x1, "ge0", "txd0"),
  59. MPP_FUNCTION(0x2, "sata0", "prsnt"),
  60. MPP_FUNCTION(0x4, "tdm", "rst"),
  61. MPP_FUNCTION(0x5, "audio", "sdo")),
  62. MPP_MODE(7,
  63. MPP_FUNCTION(0x0, "gpo", NULL),
  64. MPP_FUNCTION(0x1, "ge0", "txd1"),
  65. MPP_FUNCTION(0x4, "tdm", "dtx"),
  66. MPP_FUNCTION(0x5, "audio", "lrclk")),
  67. MPP_MODE(8,
  68. MPP_FUNCTION(0x0, "gpio", NULL),
  69. MPP_FUNCTION(0x1, "ge0", "txd2"),
  70. MPP_FUNCTION(0x2, "uart0", "rts"),
  71. MPP_FUNCTION(0x4, "tdm", "drx"),
  72. MPP_FUNCTION(0x5, "audio", "bclk")),
  73. MPP_MODE(9,
  74. MPP_FUNCTION(0x0, "gpo", NULL),
  75. MPP_FUNCTION(0x1, "ge0", "txd3"),
  76. MPP_FUNCTION(0x2, "uart1", "txd"),
  77. MPP_FUNCTION(0x3, "sd0", "clk"),
  78. MPP_FUNCTION(0x5, "audio", "spdifo")),
  79. MPP_MODE(10,
  80. MPP_FUNCTION(0x0, "gpio", NULL),
  81. MPP_FUNCTION(0x1, "ge0", "txctl"),
  82. MPP_FUNCTION(0x2, "uart0", "cts"),
  83. MPP_FUNCTION(0x4, "tdm", "fsync"),
  84. MPP_FUNCTION(0x5, "audio", "sdi")),
  85. MPP_MODE(11,
  86. MPP_FUNCTION(0x0, "gpio", NULL),
  87. MPP_FUNCTION(0x1, "ge0", "rxd0"),
  88. MPP_FUNCTION(0x2, "uart1", "rxd"),
  89. MPP_FUNCTION(0x3, "sd0", "cmd"),
  90. MPP_FUNCTION(0x4, "spi0", "cs1"),
  91. MPP_FUNCTION(0x5, "sata1", "prsnt"),
  92. MPP_FUNCTION(0x6, "spi1", "cs1")),
  93. MPP_MODE(12,
  94. MPP_FUNCTION(0x0, "gpio", NULL),
  95. MPP_FUNCTION(0x1, "ge0", "rxd1"),
  96. MPP_FUNCTION(0x2, "i2c1", "sda"),
  97. MPP_FUNCTION(0x3, "sd0", "d0"),
  98. MPP_FUNCTION(0x4, "spi1", "cs0"),
  99. MPP_FUNCTION(0x5, "audio", "spdifi")),
  100. MPP_MODE(13,
  101. MPP_FUNCTION(0x0, "gpio", NULL),
  102. MPP_FUNCTION(0x1, "ge0", "rxd2"),
  103. MPP_FUNCTION(0x2, "i2c1", "sck"),
  104. MPP_FUNCTION(0x3, "sd0", "d1"),
  105. MPP_FUNCTION(0x4, "tdm", "pclk"),
  106. MPP_FUNCTION(0x5, "audio", "rmclk")),
  107. MPP_MODE(14,
  108. MPP_FUNCTION(0x0, "gpio", NULL),
  109. MPP_FUNCTION(0x1, "ge0", "rxd3"),
  110. MPP_FUNCTION(0x2, "pcie", "clkreq0"),
  111. MPP_FUNCTION(0x3, "sd0", "d2"),
  112. MPP_FUNCTION(0x4, "spi1", "mosi"),
  113. MPP_FUNCTION(0x5, "spi0", "cs2")),
  114. MPP_MODE(15,
  115. MPP_FUNCTION(0x0, "gpio", NULL),
  116. MPP_FUNCTION(0x1, "ge0", "rxctl"),
  117. MPP_FUNCTION(0x2, "pcie", "clkreq1"),
  118. MPP_FUNCTION(0x3, "sd0", "d3"),
  119. MPP_FUNCTION(0x4, "spi1", "miso"),
  120. MPP_FUNCTION(0x5, "spi0", "cs3")),
  121. MPP_MODE(16,
  122. MPP_FUNCTION(0x0, "gpio", NULL),
  123. MPP_FUNCTION(0x1, "ge0", "rxclk"),
  124. MPP_FUNCTION(0x2, "uart1", "rxd"),
  125. MPP_FUNCTION(0x4, "tdm", "int"),
  126. MPP_FUNCTION(0x5, "audio", "extclk")),
  127. MPP_MODE(17,
  128. MPP_FUNCTION(0x0, "gpo", NULL),
  129. MPP_FUNCTION(0x1, "ge", "mdc")),
  130. MPP_MODE(18,
  131. MPP_FUNCTION(0x0, "gpio", NULL),
  132. MPP_FUNCTION(0x1, "ge", "mdio")),
  133. MPP_MODE(19,
  134. MPP_FUNCTION(0x0, "gpio", NULL),
  135. MPP_FUNCTION(0x1, "ge0", "txclk"),
  136. MPP_FUNCTION(0x2, "ge1", "txclkout"),
  137. MPP_FUNCTION(0x4, "tdm", "pclk")),
  138. MPP_MODE(20,
  139. MPP_FUNCTION(0x0, "gpo", NULL),
  140. MPP_FUNCTION(0x1, "ge0", "txd4"),
  141. MPP_FUNCTION(0x2, "ge1", "txd0")),
  142. MPP_MODE(21,
  143. MPP_FUNCTION(0x0, "gpo", NULL),
  144. MPP_FUNCTION(0x1, "ge0", "txd5"),
  145. MPP_FUNCTION(0x2, "ge1", "txd1"),
  146. MPP_FUNCTION(0x4, "uart1", "txd")),
  147. MPP_MODE(22,
  148. MPP_FUNCTION(0x0, "gpo", NULL),
  149. MPP_FUNCTION(0x1, "ge0", "txd6"),
  150. MPP_FUNCTION(0x2, "ge1", "txd2"),
  151. MPP_FUNCTION(0x4, "uart0", "rts")),
  152. MPP_MODE(23,
  153. MPP_FUNCTION(0x0, "gpo", NULL),
  154. MPP_FUNCTION(0x1, "ge0", "txd7"),
  155. MPP_FUNCTION(0x2, "ge1", "txd3"),
  156. MPP_FUNCTION(0x4, "spi1", "mosi")),
  157. MPP_MODE(24,
  158. MPP_FUNCTION(0x0, "gpio", NULL),
  159. MPP_FUNCTION(0x1, "ge0", "col"),
  160. MPP_FUNCTION(0x2, "ge1", "txctl"),
  161. MPP_FUNCTION(0x4, "spi1", "cs0")),
  162. MPP_MODE(25,
  163. MPP_FUNCTION(0x0, "gpio", NULL),
  164. MPP_FUNCTION(0x1, "ge0", "rxerr"),
  165. MPP_FUNCTION(0x2, "ge1", "rxd0"),
  166. MPP_FUNCTION(0x4, "uart1", "rxd")),
  167. MPP_MODE(26,
  168. MPP_FUNCTION(0x0, "gpio", NULL),
  169. MPP_FUNCTION(0x1, "ge0", "crs"),
  170. MPP_FUNCTION(0x2, "ge1", "rxd1"),
  171. MPP_FUNCTION(0x4, "spi1", "miso")),
  172. MPP_MODE(27,
  173. MPP_FUNCTION(0x0, "gpio", NULL),
  174. MPP_FUNCTION(0x1, "ge0", "rxd4"),
  175. MPP_FUNCTION(0x2, "ge1", "rxd2"),
  176. MPP_FUNCTION(0x4, "uart0", "cts")),
  177. MPP_MODE(28,
  178. MPP_FUNCTION(0x0, "gpio", NULL),
  179. MPP_FUNCTION(0x1, "ge0", "rxd5"),
  180. MPP_FUNCTION(0x2, "ge1", "rxd3")),
  181. MPP_MODE(29,
  182. MPP_FUNCTION(0x0, "gpio", NULL),
  183. MPP_FUNCTION(0x1, "ge0", "rxd6"),
  184. MPP_FUNCTION(0x2, "ge1", "rxctl"),
  185. MPP_FUNCTION(0x4, "i2c1", "sda")),
  186. MPP_MODE(30,
  187. MPP_FUNCTION(0x0, "gpio", NULL),
  188. MPP_FUNCTION(0x1, "ge0", "rxd7"),
  189. MPP_FUNCTION(0x2, "ge1", "rxclk"),
  190. MPP_FUNCTION(0x4, "i2c1", "sck")),
  191. MPP_MODE(31,
  192. MPP_FUNCTION(0x0, "gpio", NULL),
  193. MPP_FUNCTION(0x3, "tclk", NULL),
  194. MPP_FUNCTION(0x4, "ge0", "txerr")),
  195. MPP_MODE(32,
  196. MPP_FUNCTION(0x0, "gpio", NULL),
  197. MPP_FUNCTION(0x1, "spi0", "cs0")),
  198. MPP_MODE(33,
  199. MPP_FUNCTION(0x0, "gpio", NULL),
  200. MPP_FUNCTION(0x1, "dev", "bootcs"),
  201. MPP_FUNCTION(0x2, "spi0", "cs0")),
  202. MPP_MODE(34,
  203. MPP_FUNCTION(0x0, "gpo", NULL),
  204. MPP_FUNCTION(0x1, "dev", "we0"),
  205. MPP_FUNCTION(0x2, "spi0", "mosi")),
  206. MPP_MODE(35,
  207. MPP_FUNCTION(0x0, "gpo", NULL),
  208. MPP_FUNCTION(0x1, "dev", "oe"),
  209. MPP_FUNCTION(0x2, "spi0", "sck")),
  210. MPP_MODE(36,
  211. MPP_FUNCTION(0x0, "gpo", NULL),
  212. MPP_FUNCTION(0x1, "dev", "a1"),
  213. MPP_FUNCTION(0x2, "spi0", "miso")),
  214. MPP_MODE(37,
  215. MPP_FUNCTION(0x0, "gpo", NULL),
  216. MPP_FUNCTION(0x1, "dev", "a0"),
  217. MPP_FUNCTION(0x2, "sata0", "prsnt")),
  218. MPP_MODE(38,
  219. MPP_FUNCTION(0x0, "gpio", NULL),
  220. MPP_FUNCTION(0x1, "dev", "ready"),
  221. MPP_FUNCTION(0x2, "uart1", "cts"),
  222. MPP_FUNCTION(0x3, "uart0", "cts")),
  223. MPP_MODE(39,
  224. MPP_FUNCTION(0x0, "gpo", NULL),
  225. MPP_FUNCTION(0x1, "dev", "ad0"),
  226. MPP_FUNCTION(0x2, "audio", "spdifo")),
  227. MPP_MODE(40,
  228. MPP_FUNCTION(0x0, "gpio", NULL),
  229. MPP_FUNCTION(0x1, "dev", "ad1"),
  230. MPP_FUNCTION(0x2, "uart1", "rts"),
  231. MPP_FUNCTION(0x3, "uart0", "rts")),
  232. MPP_MODE(41,
  233. MPP_FUNCTION(0x0, "gpio", NULL),
  234. MPP_FUNCTION(0x1, "dev", "ad2"),
  235. MPP_FUNCTION(0x2, "uart1", "rxd")),
  236. MPP_MODE(42,
  237. MPP_FUNCTION(0x0, "gpo", NULL),
  238. MPP_FUNCTION(0x1, "dev", "ad3"),
  239. MPP_FUNCTION(0x2, "uart1", "txd")),
  240. MPP_MODE(43,
  241. MPP_FUNCTION(0x0, "gpo", NULL),
  242. MPP_FUNCTION(0x1, "dev", "ad4"),
  243. MPP_FUNCTION(0x2, "audio", "bclk")),
  244. MPP_MODE(44,
  245. MPP_FUNCTION(0x0, "gpo", NULL),
  246. MPP_FUNCTION(0x1, "dev", "ad5"),
  247. MPP_FUNCTION(0x2, "audio", "mclk")),
  248. MPP_MODE(45,
  249. MPP_FUNCTION(0x0, "gpo", NULL),
  250. MPP_FUNCTION(0x1, "dev", "ad6"),
  251. MPP_FUNCTION(0x2, "audio", "lrclk")),
  252. MPP_MODE(46,
  253. MPP_FUNCTION(0x0, "gpo", NULL),
  254. MPP_FUNCTION(0x1, "dev", "ad7"),
  255. MPP_FUNCTION(0x2, "audio", "sdo")),
  256. MPP_MODE(47,
  257. MPP_FUNCTION(0x0, "gpo", NULL),
  258. MPP_FUNCTION(0x1, "dev", "ad8"),
  259. MPP_FUNCTION(0x3, "sd0", "clk"),
  260. MPP_FUNCTION(0x5, "audio", "spdifo")),
  261. MPP_MODE(48,
  262. MPP_FUNCTION(0x0, "gpio", NULL),
  263. MPP_FUNCTION(0x1, "dev", "ad9"),
  264. MPP_FUNCTION(0x2, "uart0", "rts"),
  265. MPP_FUNCTION(0x3, "sd0", "cmd"),
  266. MPP_FUNCTION(0x4, "sata1", "prsnt"),
  267. MPP_FUNCTION(0x5, "spi0", "cs1")),
  268. MPP_MODE(49,
  269. MPP_FUNCTION(0x0, "gpio", NULL),
  270. MPP_FUNCTION(0x1, "dev", "ad10"),
  271. MPP_FUNCTION(0x2, "pcie", "clkreq1"),
  272. MPP_FUNCTION(0x3, "sd0", "d0"),
  273. MPP_FUNCTION(0x4, "spi1", "cs0"),
  274. MPP_FUNCTION(0x5, "audio", "spdifi")),
  275. MPP_MODE(50,
  276. MPP_FUNCTION(0x0, "gpio", NULL),
  277. MPP_FUNCTION(0x1, "dev", "ad11"),
  278. MPP_FUNCTION(0x2, "uart0", "cts"),
  279. MPP_FUNCTION(0x3, "sd0", "d1"),
  280. MPP_FUNCTION(0x4, "spi1", "miso"),
  281. MPP_FUNCTION(0x5, "audio", "rmclk")),
  282. MPP_MODE(51,
  283. MPP_FUNCTION(0x0, "gpio", NULL),
  284. MPP_FUNCTION(0x1, "dev", "ad12"),
  285. MPP_FUNCTION(0x2, "i2c1", "sda"),
  286. MPP_FUNCTION(0x3, "sd0", "d2"),
  287. MPP_FUNCTION(0x4, "spi1", "mosi")),
  288. MPP_MODE(52,
  289. MPP_FUNCTION(0x0, "gpio", NULL),
  290. MPP_FUNCTION(0x1, "dev", "ad13"),
  291. MPP_FUNCTION(0x2, "i2c1", "sck"),
  292. MPP_FUNCTION(0x3, "sd0", "d3"),
  293. MPP_FUNCTION(0x4, "spi1", "sck")),
  294. MPP_MODE(53,
  295. MPP_FUNCTION(0x0, "gpio", NULL),
  296. MPP_FUNCTION(0x1, "dev", "ad14"),
  297. MPP_FUNCTION(0x2, "sd0", "clk"),
  298. MPP_FUNCTION(0x3, "tdm", "pclk"),
  299. MPP_FUNCTION(0x4, "spi0", "cs2"),
  300. MPP_FUNCTION(0x5, "pcie", "clkreq1")),
  301. MPP_MODE(54,
  302. MPP_FUNCTION(0x0, "gpo", NULL),
  303. MPP_FUNCTION(0x1, "dev", "ad15"),
  304. MPP_FUNCTION(0x3, "tdm", "dtx")),
  305. MPP_MODE(55,
  306. MPP_FUNCTION(0x0, "gpio", NULL),
  307. MPP_FUNCTION(0x1, "dev", "cs1"),
  308. MPP_FUNCTION(0x2, "uart1", "txd"),
  309. MPP_FUNCTION(0x3, "tdm", "rst"),
  310. MPP_FUNCTION(0x4, "sata1", "prsnt"),
  311. MPP_FUNCTION(0x5, "sata0", "prsnt")),
  312. MPP_MODE(56,
  313. MPP_FUNCTION(0x0, "gpio", NULL),
  314. MPP_FUNCTION(0x1, "dev", "cs2"),
  315. MPP_FUNCTION(0x2, "uart1", "cts"),
  316. MPP_FUNCTION(0x3, "uart0", "cts"),
  317. MPP_FUNCTION(0x4, "spi0", "cs3"),
  318. MPP_FUNCTION(0x5, "pcie", "clkreq0"),
  319. MPP_FUNCTION(0x6, "spi1", "cs1")),
  320. MPP_MODE(57,
  321. MPP_FUNCTION(0x0, "gpio", NULL),
  322. MPP_FUNCTION(0x1, "dev", "cs3"),
  323. MPP_FUNCTION(0x2, "uart1", "rxd"),
  324. MPP_FUNCTION(0x3, "tdm", "fsync"),
  325. MPP_FUNCTION(0x4, "sata0", "prsnt"),
  326. MPP_FUNCTION(0x5, "audio", "sdo")),
  327. MPP_MODE(58,
  328. MPP_FUNCTION(0x0, "gpio", NULL),
  329. MPP_FUNCTION(0x1, "dev", "cs0"),
  330. MPP_FUNCTION(0x2, "uart1", "rts"),
  331. MPP_FUNCTION(0x3, "tdm", "int"),
  332. MPP_FUNCTION(0x5, "audio", "extclk"),
  333. MPP_FUNCTION(0x6, "uart0", "rts")),
  334. MPP_MODE(59,
  335. MPP_FUNCTION(0x0, "gpo", NULL),
  336. MPP_FUNCTION(0x1, "dev", "ale0"),
  337. MPP_FUNCTION(0x2, "uart1", "rts"),
  338. MPP_FUNCTION(0x3, "uart0", "rts"),
  339. MPP_FUNCTION(0x5, "audio", "bclk")),
  340. MPP_MODE(60,
  341. MPP_FUNCTION(0x0, "gpio", NULL),
  342. MPP_FUNCTION(0x1, "dev", "ale1"),
  343. MPP_FUNCTION(0x2, "uart1", "rxd"),
  344. MPP_FUNCTION(0x3, "sata0", "prsnt"),
  345. MPP_FUNCTION(0x4, "pcie", "rstout"),
  346. MPP_FUNCTION(0x5, "audio", "sdi")),
  347. MPP_MODE(61,
  348. MPP_FUNCTION(0x0, "gpo", NULL),
  349. MPP_FUNCTION(0x1, "dev", "we1"),
  350. MPP_FUNCTION(0x2, "uart1", "txd"),
  351. MPP_FUNCTION(0x5, "audio", "lrclk")),
  352. MPP_MODE(62,
  353. MPP_FUNCTION(0x0, "gpio", NULL),
  354. MPP_FUNCTION(0x1, "dev", "a2"),
  355. MPP_FUNCTION(0x2, "uart1", "cts"),
  356. MPP_FUNCTION(0x3, "tdm", "drx"),
  357. MPP_FUNCTION(0x4, "pcie", "clkreq0"),
  358. MPP_FUNCTION(0x5, "audio", "mclk"),
  359. MPP_FUNCTION(0x6, "uart0", "cts")),
  360. MPP_MODE(63,
  361. MPP_FUNCTION(0x0, "gpio", NULL),
  362. MPP_FUNCTION(0x1, "spi0", "sck"),
  363. MPP_FUNCTION(0x2, "tclk", NULL)),
  364. MPP_MODE(64,
  365. MPP_FUNCTION(0x0, "gpio", NULL),
  366. MPP_FUNCTION(0x1, "spi0", "miso"),
  367. MPP_FUNCTION(0x2, "spi0", "cs1")),
  368. MPP_MODE(65,
  369. MPP_FUNCTION(0x0, "gpio", NULL),
  370. MPP_FUNCTION(0x1, "spi0", "mosi"),
  371. MPP_FUNCTION(0x2, "spi0", "cs2")),
  372. };
  373. static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
  374. static const struct of_device_id armada_370_pinctrl_of_match[] = {
  375. { .compatible = "marvell,mv88f6710-pinctrl" },
  376. { },
  377. };
  378. static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
  379. MPP_FUNC_CTRL(0, 65, NULL, armada_370_mpp_ctrl),
  380. };
  381. static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
  382. MPP_GPIO_RANGE(0, 0, 0, 32),
  383. MPP_GPIO_RANGE(1, 32, 32, 32),
  384. MPP_GPIO_RANGE(2, 64, 64, 2),
  385. };
  386. static int armada_370_pinctrl_probe(struct platform_device *pdev)
  387. {
  388. struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
  389. struct resource *res;
  390. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  391. mpp_base = devm_ioremap_resource(&pdev->dev, res);
  392. if (IS_ERR(mpp_base))
  393. return PTR_ERR(mpp_base);
  394. soc->variant = 0; /* no variants for Armada 370 */
  395. soc->controls = mv88f6710_mpp_controls;
  396. soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
  397. soc->modes = mv88f6710_mpp_modes;
  398. soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
  399. soc->gpioranges = mv88f6710_mpp_gpio_ranges;
  400. soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
  401. pdev->dev.platform_data = soc;
  402. return mvebu_pinctrl_probe(pdev);
  403. }
  404. static int armada_370_pinctrl_remove(struct platform_device *pdev)
  405. {
  406. return mvebu_pinctrl_remove(pdev);
  407. }
  408. static struct platform_driver armada_370_pinctrl_driver = {
  409. .driver = {
  410. .name = "armada-370-pinctrl",
  411. .of_match_table = armada_370_pinctrl_of_match,
  412. },
  413. .probe = armada_370_pinctrl_probe,
  414. .remove = armada_370_pinctrl_remove,
  415. };
  416. module_platform_driver(armada_370_pinctrl_driver);
  417. MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
  418. MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
  419. MODULE_LICENSE("GPL v2");