fw.c 27 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2014 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../pci.h"
  27. #include "../base.h"
  28. #include "../core.h"
  29. #include "reg.h"
  30. #include "def.h"
  31. #include "fw.h"
  32. #include "dm.h"
  33. static void _rtl92ee_enable_fw_download(struct ieee80211_hw *hw, bool enable)
  34. {
  35. struct rtl_priv *rtlpriv = rtl_priv(hw);
  36. u8 tmp;
  37. if (enable) {
  38. rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x05);
  39. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL + 2);
  40. rtl_write_byte(rtlpriv, REG_MCUFWDL + 2, tmp & 0xf7);
  41. } else {
  42. tmp = rtl_read_byte(rtlpriv, REG_MCUFWDL);
  43. rtl_write_byte(rtlpriv, REG_MCUFWDL, tmp & 0xfe);
  44. }
  45. }
  46. static void _rtl92ee_fw_block_write(struct ieee80211_hw *hw,
  47. const u8 *buffer, u32 size)
  48. {
  49. struct rtl_priv *rtlpriv = rtl_priv(hw);
  50. u32 blocksize = sizeof(u32);
  51. u8 *bufferptr = (u8 *)buffer;
  52. u32 *pu4byteptr = (u32 *)buffer;
  53. u32 i, offset, blockcount, remainsize;
  54. blockcount = size / blocksize;
  55. remainsize = size % blocksize;
  56. for (i = 0; i < blockcount; i++) {
  57. offset = i * blocksize;
  58. rtl_write_dword(rtlpriv, (FW_8192C_START_ADDRESS + offset),
  59. *(pu4byteptr + i));
  60. }
  61. if (remainsize) {
  62. offset = blockcount * blocksize;
  63. bufferptr += offset;
  64. for (i = 0; i < remainsize; i++) {
  65. rtl_write_byte(rtlpriv,
  66. (FW_8192C_START_ADDRESS + offset + i),
  67. *(bufferptr + i));
  68. }
  69. }
  70. }
  71. static void _rtl92ee_fw_page_write(struct ieee80211_hw *hw, u32 page,
  72. const u8 *buffer, u32 size)
  73. {
  74. struct rtl_priv *rtlpriv = rtl_priv(hw);
  75. u8 value8;
  76. u8 u8page = (u8)(page & 0x07);
  77. value8 = (rtl_read_byte(rtlpriv, REG_MCUFWDL + 2) & 0xF8) | u8page;
  78. rtl_write_byte(rtlpriv, (REG_MCUFWDL + 2), value8);
  79. _rtl92ee_fw_block_write(hw, buffer, size);
  80. }
  81. static void _rtl92ee_fill_dummy(u8 *pfwbuf, u32 *pfwlen)
  82. {
  83. u32 fwlen = *pfwlen;
  84. u8 remain = (u8)(fwlen % 4);
  85. remain = (remain == 0) ? 0 : (4 - remain);
  86. while (remain > 0) {
  87. pfwbuf[fwlen] = 0;
  88. fwlen++;
  89. remain--;
  90. }
  91. *pfwlen = fwlen;
  92. }
  93. static void _rtl92ee_write_fw(struct ieee80211_hw *hw,
  94. enum version_8192e version,
  95. u8 *buffer, u32 size)
  96. {
  97. struct rtl_priv *rtlpriv = rtl_priv(hw);
  98. u8 *bufferptr = (u8 *)buffer;
  99. u32 pagenums, remainsize;
  100. u32 page, offset;
  101. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "FW size is %d bytes,\n", size);
  102. _rtl92ee_fill_dummy(bufferptr, &size);
  103. pagenums = size / FW_8192C_PAGE_SIZE;
  104. remainsize = size % FW_8192C_PAGE_SIZE;
  105. if (pagenums > 8) {
  106. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  107. "Page numbers should not greater then 8\n");
  108. }
  109. for (page = 0; page < pagenums; page++) {
  110. offset = page * FW_8192C_PAGE_SIZE;
  111. _rtl92ee_fw_page_write(hw, page, (bufferptr + offset),
  112. FW_8192C_PAGE_SIZE);
  113. udelay(2);
  114. }
  115. if (remainsize) {
  116. offset = pagenums * FW_8192C_PAGE_SIZE;
  117. page = pagenums;
  118. _rtl92ee_fw_page_write(hw, page, (bufferptr + offset),
  119. remainsize);
  120. }
  121. }
  122. static int _rtl92ee_fw_free_to_go(struct ieee80211_hw *hw)
  123. {
  124. struct rtl_priv *rtlpriv = rtl_priv(hw);
  125. int err = -EIO;
  126. u32 counter = 0;
  127. u32 value32;
  128. do {
  129. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  130. } while ((counter++ < FW_8192C_POLLING_TIMEOUT_COUNT) &&
  131. (!(value32 & FWDL_CHKSUM_RPT)));
  132. if (counter >= FW_8192C_POLLING_TIMEOUT_COUNT) {
  133. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  134. "chksum report faill ! REG_MCUFWDL:0x%08x .\n",
  135. value32);
  136. goto exit;
  137. }
  138. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  139. "Checksum report OK ! REG_MCUFWDL:0x%08x .\n", value32);
  140. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  141. value32 |= MCUFWDL_RDY;
  142. value32 &= ~WINTINI_RDY;
  143. rtl_write_dword(rtlpriv, REG_MCUFWDL, value32);
  144. rtl92ee_firmware_selfreset(hw);
  145. counter = 0;
  146. do {
  147. value32 = rtl_read_dword(rtlpriv, REG_MCUFWDL);
  148. if (value32 & WINTINI_RDY) {
  149. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD ,
  150. "Polling FW ready success!! REG_MCUFWDL:0x%08x. count = %d\n",
  151. value32, counter);
  152. err = 0;
  153. goto exit;
  154. }
  155. udelay(FW_8192C_POLLING_DELAY*10);
  156. } while (counter++ < FW_8192C_POLLING_TIMEOUT_COUNT);
  157. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  158. "Polling FW ready fail!! REG_MCUFWDL:0x%08x. count = %d\n",
  159. value32, counter);
  160. exit:
  161. return err;
  162. }
  163. int rtl92ee_download_fw(struct ieee80211_hw *hw, bool buse_wake_on_wlan_fw)
  164. {
  165. struct rtl_priv *rtlpriv = rtl_priv(hw);
  166. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  167. struct rtl92c_firmware_header *pfwheader;
  168. u8 *pfwdata;
  169. u32 fwsize;
  170. int err;
  171. enum version_8192e version = rtlhal->version;
  172. if (!rtlhal->pfirmware)
  173. return 1;
  174. pfwheader = (struct rtl92c_firmware_header *)rtlhal->pfirmware;
  175. rtlhal->fw_version = pfwheader->version;
  176. rtlhal->fw_subversion = pfwheader->subversion;
  177. pfwdata = (u8 *)rtlhal->pfirmware;
  178. fwsize = rtlhal->fwsize;
  179. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  180. "normal Firmware SIZE %d\n" , fwsize);
  181. if (IS_FW_HEADER_EXIST(pfwheader)) {
  182. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  183. "Firmware Version(%d), Signature(%#x),Size(%d)\n",
  184. pfwheader->version, pfwheader->signature,
  185. (int)sizeof(struct rtl92c_firmware_header));
  186. pfwdata = pfwdata + sizeof(struct rtl92c_firmware_header);
  187. fwsize = fwsize - sizeof(struct rtl92c_firmware_header);
  188. } else {
  189. RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG,
  190. "Firmware no Header, Signature(%#x)\n",
  191. pfwheader->signature);
  192. }
  193. if (rtlhal->mac_func_enable) {
  194. if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) {
  195. rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
  196. rtl92ee_firmware_selfreset(hw);
  197. }
  198. }
  199. _rtl92ee_enable_fw_download(hw, true);
  200. _rtl92ee_write_fw(hw, version, pfwdata, fwsize);
  201. _rtl92ee_enable_fw_download(hw, false);
  202. err = _rtl92ee_fw_free_to_go(hw);
  203. if (err) {
  204. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  205. "Firmware is not ready to run!\n");
  206. } else {
  207. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD ,
  208. "Firmware is ready to run!\n");
  209. }
  210. return 0;
  211. }
  212. static bool _rtl92ee_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
  213. {
  214. struct rtl_priv *rtlpriv = rtl_priv(hw);
  215. u8 val_hmetfr;
  216. bool result = false;
  217. val_hmetfr = rtl_read_byte(rtlpriv, REG_HMETFR);
  218. if (((val_hmetfr >> boxnum) & BIT(0)) == 0)
  219. result = true;
  220. return result;
  221. }
  222. static void _rtl92ee_fill_h2c_command(struct ieee80211_hw *hw, u8 element_id,
  223. u32 cmd_len, u8 *cmdbuffer)
  224. {
  225. struct rtl_priv *rtlpriv = rtl_priv(hw);
  226. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  227. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  228. u8 boxnum;
  229. u16 box_reg = 0, box_extreg = 0;
  230. u8 u1b_tmp;
  231. bool isfw_read = false;
  232. u8 buf_index = 0;
  233. bool bwrite_sucess = false;
  234. u8 wait_h2c_limmit = 100;
  235. u8 boxcontent[4], boxextcontent[4];
  236. u32 h2c_waitcounter = 0;
  237. unsigned long flag;
  238. u8 idx;
  239. if (ppsc->dot11_psmode != EACTIVE ||
  240. ppsc->inactive_pwrstate == ERFOFF) {
  241. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  242. "FillH2CCommand8192E(): Return because RF is off!!!\n");
  243. return;
  244. }
  245. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD , "come in\n");
  246. /* 1. Prevent race condition in setting H2C cmd.
  247. * (copy from MgntActSet_RF_State().)
  248. */
  249. while (true) {
  250. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  251. if (rtlhal->h2c_setinprogress) {
  252. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  253. "H2C set in progress! Wait to set..element_id(%d).\n",
  254. element_id);
  255. while (rtlhal->h2c_setinprogress) {
  256. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
  257. flag);
  258. h2c_waitcounter++;
  259. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  260. "Wait 100 us (%d times)...\n",
  261. h2c_waitcounter);
  262. udelay(100);
  263. if (h2c_waitcounter > 1000)
  264. return;
  265. spin_lock_irqsave(&rtlpriv->locks.h2c_lock,
  266. flag);
  267. }
  268. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  269. } else {
  270. rtlhal->h2c_setinprogress = true;
  271. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  272. break;
  273. }
  274. }
  275. while (!bwrite_sucess) {
  276. /* 2. Find the last BOX number which has been writen. */
  277. boxnum = rtlhal->last_hmeboxnum;
  278. switch (boxnum) {
  279. case 0:
  280. box_reg = REG_HMEBOX_0;
  281. box_extreg = REG_HMEBOX_EXT_0;
  282. break;
  283. case 1:
  284. box_reg = REG_HMEBOX_1;
  285. box_extreg = REG_HMEBOX_EXT_1;
  286. break;
  287. case 2:
  288. box_reg = REG_HMEBOX_2;
  289. box_extreg = REG_HMEBOX_EXT_2;
  290. break;
  291. case 3:
  292. box_reg = REG_HMEBOX_3;
  293. box_extreg = REG_HMEBOX_EXT_3;
  294. break;
  295. default:
  296. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  297. "switch case not process\n");
  298. break;
  299. }
  300. /* 3. Check if the box content is empty. */
  301. isfw_read = false;
  302. u1b_tmp = rtl_read_byte(rtlpriv, REG_CR);
  303. if (u1b_tmp != 0xea) {
  304. isfw_read = true;
  305. } else {
  306. if (rtl_read_byte(rtlpriv, REG_TXDMA_STATUS) == 0xea ||
  307. rtl_read_byte(rtlpriv, REG_TXPKT_EMPTY) == 0xea)
  308. rtl_write_byte(rtlpriv, REG_SYS_CFG1 + 3, 0xff);
  309. }
  310. if (isfw_read) {
  311. wait_h2c_limmit = 100;
  312. isfw_read = _rtl92ee_check_fw_read_last_h2c(hw, boxnum);
  313. while (!isfw_read) {
  314. wait_h2c_limmit--;
  315. if (wait_h2c_limmit == 0) {
  316. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  317. "Waiting too long for FW read clear HMEBox(%d)!!!\n",
  318. boxnum);
  319. break;
  320. }
  321. udelay(10);
  322. isfw_read =
  323. _rtl92ee_check_fw_read_last_h2c(hw, boxnum);
  324. u1b_tmp = rtl_read_byte(rtlpriv, 0x130);
  325. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  326. "Waiting for FW read clear HMEBox(%d)!!! 0x130 = %2x\n",
  327. boxnum, u1b_tmp);
  328. }
  329. }
  330. /* If Fw has not read the last
  331. * H2C cmd, break and give up this H2C.
  332. */
  333. if (!isfw_read) {
  334. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  335. "Write H2C reg BOX[%d] fail,Fw don't read.\n",
  336. boxnum);
  337. break;
  338. }
  339. /* 4. Fill the H2C cmd into box */
  340. memset(boxcontent, 0, sizeof(boxcontent));
  341. memset(boxextcontent, 0, sizeof(boxextcontent));
  342. boxcontent[0] = element_id;
  343. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  344. "Write element_id box_reg(%4x) = %2x\n",
  345. box_reg, element_id);
  346. switch (cmd_len) {
  347. case 1:
  348. case 2:
  349. case 3:
  350. /*boxcontent[0] &= ~(BIT(7));*/
  351. memcpy((u8 *)(boxcontent) + 1,
  352. cmdbuffer + buf_index, cmd_len);
  353. for (idx = 0; idx < 4; idx++) {
  354. rtl_write_byte(rtlpriv, box_reg + idx,
  355. boxcontent[idx]);
  356. }
  357. break;
  358. case 4:
  359. case 5:
  360. case 6:
  361. case 7:
  362. /*boxcontent[0] |= (BIT(7));*/
  363. memcpy((u8 *)(boxextcontent),
  364. cmdbuffer + buf_index+3, cmd_len-3);
  365. memcpy((u8 *)(boxcontent) + 1,
  366. cmdbuffer + buf_index, 3);
  367. for (idx = 0; idx < 4; idx++) {
  368. rtl_write_byte(rtlpriv, box_extreg + idx,
  369. boxextcontent[idx]);
  370. }
  371. for (idx = 0; idx < 4; idx++) {
  372. rtl_write_byte(rtlpriv, box_reg + idx,
  373. boxcontent[idx]);
  374. }
  375. break;
  376. default:
  377. RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  378. "switch case not process\n");
  379. break;
  380. }
  381. bwrite_sucess = true;
  382. rtlhal->last_hmeboxnum = boxnum + 1;
  383. if (rtlhal->last_hmeboxnum == 4)
  384. rtlhal->last_hmeboxnum = 0;
  385. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD ,
  386. "pHalData->last_hmeboxnum = %d\n",
  387. rtlhal->last_hmeboxnum);
  388. }
  389. spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
  390. rtlhal->h2c_setinprogress = false;
  391. spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
  392. RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD , "go out\n");
  393. }
  394. void rtl92ee_fill_h2c_cmd(struct ieee80211_hw *hw,
  395. u8 element_id, u32 cmd_len, u8 *cmdbuffer)
  396. {
  397. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  398. u32 tmp_cmdbuf[2];
  399. if (!rtlhal->fw_ready) {
  400. RT_ASSERT(false,
  401. "return H2C cmd because of Fw download fail!!!\n");
  402. return;
  403. }
  404. memset(tmp_cmdbuf, 0, 8);
  405. memcpy(tmp_cmdbuf, cmdbuffer, cmd_len);
  406. _rtl92ee_fill_h2c_command(hw, element_id, cmd_len, (u8 *)&tmp_cmdbuf);
  407. }
  408. void rtl92ee_firmware_selfreset(struct ieee80211_hw *hw)
  409. {
  410. u8 u1b_tmp;
  411. struct rtl_priv *rtlpriv = rtl_priv(hw);
  412. u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
  413. rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
  414. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  415. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
  416. udelay(50);
  417. u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
  418. rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
  419. u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
  420. rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp | BIT(2)));
  421. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD ,
  422. " _8051Reset92E(): 8051 reset success .\n");
  423. }
  424. void rtl92ee_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
  425. {
  426. struct rtl_priv *rtlpriv = rtl_priv(hw);
  427. u8 u1_h2c_set_pwrmode[H2C_92E_PWEMODE_LENGTH] = { 0 };
  428. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  429. u8 rlbm , power_state = 0;
  430. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD , "FW LPS mode = %d\n", mode);
  431. SET_H2CCMD_PWRMODE_PARM_MODE(u1_h2c_set_pwrmode, ((mode) ? 1 : 0));
  432. rlbm = 0;/*YJ,temp,120316. FW now not support RLBM=2.*/
  433. SET_H2CCMD_PWRMODE_PARM_RLBM(u1_h2c_set_pwrmode, rlbm);
  434. SET_H2CCMD_PWRMODE_PARM_SMART_PS(u1_h2c_set_pwrmode,
  435. (rtlpriv->mac80211.p2p) ?
  436. ppsc->smart_ps : 1);
  437. SET_H2CCMD_PWRMODE_PARM_AWAKE_INTERVAL(u1_h2c_set_pwrmode,
  438. ppsc->reg_max_lps_awakeintvl);
  439. SET_H2CCMD_PWRMODE_PARM_ALL_QUEUE_UAPSD(u1_h2c_set_pwrmode, 0);
  440. if (mode == FW_PS_ACTIVE_MODE)
  441. power_state |= FW_PWR_STATE_ACTIVE;
  442. else
  443. power_state |= FW_PWR_STATE_RF_OFF;
  444. SET_H2CCMD_PWRMODE_PARM_PWR_STATE(u1_h2c_set_pwrmode, power_state);
  445. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_DMESG,
  446. "rtl92c_set_fw_pwrmode(): u1_h2c_set_pwrmode\n",
  447. u1_h2c_set_pwrmode, H2C_92E_PWEMODE_LENGTH);
  448. rtl92ee_fill_h2c_cmd(hw, H2C_92E_SETPWRMODE, H2C_92E_PWEMODE_LENGTH,
  449. u1_h2c_set_pwrmode);
  450. }
  451. void rtl92ee_set_fw_media_status_rpt_cmd(struct ieee80211_hw *hw, u8 mstatus)
  452. {
  453. u8 parm[3] = { 0 , 0 , 0 };
  454. /* parm[0]: bit0=0-->Disconnect, bit0=1-->Connect
  455. * bit1=0-->update Media Status to MACID
  456. * bit1=1-->update Media Status from MACID to MACID_End
  457. * parm[1]: MACID, if this is INFRA_STA, MacID = 0
  458. * parm[2]: MACID_End
  459. */
  460. SET_H2CCMD_MSRRPT_PARM_OPMODE(parm, mstatus);
  461. SET_H2CCMD_MSRRPT_PARM_MACID_IND(parm, 0);
  462. rtl92ee_fill_h2c_cmd(hw, H2C_92E_MSRRPT, 3, parm);
  463. }
  464. #define BEACON_PG 0 /* ->1 */
  465. #define PSPOLL_PG 2
  466. #define NULL_PG 3
  467. #define PROBERSP_PG 4 /* ->5 */
  468. #define TOTAL_RESERVED_PKT_LEN 768
  469. static u8 reserved_page_packet[TOTAL_RESERVED_PKT_LEN] = {
  470. /* page 0 beacon */
  471. 0x80, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF,
  472. 0xFF, 0xFF, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  473. 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x20, 0x00,
  474. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  475. 0x64, 0x00, 0x10, 0x04, 0x00, 0x05, 0x54, 0x65,
  476. 0x73, 0x74, 0x32, 0x01, 0x08, 0x82, 0x84, 0x0B,
  477. 0x16, 0x24, 0x30, 0x48, 0x6C, 0x03, 0x01, 0x06,
  478. 0x06, 0x02, 0x00, 0x00, 0x2A, 0x01, 0x02, 0x32,
  479. 0x04, 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C,
  480. 0x09, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
  481. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  482. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  483. 0x00, 0x3D, 0x00, 0xDD, 0x07, 0x00, 0xE0, 0x4C,
  484. 0x02, 0x02, 0x00, 0x00, 0xDD, 0x18, 0x00, 0x50,
  485. 0xF2, 0x01, 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04,
  486. 0x01, 0x00, 0x00, 0x50, 0xF2, 0x04, 0x01, 0x00,
  487. /* page 1 beacon */
  488. 0x00, 0x50, 0xF2, 0x02, 0x00, 0x00, 0x00, 0x00,
  489. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  490. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  491. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  492. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  493. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  494. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  495. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  496. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  497. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  498. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  499. 0x10, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  500. 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00,
  501. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  502. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  503. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  504. /* page 2 ps-poll */
  505. 0xA4, 0x10, 0x01, 0xC0, 0xEC, 0x1A, 0x59, 0x0B,
  506. 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  507. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  508. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  509. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  510. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  511. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  512. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  513. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  514. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  515. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  516. 0x18, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  517. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  518. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  519. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  520. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  521. /* page 3 null */
  522. 0x48, 0x01, 0x00, 0x00, 0xEC, 0x1A, 0x59, 0x0B,
  523. 0xAD, 0xD4, 0x00, 0xE0, 0x4C, 0x02, 0xB1, 0x78,
  524. 0xEC, 0x1A, 0x59, 0x0B, 0xAD, 0xD4, 0x00, 0x00,
  525. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  526. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  527. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  528. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  529. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  530. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  531. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  532. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  533. 0x72, 0x00, 0x28, 0x8C, 0x00, 0x12, 0x00, 0x00,
  534. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
  535. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  536. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  537. 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  538. /* page 4 probe_resp */
  539. 0x50, 0x00, 0x00, 0x00, 0x00, 0x40, 0x10, 0x10,
  540. 0x00, 0x03, 0x00, 0xE0, 0x4C, 0x76, 0x00, 0x42,
  541. 0x00, 0x40, 0x10, 0x10, 0x00, 0x03, 0x00, 0x00,
  542. 0x9E, 0x46, 0x15, 0x32, 0x27, 0xF2, 0x2D, 0x00,
  543. 0x64, 0x00, 0x00, 0x04, 0x00, 0x0C, 0x6C, 0x69,
  544. 0x6E, 0x6B, 0x73, 0x79, 0x73, 0x5F, 0x77, 0x6C,
  545. 0x61, 0x6E, 0x01, 0x04, 0x82, 0x84, 0x8B, 0x96,
  546. 0x03, 0x01, 0x01, 0x06, 0x02, 0x00, 0x00, 0x2A,
  547. 0x01, 0x00, 0x32, 0x08, 0x24, 0x30, 0x48, 0x6C,
  548. 0x0C, 0x12, 0x18, 0x60, 0x2D, 0x1A, 0x6C, 0x18,
  549. 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  550. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  551. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  552. 0x3D, 0x00, 0xDD, 0x06, 0x00, 0xE0, 0x4C, 0x02,
  553. 0x01, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  554. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  555. /* page 5 probe_resp */
  556. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  557. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  558. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  559. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  560. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  561. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  562. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  563. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  564. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  565. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  566. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  567. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  568. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  569. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  570. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  571. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  572. };
  573. void rtl92ee_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
  574. {
  575. struct rtl_priv *rtlpriv = rtl_priv(hw);
  576. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  577. struct sk_buff *skb = NULL;
  578. u32 totalpacketlen;
  579. u8 u1rsvdpageloc[5] = { 0 };
  580. bool b_dlok = false;
  581. u8 *beacon;
  582. u8 *p_pspoll;
  583. u8 *nullfunc;
  584. u8 *p_probersp;
  585. /*---------------------------------------------------------
  586. * (1) beacon
  587. *---------------------------------------------------------
  588. */
  589. beacon = &reserved_page_packet[BEACON_PG * 128];
  590. SET_80211_HDR_ADDRESS2(beacon, mac->mac_addr);
  591. SET_80211_HDR_ADDRESS3(beacon, mac->bssid);
  592. /*-------------------------------------------------------
  593. * (2) ps-poll
  594. *--------------------------------------------------------
  595. */
  596. p_pspoll = &reserved_page_packet[PSPOLL_PG * 128];
  597. SET_80211_PS_POLL_AID(p_pspoll, (mac->assoc_id | 0xc000));
  598. SET_80211_PS_POLL_BSSID(p_pspoll, mac->bssid);
  599. SET_80211_PS_POLL_TA(p_pspoll, mac->mac_addr);
  600. SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(u1rsvdpageloc, PSPOLL_PG);
  601. /*--------------------------------------------------------
  602. * (3) null data
  603. *---------------------------------------------------------
  604. */
  605. nullfunc = &reserved_page_packet[NULL_PG * 128];
  606. SET_80211_HDR_ADDRESS1(nullfunc, mac->bssid);
  607. SET_80211_HDR_ADDRESS2(nullfunc, mac->mac_addr);
  608. SET_80211_HDR_ADDRESS3(nullfunc, mac->bssid);
  609. SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(u1rsvdpageloc, NULL_PG);
  610. /*---------------------------------------------------------
  611. * (4) probe response
  612. *----------------------------------------------------------
  613. */
  614. p_probersp = &reserved_page_packet[PROBERSP_PG * 128];
  615. SET_80211_HDR_ADDRESS1(p_probersp, mac->bssid);
  616. SET_80211_HDR_ADDRESS2(p_probersp, mac->mac_addr);
  617. SET_80211_HDR_ADDRESS3(p_probersp, mac->bssid);
  618. SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(u1rsvdpageloc, PROBERSP_PG);
  619. totalpacketlen = TOTAL_RESERVED_PKT_LEN;
  620. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
  621. "rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  622. &reserved_page_packet[0], totalpacketlen);
  623. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
  624. "rtl92ee_set_fw_rsvdpagepkt(): HW_VAR_SET_TX_CMD: ALL\n",
  625. u1rsvdpageloc, 3);
  626. skb = dev_alloc_skb(totalpacketlen);
  627. memcpy((u8 *)skb_put(skb, totalpacketlen),
  628. &reserved_page_packet, totalpacketlen);
  629. b_dlok = true;
  630. if (b_dlok) {
  631. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
  632. "Set RSVD page location to Fw.\n");
  633. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD ,
  634. "H2C_RSVDPAGE:\n", u1rsvdpageloc, 3);
  635. rtl92ee_fill_h2c_cmd(hw, H2C_92E_RSVDPAGE,
  636. sizeof(u1rsvdpageloc), u1rsvdpageloc);
  637. } else {
  638. RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
  639. "Set RSVD page location to Fw FAIL!!!!!!.\n");
  640. }
  641. }
  642. /*Shoud check FW support p2p or not.*/
  643. static void rtl92ee_set_p2p_ctw_period_cmd(struct ieee80211_hw *hw, u8 ctwindow)
  644. {
  645. u8 u1_ctwindow_period[1] = {ctwindow};
  646. rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_CTW_CMD, 1, u1_ctwindow_period);
  647. }
  648. void rtl92ee_set_p2p_ps_offload_cmd(struct ieee80211_hw *hw, u8 p2p_ps_state)
  649. {
  650. struct rtl_priv *rtlpriv = rtl_priv(hw);
  651. struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw));
  652. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  653. struct rtl_p2p_ps_info *p2pinfo = &rtlps->p2p_ps_info;
  654. struct p2p_ps_offload_t *p2p_ps_offload = &rtlhal->p2p_ps_offload;
  655. u8 i;
  656. u16 ctwindow;
  657. u32 start_time, tsf_low;
  658. switch (p2p_ps_state) {
  659. case P2P_PS_DISABLE:
  660. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_DISABLE\n");
  661. memset(p2p_ps_offload, 0, sizeof(*p2p_ps_offload));
  662. break;
  663. case P2P_PS_ENABLE:
  664. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_ENABLE\n");
  665. /* update CTWindow value. */
  666. if (p2pinfo->ctwindow > 0) {
  667. p2p_ps_offload->ctwindow_en = 1;
  668. ctwindow = p2pinfo->ctwindow;
  669. rtl92ee_set_p2p_ctw_period_cmd(hw, ctwindow);
  670. }
  671. /* hw only support 2 set of NoA */
  672. for (i = 0 ; i < p2pinfo->noa_num ; i++) {
  673. /* To control the register setting for which NOA*/
  674. rtl_write_byte(rtlpriv, 0x5cf, (i << 4));
  675. if (i == 0)
  676. p2p_ps_offload->noa0_en = 1;
  677. else
  678. p2p_ps_offload->noa1_en = 1;
  679. /* config P2P NoA Descriptor Register */
  680. rtl_write_dword(rtlpriv, 0x5E0,
  681. p2pinfo->noa_duration[i]);
  682. rtl_write_dword(rtlpriv, 0x5E4,
  683. p2pinfo->noa_interval[i]);
  684. /*Get Current TSF value */
  685. tsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
  686. start_time = p2pinfo->noa_start_time[i];
  687. if (p2pinfo->noa_count_type[i] != 1) {
  688. while (start_time <= (tsf_low + (50 * 1024))) {
  689. start_time += p2pinfo->noa_interval[i];
  690. if (p2pinfo->noa_count_type[i] != 255)
  691. p2pinfo->noa_count_type[i]--;
  692. }
  693. }
  694. rtl_write_dword(rtlpriv, 0x5E8, start_time);
  695. rtl_write_dword(rtlpriv, 0x5EC,
  696. p2pinfo->noa_count_type[i]);
  697. }
  698. if ((p2pinfo->opp_ps == 1) || (p2pinfo->noa_num > 0)) {
  699. /* rst p2p circuit */
  700. rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, BIT(4));
  701. p2p_ps_offload->offload_en = 1;
  702. if (P2P_ROLE_GO == rtlpriv->mac80211.p2p) {
  703. p2p_ps_offload->role = 1;
  704. p2p_ps_offload->allstasleep = 0;
  705. } else {
  706. p2p_ps_offload->role = 0;
  707. }
  708. p2p_ps_offload->discovery = 0;
  709. }
  710. break;
  711. case P2P_PS_SCAN:
  712. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_SCAN\n");
  713. p2p_ps_offload->discovery = 1;
  714. break;
  715. case P2P_PS_SCAN_DONE:
  716. RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD , "P2P_PS_SCAN_DONE\n");
  717. p2p_ps_offload->discovery = 0;
  718. p2pinfo->p2p_ps_state = P2P_PS_ENABLE;
  719. break;
  720. default:
  721. break;
  722. }
  723. rtl92ee_fill_h2c_cmd(hw, H2C_92E_P2P_PS_OFFLOAD, 1,
  724. (u8 *)p2p_ps_offload);
  725. }
  726. static void _rtl92ee_c2h_ra_report_handler(struct ieee80211_hw *hw,
  727. u8 *cmd_buf, u8 cmd_len)
  728. {
  729. u8 rate = cmd_buf[0] & 0x3F;
  730. bool collision_state = cmd_buf[3] & BIT(0);
  731. rtl92ee_dm_dynamic_arfb_select(hw, rate, collision_state);
  732. }
  733. static void _rtl92ee_c2h_content_parsing(struct ieee80211_hw *hw, u8 c2h_cmd_id,
  734. u8 c2h_cmd_len, u8 *tmp_buf)
  735. {
  736. struct rtl_priv *rtlpriv = rtl_priv(hw);
  737. switch (c2h_cmd_id) {
  738. case C2H_8192E_DBG:
  739. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  740. "[C2H], C2H_8723BE_DBG!!\n");
  741. break;
  742. case C2H_8192E_TXBF:
  743. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  744. "[C2H], C2H_8192E_TXBF!!\n");
  745. break;
  746. case C2H_8192E_TX_REPORT:
  747. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE ,
  748. "[C2H], C2H_8723BE_TX_REPORT!\n");
  749. break;
  750. case C2H_8192E_BT_INFO:
  751. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  752. "[C2H], C2H_8723BE_BT_INFO!!\n");
  753. rtlpriv->btcoexist.btc_ops->btc_btinfo_notify(rtlpriv, tmp_buf,
  754. c2h_cmd_len);
  755. break;
  756. case C2H_8192E_BT_MP:
  757. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  758. "[C2H], C2H_8723BE_BT_MP!!\n");
  759. break;
  760. case C2H_8192E_RA_RPT:
  761. _rtl92ee_c2h_ra_report_handler(hw, tmp_buf, c2h_cmd_len);
  762. break;
  763. default:
  764. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  765. "[C2H], Unknown packet!! CmdId(%#X)!\n", c2h_cmd_id);
  766. break;
  767. }
  768. }
  769. void rtl92ee_c2h_packet_handler(struct ieee80211_hw *hw, u8 *buffer, u8 len)
  770. {
  771. struct rtl_priv *rtlpriv = rtl_priv(hw);
  772. u8 c2h_cmd_id = 0, c2h_cmd_seq = 0, c2h_cmd_len = 0;
  773. u8 *tmp_buf = NULL;
  774. c2h_cmd_id = buffer[0];
  775. c2h_cmd_seq = buffer[1];
  776. c2h_cmd_len = len - 2;
  777. tmp_buf = buffer + 2;
  778. RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE,
  779. "[C2H packet], c2hCmdId=0x%x, c2hCmdSeq=0x%x, c2hCmdLen=%d\n",
  780. c2h_cmd_id, c2h_cmd_seq, c2h_cmd_len);
  781. RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_TRACE,
  782. "[C2H packet], Content Hex:\n", tmp_buf, c2h_cmd_len);
  783. _rtl92ee_c2h_content_parsing(hw, c2h_cmd_id, c2h_cmd_len, tmp_buf);
  784. }