lmc_main.c 61 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131
  1. /*
  2. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  3. * All rights reserved. www.lanmedia.com
  4. * Generic HDLC port Copyright (C) 2008 Krzysztof Halasa <khc@pm.waw.pl>
  5. *
  6. * This code is written by:
  7. * Andrew Stanley-Jones (asj@cban.com)
  8. * Rob Braun (bbraun@vix.com),
  9. * Michael Graff (explorer@vix.com) and
  10. * Matt Thomas (matt@3am-software.com).
  11. *
  12. * With Help By:
  13. * David Boggs
  14. * Ron Crane
  15. * Alan Cox
  16. *
  17. * This software may be used and distributed according to the terms
  18. * of the GNU General Public License version 2, incorporated herein by reference.
  19. *
  20. * Driver for the LanMedia LMC5200, LMC5245, LMC1000, LMC1200 cards.
  21. *
  22. * To control link specific options lmcctl is required.
  23. * It can be obtained from ftp.lanmedia.com.
  24. *
  25. * Linux driver notes:
  26. * Linux uses the device struct lmc_private to pass private information
  27. * around.
  28. *
  29. * The initialization portion of this driver (the lmc_reset() and the
  30. * lmc_dec_reset() functions, as well as the led controls and the
  31. * lmc_initcsrs() functions.
  32. *
  33. * The watchdog function runs every second and checks to see if
  34. * we still have link, and that the timing source is what we expected
  35. * it to be. If link is lost, the interface is marked down, and
  36. * we no longer can transmit.
  37. *
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/string.h>
  42. #include <linux/timer.h>
  43. #include <linux/ptrace.h>
  44. #include <linux/errno.h>
  45. #include <linux/ioport.h>
  46. #include <linux/slab.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/pci.h>
  49. #include <linux/delay.h>
  50. #include <linux/hdlc.h>
  51. #include <linux/in.h>
  52. #include <linux/if_arp.h>
  53. #include <linux/netdevice.h>
  54. #include <linux/etherdevice.h>
  55. #include <linux/skbuff.h>
  56. #include <linux/inet.h>
  57. #include <linux/bitops.h>
  58. #include <asm/processor.h> /* Processor type for cache alignment. */
  59. #include <asm/io.h>
  60. #include <asm/dma.h>
  61. #include <asm/uaccess.h>
  62. //#include <asm/spinlock.h>
  63. #define DRIVER_MAJOR_VERSION 1
  64. #define DRIVER_MINOR_VERSION 34
  65. #define DRIVER_SUB_VERSION 0
  66. #define DRIVER_VERSION ((DRIVER_MAJOR_VERSION << 8) + DRIVER_MINOR_VERSION)
  67. #include "lmc.h"
  68. #include "lmc_var.h"
  69. #include "lmc_ioctl.h"
  70. #include "lmc_debug.h"
  71. #include "lmc_proto.h"
  72. static int LMC_PKT_BUF_SZ = 1542;
  73. static const struct pci_device_id lmc_pci_tbl[] = {
  74. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  75. PCI_VENDOR_ID_LMC, PCI_ANY_ID },
  76. { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
  77. PCI_ANY_ID, PCI_VENDOR_ID_LMC },
  78. { 0 }
  79. };
  80. MODULE_DEVICE_TABLE(pci, lmc_pci_tbl);
  81. MODULE_LICENSE("GPL v2");
  82. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  83. struct net_device *dev);
  84. static int lmc_rx (struct net_device *dev);
  85. static int lmc_open(struct net_device *dev);
  86. static int lmc_close(struct net_device *dev);
  87. static struct net_device_stats *lmc_get_stats(struct net_device *dev);
  88. static irqreturn_t lmc_interrupt(int irq, void *dev_instance);
  89. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, size_t csr_size);
  90. static void lmc_softreset(lmc_softc_t * const);
  91. static void lmc_running_reset(struct net_device *dev);
  92. static int lmc_ifdown(struct net_device * const);
  93. static void lmc_watchdog(unsigned long data);
  94. static void lmc_reset(lmc_softc_t * const sc);
  95. static void lmc_dec_reset(lmc_softc_t * const sc);
  96. static void lmc_driver_timeout(struct net_device *dev);
  97. /*
  98. * linux reserves 16 device specific IOCTLs. We call them
  99. * LMCIOC* to control various bits of our world.
  100. */
  101. int lmc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) /*fold00*/
  102. {
  103. lmc_softc_t *sc = dev_to_sc(dev);
  104. lmc_ctl_t ctl;
  105. int ret = -EOPNOTSUPP;
  106. u16 regVal;
  107. unsigned long flags;
  108. lmc_trace(dev, "lmc_ioctl in");
  109. /*
  110. * Most functions mess with the structure
  111. * Disable interrupts while we do the polling
  112. */
  113. switch (cmd) {
  114. /*
  115. * Return current driver state. Since we keep this up
  116. * To date internally, just copy this out to the user.
  117. */
  118. case LMCIOCGINFO: /*fold01*/
  119. if (copy_to_user(ifr->ifr_data, &sc->ictl, sizeof(lmc_ctl_t)))
  120. ret = -EFAULT;
  121. else
  122. ret = 0;
  123. break;
  124. case LMCIOCSINFO: /*fold01*/
  125. if (!capable(CAP_NET_ADMIN)) {
  126. ret = -EPERM;
  127. break;
  128. }
  129. if(dev->flags & IFF_UP){
  130. ret = -EBUSY;
  131. break;
  132. }
  133. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  134. ret = -EFAULT;
  135. break;
  136. }
  137. spin_lock_irqsave(&sc->lmc_lock, flags);
  138. sc->lmc_media->set_status (sc, &ctl);
  139. if(ctl.crc_length != sc->ictl.crc_length) {
  140. sc->lmc_media->set_crc_length(sc, ctl.crc_length);
  141. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16)
  142. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  143. else
  144. sc->TxDescriptControlInit &= ~LMC_TDES_ADD_CRC_DISABLE;
  145. }
  146. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  147. ret = 0;
  148. break;
  149. case LMCIOCIFTYPE: /*fold01*/
  150. {
  151. u16 old_type = sc->if_type;
  152. u16 new_type;
  153. if (!capable(CAP_NET_ADMIN)) {
  154. ret = -EPERM;
  155. break;
  156. }
  157. if (copy_from_user(&new_type, ifr->ifr_data, sizeof(u16))) {
  158. ret = -EFAULT;
  159. break;
  160. }
  161. if (new_type == old_type)
  162. {
  163. ret = 0 ;
  164. break; /* no change */
  165. }
  166. spin_lock_irqsave(&sc->lmc_lock, flags);
  167. lmc_proto_close(sc);
  168. sc->if_type = new_type;
  169. lmc_proto_attach(sc);
  170. ret = lmc_proto_open(sc);
  171. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  172. break;
  173. }
  174. case LMCIOCGETXINFO: /*fold01*/
  175. spin_lock_irqsave(&sc->lmc_lock, flags);
  176. sc->lmc_xinfo.Magic0 = 0xBEEFCAFE;
  177. sc->lmc_xinfo.PciCardType = sc->lmc_cardtype;
  178. sc->lmc_xinfo.PciSlotNumber = 0;
  179. sc->lmc_xinfo.DriverMajorVersion = DRIVER_MAJOR_VERSION;
  180. sc->lmc_xinfo.DriverMinorVersion = DRIVER_MINOR_VERSION;
  181. sc->lmc_xinfo.DriverSubVersion = DRIVER_SUB_VERSION;
  182. sc->lmc_xinfo.XilinxRevisionNumber =
  183. lmc_mii_readreg (sc, 0, 3) & 0xf;
  184. sc->lmc_xinfo.MaxFrameSize = LMC_PKT_BUF_SZ;
  185. sc->lmc_xinfo.link_status = sc->lmc_media->get_link_status (sc);
  186. sc->lmc_xinfo.mii_reg16 = lmc_mii_readreg (sc, 0, 16);
  187. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  188. sc->lmc_xinfo.Magic1 = 0xDEADBEEF;
  189. if (copy_to_user(ifr->ifr_data, &sc->lmc_xinfo,
  190. sizeof(struct lmc_xinfo)))
  191. ret = -EFAULT;
  192. else
  193. ret = 0;
  194. break;
  195. case LMCIOCGETLMCSTATS:
  196. spin_lock_irqsave(&sc->lmc_lock, flags);
  197. if (sc->lmc_cardtype == LMC_CARDTYPE_T1) {
  198. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_LSB);
  199. sc->extra_stats.framingBitErrorCount +=
  200. lmc_mii_readreg(sc, 0, 18) & 0xff;
  201. lmc_mii_writereg(sc, 0, 17, T1FRAMER_FERR_MSB);
  202. sc->extra_stats.framingBitErrorCount +=
  203. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  204. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_LSB);
  205. sc->extra_stats.lineCodeViolationCount +=
  206. lmc_mii_readreg(sc, 0, 18) & 0xff;
  207. lmc_mii_writereg(sc, 0, 17, T1FRAMER_LCV_MSB);
  208. sc->extra_stats.lineCodeViolationCount +=
  209. (lmc_mii_readreg(sc, 0, 18) & 0xff) << 8;
  210. lmc_mii_writereg(sc, 0, 17, T1FRAMER_AERR);
  211. regVal = lmc_mii_readreg(sc, 0, 18) & 0xff;
  212. sc->extra_stats.lossOfFrameCount +=
  213. (regVal & T1FRAMER_LOF_MASK) >> 4;
  214. sc->extra_stats.changeOfFrameAlignmentCount +=
  215. (regVal & T1FRAMER_COFA_MASK) >> 2;
  216. sc->extra_stats.severelyErroredFrameCount +=
  217. regVal & T1FRAMER_SEF_MASK;
  218. }
  219. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  220. if (copy_to_user(ifr->ifr_data, &sc->lmc_device->stats,
  221. sizeof(sc->lmc_device->stats)) ||
  222. copy_to_user(ifr->ifr_data + sizeof(sc->lmc_device->stats),
  223. &sc->extra_stats, sizeof(sc->extra_stats)))
  224. ret = -EFAULT;
  225. else
  226. ret = 0;
  227. break;
  228. case LMCIOCCLEARLMCSTATS:
  229. if (!capable(CAP_NET_ADMIN)) {
  230. ret = -EPERM;
  231. break;
  232. }
  233. spin_lock_irqsave(&sc->lmc_lock, flags);
  234. memset(&sc->lmc_device->stats, 0, sizeof(sc->lmc_device->stats));
  235. memset(&sc->extra_stats, 0, sizeof(sc->extra_stats));
  236. sc->extra_stats.check = STATCHECK;
  237. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  238. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  239. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  240. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  241. ret = 0;
  242. break;
  243. case LMCIOCSETCIRCUIT: /*fold01*/
  244. if (!capable(CAP_NET_ADMIN)){
  245. ret = -EPERM;
  246. break;
  247. }
  248. if(dev->flags & IFF_UP){
  249. ret = -EBUSY;
  250. break;
  251. }
  252. if (copy_from_user(&ctl, ifr->ifr_data, sizeof(lmc_ctl_t))) {
  253. ret = -EFAULT;
  254. break;
  255. }
  256. spin_lock_irqsave(&sc->lmc_lock, flags);
  257. sc->lmc_media->set_circuit_type(sc, ctl.circuit_type);
  258. sc->ictl.circuit_type = ctl.circuit_type;
  259. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  260. ret = 0;
  261. break;
  262. case LMCIOCRESET: /*fold01*/
  263. if (!capable(CAP_NET_ADMIN)){
  264. ret = -EPERM;
  265. break;
  266. }
  267. spin_lock_irqsave(&sc->lmc_lock, flags);
  268. /* Reset driver and bring back to current state */
  269. printk (" REG16 before reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  270. lmc_running_reset (dev);
  271. printk (" REG16 after reset +%04x\n", lmc_mii_readreg (sc, 0, 16));
  272. LMC_EVENT_LOG(LMC_EVENT_FORCEDRESET, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  273. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  274. ret = 0;
  275. break;
  276. #ifdef DEBUG
  277. case LMCIOCDUMPEVENTLOG:
  278. if (copy_to_user(ifr->ifr_data, &lmcEventLogIndex, sizeof(u32))) {
  279. ret = -EFAULT;
  280. break;
  281. }
  282. if (copy_to_user(ifr->ifr_data + sizeof(u32), lmcEventLogBuf,
  283. sizeof(lmcEventLogBuf)))
  284. ret = -EFAULT;
  285. else
  286. ret = 0;
  287. break;
  288. #endif /* end ifdef _DBG_EVENTLOG */
  289. case LMCIOCT1CONTROL: /*fold01*/
  290. if (sc->lmc_cardtype != LMC_CARDTYPE_T1){
  291. ret = -EOPNOTSUPP;
  292. break;
  293. }
  294. break;
  295. case LMCIOCXILINX: /*fold01*/
  296. {
  297. struct lmc_xilinx_control xc; /*fold02*/
  298. if (!capable(CAP_NET_ADMIN)){
  299. ret = -EPERM;
  300. break;
  301. }
  302. /*
  303. * Stop the xwitter whlie we restart the hardware
  304. */
  305. netif_stop_queue(dev);
  306. if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) {
  307. ret = -EFAULT;
  308. break;
  309. }
  310. switch(xc.command){
  311. case lmc_xilinx_reset: /*fold02*/
  312. {
  313. u16 mii;
  314. spin_lock_irqsave(&sc->lmc_lock, flags);
  315. mii = lmc_mii_readreg (sc, 0, 16);
  316. /*
  317. * Make all of them 0 and make input
  318. */
  319. lmc_gpio_mkinput(sc, 0xff);
  320. /*
  321. * make the reset output
  322. */
  323. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  324. /*
  325. * RESET low to force configuration. This also forces
  326. * the transmitter clock to be internal, but we expect to reset
  327. * that later anyway.
  328. */
  329. sc->lmc_gpio &= ~LMC_GEP_RESET;
  330. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  331. /*
  332. * hold for more than 10 microseconds
  333. */
  334. udelay(50);
  335. sc->lmc_gpio |= LMC_GEP_RESET;
  336. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  337. /*
  338. * stop driving Xilinx-related signals
  339. */
  340. lmc_gpio_mkinput(sc, 0xff);
  341. /* Reset the frammer hardware */
  342. sc->lmc_media->set_link_status (sc, 1);
  343. sc->lmc_media->set_status (sc, NULL);
  344. // lmc_softreset(sc);
  345. {
  346. int i;
  347. for(i = 0; i < 5; i++){
  348. lmc_led_on(sc, LMC_DS3_LED0);
  349. mdelay(100);
  350. lmc_led_off(sc, LMC_DS3_LED0);
  351. lmc_led_on(sc, LMC_DS3_LED1);
  352. mdelay(100);
  353. lmc_led_off(sc, LMC_DS3_LED1);
  354. lmc_led_on(sc, LMC_DS3_LED3);
  355. mdelay(100);
  356. lmc_led_off(sc, LMC_DS3_LED3);
  357. lmc_led_on(sc, LMC_DS3_LED2);
  358. mdelay(100);
  359. lmc_led_off(sc, LMC_DS3_LED2);
  360. }
  361. }
  362. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  363. ret = 0x0;
  364. }
  365. break;
  366. case lmc_xilinx_load_prom: /*fold02*/
  367. {
  368. u16 mii;
  369. int timeout = 500000;
  370. spin_lock_irqsave(&sc->lmc_lock, flags);
  371. mii = lmc_mii_readreg (sc, 0, 16);
  372. /*
  373. * Make all of them 0 and make input
  374. */
  375. lmc_gpio_mkinput(sc, 0xff);
  376. /*
  377. * make the reset output
  378. */
  379. lmc_gpio_mkoutput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  380. /*
  381. * RESET low to force configuration. This also forces
  382. * the transmitter clock to be internal, but we expect to reset
  383. * that later anyway.
  384. */
  385. sc->lmc_gpio &= ~(LMC_GEP_RESET | LMC_GEP_DP);
  386. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  387. /*
  388. * hold for more than 10 microseconds
  389. */
  390. udelay(50);
  391. sc->lmc_gpio |= LMC_GEP_DP | LMC_GEP_RESET;
  392. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  393. /*
  394. * busy wait for the chip to reset
  395. */
  396. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  397. (timeout-- > 0))
  398. cpu_relax();
  399. /*
  400. * stop driving Xilinx-related signals
  401. */
  402. lmc_gpio_mkinput(sc, 0xff);
  403. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  404. ret = 0x0;
  405. break;
  406. }
  407. case lmc_xilinx_load: /*fold02*/
  408. {
  409. char *data;
  410. int pos;
  411. int timeout = 500000;
  412. if (!xc.data) {
  413. ret = -EINVAL;
  414. break;
  415. }
  416. data = kmalloc(xc.len, GFP_KERNEL);
  417. if (!data) {
  418. ret = -ENOMEM;
  419. break;
  420. }
  421. if(copy_from_user(data, xc.data, xc.len))
  422. {
  423. kfree(data);
  424. ret = -ENOMEM;
  425. break;
  426. }
  427. printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data);
  428. spin_lock_irqsave(&sc->lmc_lock, flags);
  429. lmc_gpio_mkinput(sc, 0xff);
  430. /*
  431. * Clear the Xilinx and start prgramming from the DEC
  432. */
  433. /*
  434. * Set ouput as:
  435. * Reset: 0 (active)
  436. * DP: 0 (active)
  437. * Mode: 1
  438. *
  439. */
  440. sc->lmc_gpio = 0x00;
  441. sc->lmc_gpio &= ~LMC_GEP_DP;
  442. sc->lmc_gpio &= ~LMC_GEP_RESET;
  443. sc->lmc_gpio |= LMC_GEP_MODE;
  444. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  445. lmc_gpio_mkoutput(sc, LMC_GEP_MODE | LMC_GEP_DP | LMC_GEP_RESET);
  446. /*
  447. * Wait at least 10 us 20 to be safe
  448. */
  449. udelay(50);
  450. /*
  451. * Clear reset and activate programming lines
  452. * Reset: Input
  453. * DP: Input
  454. * Clock: Output
  455. * Data: Output
  456. * Mode: Output
  457. */
  458. lmc_gpio_mkinput(sc, LMC_GEP_DP | LMC_GEP_RESET);
  459. /*
  460. * Set LOAD, DATA, Clock to 1
  461. */
  462. sc->lmc_gpio = 0x00;
  463. sc->lmc_gpio |= LMC_GEP_MODE;
  464. sc->lmc_gpio |= LMC_GEP_DATA;
  465. sc->lmc_gpio |= LMC_GEP_CLK;
  466. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  467. lmc_gpio_mkoutput(sc, LMC_GEP_DATA | LMC_GEP_CLK | LMC_GEP_MODE );
  468. /*
  469. * busy wait for the chip to reset
  470. */
  471. while( (LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0 &&
  472. (timeout-- > 0))
  473. cpu_relax();
  474. printk(KERN_DEBUG "%s: Waited %d for the Xilinx to clear it's memory\n", dev->name, 500000-timeout);
  475. for(pos = 0; pos < xc.len; pos++){
  476. switch(data[pos]){
  477. case 0:
  478. sc->lmc_gpio &= ~LMC_GEP_DATA; /* Data is 0 */
  479. break;
  480. case 1:
  481. sc->lmc_gpio |= LMC_GEP_DATA; /* Data is 1 */
  482. break;
  483. default:
  484. printk(KERN_WARNING "%s Bad data in xilinx programming data at %d, got %d wanted 0 or 1\n", dev->name, pos, data[pos]);
  485. sc->lmc_gpio |= LMC_GEP_DATA; /* Assume it's 1 */
  486. }
  487. sc->lmc_gpio &= ~LMC_GEP_CLK; /* Clock to zero */
  488. sc->lmc_gpio |= LMC_GEP_MODE;
  489. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  490. udelay(1);
  491. sc->lmc_gpio |= LMC_GEP_CLK; /* Put the clack back to one */
  492. sc->lmc_gpio |= LMC_GEP_MODE;
  493. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  494. udelay(1);
  495. }
  496. if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_INIT) == 0){
  497. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (corrupted data)\n", dev->name);
  498. }
  499. else if((LMC_CSR_READ(sc, csr_gp) & LMC_GEP_DP) == 0){
  500. printk(KERN_WARNING "%s: Reprogramming FAILED. Needs to be reprogrammed. (done)\n", dev->name);
  501. }
  502. else {
  503. printk(KERN_DEBUG "%s: Done reprogramming Xilinx, %d bits, good luck!\n", dev->name, pos);
  504. }
  505. lmc_gpio_mkinput(sc, 0xff);
  506. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  507. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  508. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  509. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  510. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  511. kfree(data);
  512. ret = 0;
  513. break;
  514. }
  515. default: /*fold02*/
  516. ret = -EBADE;
  517. break;
  518. }
  519. netif_wake_queue(dev);
  520. sc->lmc_txfull = 0;
  521. }
  522. break;
  523. default: /*fold01*/
  524. /* If we don't know what to do, give the protocol a shot. */
  525. ret = lmc_proto_ioctl (sc, ifr, cmd);
  526. break;
  527. }
  528. lmc_trace(dev, "lmc_ioctl out");
  529. return ret;
  530. }
  531. /* the watchdog process that cruises around */
  532. static void lmc_watchdog (unsigned long data) /*fold00*/
  533. {
  534. struct net_device *dev = (struct net_device *)data;
  535. lmc_softc_t *sc = dev_to_sc(dev);
  536. int link_status;
  537. u32 ticks;
  538. unsigned long flags;
  539. lmc_trace(dev, "lmc_watchdog in");
  540. spin_lock_irqsave(&sc->lmc_lock, flags);
  541. if(sc->check != 0xBEAFCAFE){
  542. printk("LMC: Corrupt net_device struct, breaking out\n");
  543. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  544. return;
  545. }
  546. /* Make sure the tx jabber and rx watchdog are off,
  547. * and the transmit and receive processes are running.
  548. */
  549. LMC_CSR_WRITE (sc, csr_15, 0x00000011);
  550. sc->lmc_cmdmode |= TULIP_CMD_TXRUN | TULIP_CMD_RXRUN;
  551. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  552. if (sc->lmc_ok == 0)
  553. goto kick_timer;
  554. LMC_EVENT_LOG(LMC_EVENT_WATCHDOG, LMC_CSR_READ (sc, csr_status), lmc_mii_readreg (sc, 0, 16));
  555. /* --- begin time out check -----------------------------------
  556. * check for a transmit interrupt timeout
  557. * Has the packet xmt vs xmt serviced threshold been exceeded */
  558. if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  559. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  560. sc->tx_TimeoutInd == 0)
  561. {
  562. /* wait for the watchdog to come around again */
  563. sc->tx_TimeoutInd = 1;
  564. }
  565. else if (sc->lmc_taint_tx == sc->lastlmc_taint_tx &&
  566. sc->lmc_device->stats.tx_packets > sc->lasttx_packets &&
  567. sc->tx_TimeoutInd)
  568. {
  569. LMC_EVENT_LOG(LMC_EVENT_XMTINTTMO, LMC_CSR_READ (sc, csr_status), 0);
  570. sc->tx_TimeoutDisplay = 1;
  571. sc->extra_stats.tx_TimeoutCnt++;
  572. /* DEC chip is stuck, hit it with a RESET!!!! */
  573. lmc_running_reset (dev);
  574. /* look at receive & transmit process state to make sure they are running */
  575. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  576. /* look at: DSR - 02 for Reg 16
  577. * CTS - 08
  578. * DCD - 10
  579. * RI - 20
  580. * for Reg 17
  581. */
  582. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg (sc, 0, 16), lmc_mii_readreg (sc, 0, 17));
  583. /* reset the transmit timeout detection flag */
  584. sc->tx_TimeoutInd = 0;
  585. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  586. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  587. } else {
  588. sc->tx_TimeoutInd = 0;
  589. sc->lastlmc_taint_tx = sc->lmc_taint_tx;
  590. sc->lasttx_packets = sc->lmc_device->stats.tx_packets;
  591. }
  592. /* --- end time out check ----------------------------------- */
  593. link_status = sc->lmc_media->get_link_status (sc);
  594. /*
  595. * hardware level link lost, but the interface is marked as up.
  596. * Mark it as down.
  597. */
  598. if ((link_status == 0) && (sc->last_link_status != 0)) {
  599. printk(KERN_WARNING "%s: hardware/physical link down\n", dev->name);
  600. sc->last_link_status = 0;
  601. /* lmc_reset (sc); Why reset??? The link can go down ok */
  602. /* Inform the world that link has been lost */
  603. netif_carrier_off(dev);
  604. }
  605. /*
  606. * hardware link is up, but the interface is marked as down.
  607. * Bring it back up again.
  608. */
  609. if (link_status != 0 && sc->last_link_status == 0) {
  610. printk(KERN_WARNING "%s: hardware/physical link up\n", dev->name);
  611. sc->last_link_status = 1;
  612. /* lmc_reset (sc); Again why reset??? */
  613. netif_carrier_on(dev);
  614. }
  615. /* Call media specific watchdog functions */
  616. sc->lmc_media->watchdog(sc);
  617. /*
  618. * Poke the transmitter to make sure it
  619. * never stops, even if we run out of mem
  620. */
  621. LMC_CSR_WRITE(sc, csr_rxpoll, 0);
  622. /*
  623. * Check for code that failed
  624. * and try and fix it as appropriate
  625. */
  626. if(sc->failed_ring == 1){
  627. /*
  628. * Failed to setup the recv/xmit rin
  629. * Try again
  630. */
  631. sc->failed_ring = 0;
  632. lmc_softreset(sc);
  633. }
  634. if(sc->failed_recv_alloc == 1){
  635. /*
  636. * We failed to alloc mem in the
  637. * interrupt handler, go through the rings
  638. * and rebuild them
  639. */
  640. sc->failed_recv_alloc = 0;
  641. lmc_softreset(sc);
  642. }
  643. /*
  644. * remember the timer value
  645. */
  646. kick_timer:
  647. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  648. LMC_CSR_WRITE (sc, csr_gp_timer, 0xffffffffUL);
  649. sc->ictl.ticks = 0x0000ffff - (ticks & 0x0000ffff);
  650. /*
  651. * restart this timer.
  652. */
  653. sc->timer.expires = jiffies + (HZ);
  654. add_timer (&sc->timer);
  655. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  656. lmc_trace(dev, "lmc_watchdog out");
  657. }
  658. static int lmc_attach(struct net_device *dev, unsigned short encoding,
  659. unsigned short parity)
  660. {
  661. if (encoding == ENCODING_NRZ && parity == PARITY_CRC16_PR1_CCITT)
  662. return 0;
  663. return -EINVAL;
  664. }
  665. static const struct net_device_ops lmc_ops = {
  666. .ndo_open = lmc_open,
  667. .ndo_stop = lmc_close,
  668. .ndo_change_mtu = hdlc_change_mtu,
  669. .ndo_start_xmit = hdlc_start_xmit,
  670. .ndo_do_ioctl = lmc_ioctl,
  671. .ndo_tx_timeout = lmc_driver_timeout,
  672. .ndo_get_stats = lmc_get_stats,
  673. };
  674. static int lmc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  675. {
  676. lmc_softc_t *sc;
  677. struct net_device *dev;
  678. u16 subdevice;
  679. u16 AdapModelNum;
  680. int err;
  681. static int cards_found;
  682. /* lmc_trace(dev, "lmc_init_one in"); */
  683. err = pci_enable_device(pdev);
  684. if (err) {
  685. printk(KERN_ERR "lmc: pci enable failed: %d\n", err);
  686. return err;
  687. }
  688. err = pci_request_regions(pdev, "lmc");
  689. if (err) {
  690. printk(KERN_ERR "lmc: pci_request_region failed\n");
  691. goto err_req_io;
  692. }
  693. /*
  694. * Allocate our own device structure
  695. */
  696. sc = kzalloc(sizeof(lmc_softc_t), GFP_KERNEL);
  697. if (!sc) {
  698. err = -ENOMEM;
  699. goto err_kzalloc;
  700. }
  701. dev = alloc_hdlcdev(sc);
  702. if (!dev) {
  703. printk(KERN_ERR "lmc:alloc_netdev for device failed\n");
  704. err = -ENOMEM;
  705. goto err_hdlcdev;
  706. }
  707. dev->type = ARPHRD_HDLC;
  708. dev_to_hdlc(dev)->xmit = lmc_start_xmit;
  709. dev_to_hdlc(dev)->attach = lmc_attach;
  710. dev->netdev_ops = &lmc_ops;
  711. dev->watchdog_timeo = HZ; /* 1 second */
  712. dev->tx_queue_len = 100;
  713. sc->lmc_device = dev;
  714. sc->name = dev->name;
  715. sc->if_type = LMC_PPP;
  716. sc->check = 0xBEAFCAFE;
  717. dev->base_addr = pci_resource_start(pdev, 0);
  718. dev->irq = pdev->irq;
  719. pci_set_drvdata(pdev, dev);
  720. SET_NETDEV_DEV(dev, &pdev->dev);
  721. /*
  722. * This will get the protocol layer ready and do any 1 time init's
  723. * Must have a valid sc and dev structure
  724. */
  725. lmc_proto_attach(sc);
  726. /* Init the spin lock so can call it latter */
  727. spin_lock_init(&sc->lmc_lock);
  728. pci_set_master(pdev);
  729. printk(KERN_INFO "%s: detected at %lx, irq %d\n", dev->name,
  730. dev->base_addr, dev->irq);
  731. err = register_hdlc_device(dev);
  732. if (err) {
  733. printk(KERN_ERR "%s: register_netdev failed.\n", dev->name);
  734. free_netdev(dev);
  735. goto err_hdlcdev;
  736. }
  737. sc->lmc_cardtype = LMC_CARDTYPE_UNKNOWN;
  738. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  739. /*
  740. *
  741. * Check either the subvendor or the subdevice, some systems reverse
  742. * the setting in the bois, seems to be version and arch dependent?
  743. * Fix the error, exchange the two values
  744. */
  745. if ((subdevice = pdev->subsystem_device) == PCI_VENDOR_ID_LMC)
  746. subdevice = pdev->subsystem_vendor;
  747. switch (subdevice) {
  748. case PCI_DEVICE_ID_LMC_HSSI:
  749. printk(KERN_INFO "%s: LMC HSSI\n", dev->name);
  750. sc->lmc_cardtype = LMC_CARDTYPE_HSSI;
  751. sc->lmc_media = &lmc_hssi_media;
  752. break;
  753. case PCI_DEVICE_ID_LMC_DS3:
  754. printk(KERN_INFO "%s: LMC DS3\n", dev->name);
  755. sc->lmc_cardtype = LMC_CARDTYPE_DS3;
  756. sc->lmc_media = &lmc_ds3_media;
  757. break;
  758. case PCI_DEVICE_ID_LMC_SSI:
  759. printk(KERN_INFO "%s: LMC SSI\n", dev->name);
  760. sc->lmc_cardtype = LMC_CARDTYPE_SSI;
  761. sc->lmc_media = &lmc_ssi_media;
  762. break;
  763. case PCI_DEVICE_ID_LMC_T1:
  764. printk(KERN_INFO "%s: LMC T1\n", dev->name);
  765. sc->lmc_cardtype = LMC_CARDTYPE_T1;
  766. sc->lmc_media = &lmc_t1_media;
  767. break;
  768. default:
  769. printk(KERN_WARNING "%s: LMC UNKNOWN CARD!\n", dev->name);
  770. break;
  771. }
  772. lmc_initcsrs (sc, dev->base_addr, 8);
  773. lmc_gpio_mkinput (sc, 0xff);
  774. sc->lmc_gpio = 0; /* drive no signals yet */
  775. sc->lmc_media->defaults (sc);
  776. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  777. /* verify that the PCI Sub System ID matches the Adapter Model number
  778. * from the MII register
  779. */
  780. AdapModelNum = (lmc_mii_readreg (sc, 0, 3) & 0x3f0) >> 4;
  781. if ((AdapModelNum != LMC_ADAP_T1 || /* detect LMC1200 */
  782. subdevice != PCI_DEVICE_ID_LMC_T1) &&
  783. (AdapModelNum != LMC_ADAP_SSI || /* detect LMC1000 */
  784. subdevice != PCI_DEVICE_ID_LMC_SSI) &&
  785. (AdapModelNum != LMC_ADAP_DS3 || /* detect LMC5245 */
  786. subdevice != PCI_DEVICE_ID_LMC_DS3) &&
  787. (AdapModelNum != LMC_ADAP_HSSI || /* detect LMC5200 */
  788. subdevice != PCI_DEVICE_ID_LMC_HSSI))
  789. printk(KERN_WARNING "%s: Model number (%d) miscompare for PCI"
  790. " Subsystem ID = 0x%04x\n",
  791. dev->name, AdapModelNum, subdevice);
  792. /*
  793. * reset clock
  794. */
  795. LMC_CSR_WRITE (sc, csr_gp_timer, 0xFFFFFFFFUL);
  796. sc->board_idx = cards_found++;
  797. sc->extra_stats.check = STATCHECK;
  798. sc->extra_stats.version_size = (DRIVER_VERSION << 16) +
  799. sizeof(sc->lmc_device->stats) + sizeof(sc->extra_stats);
  800. sc->extra_stats.lmc_cardtype = sc->lmc_cardtype;
  801. sc->lmc_ok = 0;
  802. sc->last_link_status = 0;
  803. lmc_trace(dev, "lmc_init_one out");
  804. return 0;
  805. err_hdlcdev:
  806. kfree(sc);
  807. err_kzalloc:
  808. pci_release_regions(pdev);
  809. err_req_io:
  810. pci_disable_device(pdev);
  811. return err;
  812. }
  813. /*
  814. * Called from pci when removing module.
  815. */
  816. static void lmc_remove_one(struct pci_dev *pdev)
  817. {
  818. struct net_device *dev = pci_get_drvdata(pdev);
  819. if (dev) {
  820. printk(KERN_DEBUG "%s: removing...\n", dev->name);
  821. unregister_hdlc_device(dev);
  822. free_netdev(dev);
  823. pci_release_regions(pdev);
  824. pci_disable_device(pdev);
  825. }
  826. }
  827. /* After this is called, packets can be sent.
  828. * Does not initialize the addresses
  829. */
  830. static int lmc_open(struct net_device *dev)
  831. {
  832. lmc_softc_t *sc = dev_to_sc(dev);
  833. int err;
  834. lmc_trace(dev, "lmc_open in");
  835. lmc_led_on(sc, LMC_DS3_LED0);
  836. lmc_dec_reset(sc);
  837. lmc_reset(sc);
  838. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ(sc, csr_status), 0);
  839. LMC_EVENT_LOG(LMC_EVENT_RESET2, lmc_mii_readreg(sc, 0, 16),
  840. lmc_mii_readreg(sc, 0, 17));
  841. if (sc->lmc_ok){
  842. lmc_trace(dev, "lmc_open lmc_ok out");
  843. return 0;
  844. }
  845. lmc_softreset (sc);
  846. /* Since we have to use PCI bus, this should work on x86,alpha,ppc */
  847. if (request_irq (dev->irq, lmc_interrupt, IRQF_SHARED, dev->name, dev)){
  848. printk(KERN_WARNING "%s: could not get irq: %d\n", dev->name, dev->irq);
  849. lmc_trace(dev, "lmc_open irq failed out");
  850. return -EAGAIN;
  851. }
  852. sc->got_irq = 1;
  853. /* Assert Terminal Active */
  854. sc->lmc_miireg16 |= LMC_MII16_LED_ALL;
  855. sc->lmc_media->set_link_status (sc, LMC_LINK_UP);
  856. /*
  857. * reset to last state.
  858. */
  859. sc->lmc_media->set_status (sc, NULL);
  860. /* setup default bits to be used in tulip_desc_t transmit descriptor
  861. * -baz */
  862. sc->TxDescriptControlInit = (
  863. LMC_TDES_INTERRUPT_ON_COMPLETION
  864. | LMC_TDES_FIRST_SEGMENT
  865. | LMC_TDES_LAST_SEGMENT
  866. | LMC_TDES_SECOND_ADDR_CHAINED
  867. | LMC_TDES_DISABLE_PADDING
  868. );
  869. if (sc->ictl.crc_length == LMC_CTL_CRC_LENGTH_16) {
  870. /* disable 32 bit CRC generated by ASIC */
  871. sc->TxDescriptControlInit |= LMC_TDES_ADD_CRC_DISABLE;
  872. }
  873. sc->lmc_media->set_crc_length(sc, sc->ictl.crc_length);
  874. /* Acknoledge the Terminal Active and light LEDs */
  875. /* dev->flags |= IFF_UP; */
  876. if ((err = lmc_proto_open(sc)) != 0)
  877. return err;
  878. netif_start_queue(dev);
  879. sc->extra_stats.tx_tbusy0++;
  880. /*
  881. * select what interrupts we want to get
  882. */
  883. sc->lmc_intrmask = 0;
  884. /* Should be using the default interrupt mask defined in the .h file. */
  885. sc->lmc_intrmask |= (TULIP_STS_NORMALINTR
  886. | TULIP_STS_RXINTR
  887. | TULIP_STS_TXINTR
  888. | TULIP_STS_ABNRMLINTR
  889. | TULIP_STS_SYSERROR
  890. | TULIP_STS_TXSTOPPED
  891. | TULIP_STS_TXUNDERFLOW
  892. | TULIP_STS_RXSTOPPED
  893. | TULIP_STS_RXNOBUF
  894. );
  895. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  896. sc->lmc_cmdmode |= TULIP_CMD_TXRUN;
  897. sc->lmc_cmdmode |= TULIP_CMD_RXRUN;
  898. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  899. sc->lmc_ok = 1; /* Run watchdog */
  900. /*
  901. * Set the if up now - pfb
  902. */
  903. sc->last_link_status = 1;
  904. /*
  905. * Setup a timer for the watchdog on probe, and start it running.
  906. * Since lmc_ok == 0, it will be a NOP for now.
  907. */
  908. init_timer (&sc->timer);
  909. sc->timer.expires = jiffies + HZ;
  910. sc->timer.data = (unsigned long) dev;
  911. sc->timer.function = lmc_watchdog;
  912. add_timer (&sc->timer);
  913. lmc_trace(dev, "lmc_open out");
  914. return 0;
  915. }
  916. /* Total reset to compensate for the AdTran DSU doing bad things
  917. * under heavy load
  918. */
  919. static void lmc_running_reset (struct net_device *dev) /*fold00*/
  920. {
  921. lmc_softc_t *sc = dev_to_sc(dev);
  922. lmc_trace(dev, "lmc_running_reset in");
  923. /* stop interrupts */
  924. /* Clear the interrupt mask */
  925. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  926. lmc_dec_reset (sc);
  927. lmc_reset (sc);
  928. lmc_softreset (sc);
  929. /* sc->lmc_miireg16 |= LMC_MII16_LED_ALL; */
  930. sc->lmc_media->set_link_status (sc, 1);
  931. sc->lmc_media->set_status (sc, NULL);
  932. netif_wake_queue(dev);
  933. sc->lmc_txfull = 0;
  934. sc->extra_stats.tx_tbusy0++;
  935. sc->lmc_intrmask = TULIP_DEFAULT_INTR_MASK;
  936. LMC_CSR_WRITE (sc, csr_intr, sc->lmc_intrmask);
  937. sc->lmc_cmdmode |= (TULIP_CMD_TXRUN | TULIP_CMD_RXRUN);
  938. LMC_CSR_WRITE (sc, csr_command, sc->lmc_cmdmode);
  939. lmc_trace(dev, "lmc_runnin_reset_out");
  940. }
  941. /* This is what is called when you ifconfig down a device.
  942. * This disables the timer for the watchdog and keepalives,
  943. * and disables the irq for dev.
  944. */
  945. static int lmc_close(struct net_device *dev)
  946. {
  947. /* not calling release_region() as we should */
  948. lmc_softc_t *sc = dev_to_sc(dev);
  949. lmc_trace(dev, "lmc_close in");
  950. sc->lmc_ok = 0;
  951. sc->lmc_media->set_link_status (sc, 0);
  952. del_timer (&sc->timer);
  953. lmc_proto_close(sc);
  954. lmc_ifdown (dev);
  955. lmc_trace(dev, "lmc_close out");
  956. return 0;
  957. }
  958. /* Ends the transfer of packets */
  959. /* When the interface goes down, this is called */
  960. static int lmc_ifdown (struct net_device *dev) /*fold00*/
  961. {
  962. lmc_softc_t *sc = dev_to_sc(dev);
  963. u32 csr6;
  964. int i;
  965. lmc_trace(dev, "lmc_ifdown in");
  966. /* Don't let anything else go on right now */
  967. // dev->start = 0;
  968. netif_stop_queue(dev);
  969. sc->extra_stats.tx_tbusy1++;
  970. /* stop interrupts */
  971. /* Clear the interrupt mask */
  972. LMC_CSR_WRITE (sc, csr_intr, 0x00000000);
  973. /* Stop Tx and Rx on the chip */
  974. csr6 = LMC_CSR_READ (sc, csr_command);
  975. csr6 &= ~LMC_DEC_ST; /* Turn off the Transmission bit */
  976. csr6 &= ~LMC_DEC_SR; /* Turn off the Receive bit */
  977. LMC_CSR_WRITE (sc, csr_command, csr6);
  978. sc->lmc_device->stats.rx_missed_errors +=
  979. LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  980. /* release the interrupt */
  981. if(sc->got_irq == 1){
  982. free_irq (dev->irq, dev);
  983. sc->got_irq = 0;
  984. }
  985. /* free skbuffs in the Rx queue */
  986. for (i = 0; i < LMC_RXDESCS; i++)
  987. {
  988. struct sk_buff *skb = sc->lmc_rxq[i];
  989. sc->lmc_rxq[i] = NULL;
  990. sc->lmc_rxring[i].status = 0;
  991. sc->lmc_rxring[i].length = 0;
  992. sc->lmc_rxring[i].buffer1 = 0xDEADBEEF;
  993. if (skb != NULL)
  994. dev_kfree_skb(skb);
  995. sc->lmc_rxq[i] = NULL;
  996. }
  997. for (i = 0; i < LMC_TXDESCS; i++)
  998. {
  999. if (sc->lmc_txq[i] != NULL)
  1000. dev_kfree_skb(sc->lmc_txq[i]);
  1001. sc->lmc_txq[i] = NULL;
  1002. }
  1003. lmc_led_off (sc, LMC_MII16_LED_ALL);
  1004. netif_wake_queue(dev);
  1005. sc->extra_stats.tx_tbusy0++;
  1006. lmc_trace(dev, "lmc_ifdown out");
  1007. return 0;
  1008. }
  1009. /* Interrupt handling routine. This will take an incoming packet, or clean
  1010. * up after a trasmit.
  1011. */
  1012. static irqreturn_t lmc_interrupt (int irq, void *dev_instance) /*fold00*/
  1013. {
  1014. struct net_device *dev = (struct net_device *) dev_instance;
  1015. lmc_softc_t *sc = dev_to_sc(dev);
  1016. u32 csr;
  1017. int i;
  1018. s32 stat;
  1019. unsigned int badtx;
  1020. u32 firstcsr;
  1021. int max_work = LMC_RXDESCS;
  1022. int handled = 0;
  1023. lmc_trace(dev, "lmc_interrupt in");
  1024. spin_lock(&sc->lmc_lock);
  1025. /*
  1026. * Read the csr to find what interrupts we have (if any)
  1027. */
  1028. csr = LMC_CSR_READ (sc, csr_status);
  1029. /*
  1030. * Make sure this is our interrupt
  1031. */
  1032. if ( ! (csr & sc->lmc_intrmask)) {
  1033. goto lmc_int_fail_out;
  1034. }
  1035. firstcsr = csr;
  1036. /* always go through this loop at least once */
  1037. while (csr & sc->lmc_intrmask) {
  1038. handled = 1;
  1039. /*
  1040. * Clear interrupt bits, we handle all case below
  1041. */
  1042. LMC_CSR_WRITE (sc, csr_status, csr);
  1043. /*
  1044. * One of
  1045. * - Transmit process timed out CSR5<1>
  1046. * - Transmit jabber timeout CSR5<3>
  1047. * - Transmit underflow CSR5<5>
  1048. * - Transmit Receiver buffer unavailable CSR5<7>
  1049. * - Receive process stopped CSR5<8>
  1050. * - Receive watchdog timeout CSR5<9>
  1051. * - Early transmit interrupt CSR5<10>
  1052. *
  1053. * Is this really right? Should we do a running reset for jabber?
  1054. * (being a WAN card and all)
  1055. */
  1056. if (csr & TULIP_STS_ABNRMLINTR){
  1057. lmc_running_reset (dev);
  1058. break;
  1059. }
  1060. if (csr & TULIP_STS_RXINTR){
  1061. lmc_trace(dev, "rx interrupt");
  1062. lmc_rx (dev);
  1063. }
  1064. if (csr & (TULIP_STS_TXINTR | TULIP_STS_TXNOBUF | TULIP_STS_TXSTOPPED)) {
  1065. int n_compl = 0 ;
  1066. /* reset the transmit timeout detection flag -baz */
  1067. sc->extra_stats.tx_NoCompleteCnt = 0;
  1068. badtx = sc->lmc_taint_tx;
  1069. i = badtx % LMC_TXDESCS;
  1070. while ((badtx < sc->lmc_next_tx)) {
  1071. stat = sc->lmc_txring[i].status;
  1072. LMC_EVENT_LOG (LMC_EVENT_XMTINT, stat,
  1073. sc->lmc_txring[i].length);
  1074. /*
  1075. * If bit 31 is 1 the tulip owns it break out of the loop
  1076. */
  1077. if (stat & 0x80000000)
  1078. break;
  1079. n_compl++ ; /* i.e., have an empty slot in ring */
  1080. /*
  1081. * If we have no skbuff or have cleared it
  1082. * Already continue to the next buffer
  1083. */
  1084. if (sc->lmc_txq[i] == NULL)
  1085. continue;
  1086. /*
  1087. * Check the total error summary to look for any errors
  1088. */
  1089. if (stat & 0x8000) {
  1090. sc->lmc_device->stats.tx_errors++;
  1091. if (stat & 0x4104)
  1092. sc->lmc_device->stats.tx_aborted_errors++;
  1093. if (stat & 0x0C00)
  1094. sc->lmc_device->stats.tx_carrier_errors++;
  1095. if (stat & 0x0200)
  1096. sc->lmc_device->stats.tx_window_errors++;
  1097. if (stat & 0x0002)
  1098. sc->lmc_device->stats.tx_fifo_errors++;
  1099. } else {
  1100. sc->lmc_device->stats.tx_bytes += sc->lmc_txring[i].length & 0x7ff;
  1101. sc->lmc_device->stats.tx_packets++;
  1102. }
  1103. // dev_kfree_skb(sc->lmc_txq[i]);
  1104. dev_kfree_skb_irq(sc->lmc_txq[i]);
  1105. sc->lmc_txq[i] = NULL;
  1106. badtx++;
  1107. i = badtx % LMC_TXDESCS;
  1108. }
  1109. if (sc->lmc_next_tx - badtx > LMC_TXDESCS)
  1110. {
  1111. printk ("%s: out of sync pointer\n", dev->name);
  1112. badtx += LMC_TXDESCS;
  1113. }
  1114. LMC_EVENT_LOG(LMC_EVENT_TBUSY0, n_compl, 0);
  1115. sc->lmc_txfull = 0;
  1116. netif_wake_queue(dev);
  1117. sc->extra_stats.tx_tbusy0++;
  1118. #ifdef DEBUG
  1119. sc->extra_stats.dirtyTx = badtx;
  1120. sc->extra_stats.lmc_next_tx = sc->lmc_next_tx;
  1121. sc->extra_stats.lmc_txfull = sc->lmc_txfull;
  1122. #endif
  1123. sc->lmc_taint_tx = badtx;
  1124. /*
  1125. * Why was there a break here???
  1126. */
  1127. } /* end handle transmit interrupt */
  1128. if (csr & TULIP_STS_SYSERROR) {
  1129. u32 error;
  1130. printk (KERN_WARNING "%s: system bus error csr: %#8.8x\n", dev->name, csr);
  1131. error = csr>>23 & 0x7;
  1132. switch(error){
  1133. case 0x000:
  1134. printk(KERN_WARNING "%s: Parity Fault (bad)\n", dev->name);
  1135. break;
  1136. case 0x001:
  1137. printk(KERN_WARNING "%s: Master Abort (naughty)\n", dev->name);
  1138. break;
  1139. case 0x010:
  1140. printk(KERN_WARNING "%s: Target Abort (not so naughty)\n", dev->name);
  1141. break;
  1142. default:
  1143. printk(KERN_WARNING "%s: This bus error code was supposed to be reserved!\n", dev->name);
  1144. }
  1145. lmc_dec_reset (sc);
  1146. lmc_reset (sc);
  1147. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1148. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1149. lmc_mii_readreg (sc, 0, 16),
  1150. lmc_mii_readreg (sc, 0, 17));
  1151. }
  1152. if(max_work-- <= 0)
  1153. break;
  1154. /*
  1155. * Get current csr status to make sure
  1156. * we've cleared all interrupts
  1157. */
  1158. csr = LMC_CSR_READ (sc, csr_status);
  1159. } /* end interrupt loop */
  1160. LMC_EVENT_LOG(LMC_EVENT_INT, firstcsr, csr);
  1161. lmc_int_fail_out:
  1162. spin_unlock(&sc->lmc_lock);
  1163. lmc_trace(dev, "lmc_interrupt out");
  1164. return IRQ_RETVAL(handled);
  1165. }
  1166. static netdev_tx_t lmc_start_xmit(struct sk_buff *skb,
  1167. struct net_device *dev)
  1168. {
  1169. lmc_softc_t *sc = dev_to_sc(dev);
  1170. u32 flag;
  1171. int entry;
  1172. unsigned long flags;
  1173. lmc_trace(dev, "lmc_start_xmit in");
  1174. spin_lock_irqsave(&sc->lmc_lock, flags);
  1175. /* normal path, tbusy known to be zero */
  1176. entry = sc->lmc_next_tx % LMC_TXDESCS;
  1177. sc->lmc_txq[entry] = skb;
  1178. sc->lmc_txring[entry].buffer1 = virt_to_bus (skb->data);
  1179. LMC_CONSOLE_LOG("xmit", skb->data, skb->len);
  1180. #ifndef GCOM
  1181. /* If the queue is less than half full, don't interrupt */
  1182. if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS / 2)
  1183. {
  1184. /* Do not interrupt on completion of this packet */
  1185. flag = 0x60000000;
  1186. netif_wake_queue(dev);
  1187. }
  1188. else if (sc->lmc_next_tx - sc->lmc_taint_tx == LMC_TXDESCS / 2)
  1189. {
  1190. /* This generates an interrupt on completion of this packet */
  1191. flag = 0xe0000000;
  1192. netif_wake_queue(dev);
  1193. }
  1194. else if (sc->lmc_next_tx - sc->lmc_taint_tx < LMC_TXDESCS - 1)
  1195. {
  1196. /* Do not interrupt on completion of this packet */
  1197. flag = 0x60000000;
  1198. netif_wake_queue(dev);
  1199. }
  1200. else
  1201. {
  1202. /* This generates an interrupt on completion of this packet */
  1203. flag = 0xe0000000;
  1204. sc->lmc_txfull = 1;
  1205. netif_stop_queue(dev);
  1206. }
  1207. #else
  1208. flag = LMC_TDES_INTERRUPT_ON_COMPLETION;
  1209. if (sc->lmc_next_tx - sc->lmc_taint_tx >= LMC_TXDESCS - 1)
  1210. { /* ring full, go busy */
  1211. sc->lmc_txfull = 1;
  1212. netif_stop_queue(dev);
  1213. sc->extra_stats.tx_tbusy1++;
  1214. LMC_EVENT_LOG(LMC_EVENT_TBUSY1, entry, 0);
  1215. }
  1216. #endif
  1217. if (entry == LMC_TXDESCS - 1) /* last descriptor in ring */
  1218. flag |= LMC_TDES_END_OF_RING; /* flag as such for Tulip */
  1219. /* don't pad small packets either */
  1220. flag = sc->lmc_txring[entry].length = (skb->len) | flag |
  1221. sc->TxDescriptControlInit;
  1222. /* set the transmit timeout flag to be checked in
  1223. * the watchdog timer handler. -baz
  1224. */
  1225. sc->extra_stats.tx_NoCompleteCnt++;
  1226. sc->lmc_next_tx++;
  1227. /* give ownership to the chip */
  1228. LMC_EVENT_LOG(LMC_EVENT_XMT, flag, entry);
  1229. sc->lmc_txring[entry].status = 0x80000000;
  1230. /* send now! */
  1231. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1232. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1233. lmc_trace(dev, "lmc_start_xmit_out");
  1234. return NETDEV_TX_OK;
  1235. }
  1236. static int lmc_rx(struct net_device *dev)
  1237. {
  1238. lmc_softc_t *sc = dev_to_sc(dev);
  1239. int i;
  1240. int rx_work_limit = LMC_RXDESCS;
  1241. unsigned int next_rx;
  1242. int rxIntLoopCnt; /* debug -baz */
  1243. int localLengthErrCnt = 0;
  1244. long stat;
  1245. struct sk_buff *skb, *nsb;
  1246. u16 len;
  1247. lmc_trace(dev, "lmc_rx in");
  1248. lmc_led_on(sc, LMC_DS3_LED3);
  1249. rxIntLoopCnt = 0; /* debug -baz */
  1250. i = sc->lmc_next_rx % LMC_RXDESCS;
  1251. next_rx = sc->lmc_next_rx;
  1252. while (((stat = sc->lmc_rxring[i].status) & LMC_RDES_OWN_BIT) != DESC_OWNED_BY_DC21X4)
  1253. {
  1254. rxIntLoopCnt++; /* debug -baz */
  1255. len = ((stat & LMC_RDES_FRAME_LENGTH) >> RDES_FRAME_LENGTH_BIT_NUMBER);
  1256. if ((stat & 0x0300) != 0x0300) { /* Check first segment and last segment */
  1257. if ((stat & 0x0000ffff) != 0x7fff) {
  1258. /* Oversized frame */
  1259. sc->lmc_device->stats.rx_length_errors++;
  1260. goto skip_packet;
  1261. }
  1262. }
  1263. if (stat & 0x00000008) { /* Catch a dribbling bit error */
  1264. sc->lmc_device->stats.rx_errors++;
  1265. sc->lmc_device->stats.rx_frame_errors++;
  1266. goto skip_packet;
  1267. }
  1268. if (stat & 0x00000004) { /* Catch a CRC error by the Xilinx */
  1269. sc->lmc_device->stats.rx_errors++;
  1270. sc->lmc_device->stats.rx_crc_errors++;
  1271. goto skip_packet;
  1272. }
  1273. if (len > LMC_PKT_BUF_SZ) {
  1274. sc->lmc_device->stats.rx_length_errors++;
  1275. localLengthErrCnt++;
  1276. goto skip_packet;
  1277. }
  1278. if (len < sc->lmc_crcSize + 2) {
  1279. sc->lmc_device->stats.rx_length_errors++;
  1280. sc->extra_stats.rx_SmallPktCnt++;
  1281. localLengthErrCnt++;
  1282. goto skip_packet;
  1283. }
  1284. if(stat & 0x00004000){
  1285. printk(KERN_WARNING "%s: Receiver descriptor error, receiver out of sync?\n", dev->name);
  1286. }
  1287. len -= sc->lmc_crcSize;
  1288. skb = sc->lmc_rxq[i];
  1289. /*
  1290. * We ran out of memory at some point
  1291. * just allocate an skb buff and continue.
  1292. */
  1293. if (!skb) {
  1294. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1295. if (nsb) {
  1296. sc->lmc_rxq[i] = nsb;
  1297. nsb->dev = dev;
  1298. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1299. }
  1300. sc->failed_recv_alloc = 1;
  1301. goto skip_packet;
  1302. }
  1303. sc->lmc_device->stats.rx_packets++;
  1304. sc->lmc_device->stats.rx_bytes += len;
  1305. LMC_CONSOLE_LOG("recv", skb->data, len);
  1306. /*
  1307. * I'm not sure of the sanity of this
  1308. * Packets could be arriving at a constant
  1309. * 44.210mbits/sec and we're going to copy
  1310. * them into a new buffer??
  1311. */
  1312. if(len > (LMC_MTU - (LMC_MTU>>2))){ /* len > LMC_MTU * 0.75 */
  1313. /*
  1314. * If it's a large packet don't copy it just hand it up
  1315. */
  1316. give_it_anyways:
  1317. sc->lmc_rxq[i] = NULL;
  1318. sc->lmc_rxring[i].buffer1 = 0x0;
  1319. skb_put (skb, len);
  1320. skb->protocol = lmc_proto_type(sc, skb);
  1321. skb_reset_mac_header(skb);
  1322. /* skb_reset_network_header(skb); */
  1323. skb->dev = dev;
  1324. lmc_proto_netif(sc, skb);
  1325. /*
  1326. * This skb will be destroyed by the upper layers, make a new one
  1327. */
  1328. nsb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1329. if (nsb) {
  1330. sc->lmc_rxq[i] = nsb;
  1331. nsb->dev = dev;
  1332. sc->lmc_rxring[i].buffer1 = virt_to_bus(skb_tail_pointer(nsb));
  1333. /* Transferred to 21140 below */
  1334. }
  1335. else {
  1336. /*
  1337. * We've run out of memory, stop trying to allocate
  1338. * memory and exit the interrupt handler
  1339. *
  1340. * The chip may run out of receivers and stop
  1341. * in which care we'll try to allocate the buffer
  1342. * again. (once a second)
  1343. */
  1344. sc->extra_stats.rx_BuffAllocErr++;
  1345. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1346. sc->failed_recv_alloc = 1;
  1347. goto skip_out_of_mem;
  1348. }
  1349. }
  1350. else {
  1351. nsb = dev_alloc_skb(len);
  1352. if(!nsb) {
  1353. goto give_it_anyways;
  1354. }
  1355. skb_copy_from_linear_data(skb, skb_put(nsb, len), len);
  1356. nsb->protocol = lmc_proto_type(sc, nsb);
  1357. skb_reset_mac_header(nsb);
  1358. /* skb_reset_network_header(nsb); */
  1359. nsb->dev = dev;
  1360. lmc_proto_netif(sc, nsb);
  1361. }
  1362. skip_packet:
  1363. LMC_EVENT_LOG(LMC_EVENT_RCVINT, stat, len);
  1364. sc->lmc_rxring[i].status = DESC_OWNED_BY_DC21X4;
  1365. sc->lmc_next_rx++;
  1366. i = sc->lmc_next_rx % LMC_RXDESCS;
  1367. rx_work_limit--;
  1368. if (rx_work_limit < 0)
  1369. break;
  1370. }
  1371. /* detect condition for LMC1000 where DSU cable attaches and fills
  1372. * descriptors with bogus packets
  1373. *
  1374. if (localLengthErrCnt > LMC_RXDESCS - 3) {
  1375. sc->extra_stats.rx_BadPktSurgeCnt++;
  1376. LMC_EVENT_LOG(LMC_EVENT_BADPKTSURGE, localLengthErrCnt,
  1377. sc->extra_stats.rx_BadPktSurgeCnt);
  1378. } */
  1379. /* save max count of receive descriptors serviced */
  1380. if (rxIntLoopCnt > sc->extra_stats.rxIntLoopCnt)
  1381. sc->extra_stats.rxIntLoopCnt = rxIntLoopCnt; /* debug -baz */
  1382. #ifdef DEBUG
  1383. if (rxIntLoopCnt == 0)
  1384. {
  1385. for (i = 0; i < LMC_RXDESCS; i++)
  1386. {
  1387. if ((sc->lmc_rxring[i].status & LMC_RDES_OWN_BIT)
  1388. != DESC_OWNED_BY_DC21X4)
  1389. {
  1390. rxIntLoopCnt++;
  1391. }
  1392. }
  1393. LMC_EVENT_LOG(LMC_EVENT_RCVEND, rxIntLoopCnt, 0);
  1394. }
  1395. #endif
  1396. lmc_led_off(sc, LMC_DS3_LED3);
  1397. skip_out_of_mem:
  1398. lmc_trace(dev, "lmc_rx out");
  1399. return 0;
  1400. }
  1401. static struct net_device_stats *lmc_get_stats(struct net_device *dev)
  1402. {
  1403. lmc_softc_t *sc = dev_to_sc(dev);
  1404. unsigned long flags;
  1405. lmc_trace(dev, "lmc_get_stats in");
  1406. spin_lock_irqsave(&sc->lmc_lock, flags);
  1407. sc->lmc_device->stats.rx_missed_errors += LMC_CSR_READ(sc, csr_missed_frames) & 0xffff;
  1408. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1409. lmc_trace(dev, "lmc_get_stats out");
  1410. return &sc->lmc_device->stats;
  1411. }
  1412. static struct pci_driver lmc_driver = {
  1413. .name = "lmc",
  1414. .id_table = lmc_pci_tbl,
  1415. .probe = lmc_init_one,
  1416. .remove = lmc_remove_one,
  1417. };
  1418. module_pci_driver(lmc_driver);
  1419. unsigned lmc_mii_readreg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno) /*fold00*/
  1420. {
  1421. int i;
  1422. int command = (0xf6 << 10) | (devaddr << 5) | regno;
  1423. int retval = 0;
  1424. lmc_trace(sc->lmc_device, "lmc_mii_readreg in");
  1425. LMC_MII_SYNC (sc);
  1426. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done sync");
  1427. for (i = 15; i >= 0; i--)
  1428. {
  1429. int dataval = (command & (1 << i)) ? 0x20000 : 0;
  1430. LMC_CSR_WRITE (sc, csr_9, dataval);
  1431. lmc_delay ();
  1432. /* __SLOW_DOWN_IO; */
  1433. LMC_CSR_WRITE (sc, csr_9, dataval | 0x10000);
  1434. lmc_delay ();
  1435. /* __SLOW_DOWN_IO; */
  1436. }
  1437. lmc_trace(sc->lmc_device, "lmc_mii_readreg: done1");
  1438. for (i = 19; i > 0; i--)
  1439. {
  1440. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1441. lmc_delay ();
  1442. /* __SLOW_DOWN_IO; */
  1443. retval = (retval << 1) | ((LMC_CSR_READ (sc, csr_9) & 0x80000) ? 1 : 0);
  1444. LMC_CSR_WRITE (sc, csr_9, 0x40000 | 0x10000);
  1445. lmc_delay ();
  1446. /* __SLOW_DOWN_IO; */
  1447. }
  1448. lmc_trace(sc->lmc_device, "lmc_mii_readreg out");
  1449. return (retval >> 1) & 0xffff;
  1450. }
  1451. void lmc_mii_writereg (lmc_softc_t * const sc, unsigned devaddr, unsigned regno, unsigned data) /*fold00*/
  1452. {
  1453. int i = 32;
  1454. int command = (0x5002 << 16) | (devaddr << 23) | (regno << 18) | data;
  1455. lmc_trace(sc->lmc_device, "lmc_mii_writereg in");
  1456. LMC_MII_SYNC (sc);
  1457. i = 31;
  1458. while (i >= 0)
  1459. {
  1460. int datav;
  1461. if (command & (1 << i))
  1462. datav = 0x20000;
  1463. else
  1464. datav = 0x00000;
  1465. LMC_CSR_WRITE (sc, csr_9, datav);
  1466. lmc_delay ();
  1467. /* __SLOW_DOWN_IO; */
  1468. LMC_CSR_WRITE (sc, csr_9, (datav | 0x10000));
  1469. lmc_delay ();
  1470. /* __SLOW_DOWN_IO; */
  1471. i--;
  1472. }
  1473. i = 2;
  1474. while (i > 0)
  1475. {
  1476. LMC_CSR_WRITE (sc, csr_9, 0x40000);
  1477. lmc_delay ();
  1478. /* __SLOW_DOWN_IO; */
  1479. LMC_CSR_WRITE (sc, csr_9, 0x50000);
  1480. lmc_delay ();
  1481. /* __SLOW_DOWN_IO; */
  1482. i--;
  1483. }
  1484. lmc_trace(sc->lmc_device, "lmc_mii_writereg out");
  1485. }
  1486. static void lmc_softreset (lmc_softc_t * const sc) /*fold00*/
  1487. {
  1488. int i;
  1489. lmc_trace(sc->lmc_device, "lmc_softreset in");
  1490. /* Initialize the receive rings and buffers. */
  1491. sc->lmc_txfull = 0;
  1492. sc->lmc_next_rx = 0;
  1493. sc->lmc_next_tx = 0;
  1494. sc->lmc_taint_rx = 0;
  1495. sc->lmc_taint_tx = 0;
  1496. /*
  1497. * Setup each one of the receiver buffers
  1498. * allocate an skbuff for each one, setup the descriptor table
  1499. * and point each buffer at the next one
  1500. */
  1501. for (i = 0; i < LMC_RXDESCS; i++)
  1502. {
  1503. struct sk_buff *skb;
  1504. if (sc->lmc_rxq[i] == NULL)
  1505. {
  1506. skb = dev_alloc_skb (LMC_PKT_BUF_SZ + 2);
  1507. if(skb == NULL){
  1508. printk(KERN_WARNING "%s: Failed to allocate receiver ring, will try again\n", sc->name);
  1509. sc->failed_ring = 1;
  1510. break;
  1511. }
  1512. else{
  1513. sc->lmc_rxq[i] = skb;
  1514. }
  1515. }
  1516. else
  1517. {
  1518. skb = sc->lmc_rxq[i];
  1519. }
  1520. skb->dev = sc->lmc_device;
  1521. /* owned by 21140 */
  1522. sc->lmc_rxring[i].status = 0x80000000;
  1523. /* used to be PKT_BUF_SZ now uses skb since we lose some to head room */
  1524. sc->lmc_rxring[i].length = skb_tailroom(skb);
  1525. /* use to be tail which is dumb since you're thinking why write
  1526. * to the end of the packj,et but since there's nothing there tail == data
  1527. */
  1528. sc->lmc_rxring[i].buffer1 = virt_to_bus (skb->data);
  1529. /* This is fair since the structure is static and we have the next address */
  1530. sc->lmc_rxring[i].buffer2 = virt_to_bus (&sc->lmc_rxring[i + 1]);
  1531. }
  1532. /*
  1533. * Sets end of ring
  1534. */
  1535. if (i != 0) {
  1536. sc->lmc_rxring[i - 1].length |= 0x02000000; /* Set end of buffers flag */
  1537. sc->lmc_rxring[i - 1].buffer2 = virt_to_bus(&sc->lmc_rxring[0]); /* Point back to the start */
  1538. }
  1539. LMC_CSR_WRITE (sc, csr_rxlist, virt_to_bus (sc->lmc_rxring)); /* write base address */
  1540. /* Initialize the transmit rings and buffers */
  1541. for (i = 0; i < LMC_TXDESCS; i++)
  1542. {
  1543. if (sc->lmc_txq[i] != NULL){ /* have buffer */
  1544. dev_kfree_skb(sc->lmc_txq[i]); /* free it */
  1545. sc->lmc_device->stats.tx_dropped++; /* We just dropped a packet */
  1546. }
  1547. sc->lmc_txq[i] = NULL;
  1548. sc->lmc_txring[i].status = 0x00000000;
  1549. sc->lmc_txring[i].buffer2 = virt_to_bus (&sc->lmc_txring[i + 1]);
  1550. }
  1551. sc->lmc_txring[i - 1].buffer2 = virt_to_bus (&sc->lmc_txring[0]);
  1552. LMC_CSR_WRITE (sc, csr_txlist, virt_to_bus (sc->lmc_txring));
  1553. lmc_trace(sc->lmc_device, "lmc_softreset out");
  1554. }
  1555. void lmc_gpio_mkinput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1556. {
  1557. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput in");
  1558. sc->lmc_gpio_io &= ~bits;
  1559. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1560. lmc_trace(sc->lmc_device, "lmc_gpio_mkinput out");
  1561. }
  1562. void lmc_gpio_mkoutput(lmc_softc_t * const sc, u32 bits) /*fold00*/
  1563. {
  1564. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput in");
  1565. sc->lmc_gpio_io |= bits;
  1566. LMC_CSR_WRITE(sc, csr_gp, TULIP_GP_PINSET | (sc->lmc_gpio_io));
  1567. lmc_trace(sc->lmc_device, "lmc_gpio_mkoutput out");
  1568. }
  1569. void lmc_led_on(lmc_softc_t * const sc, u32 led) /*fold00*/
  1570. {
  1571. lmc_trace(sc->lmc_device, "lmc_led_on in");
  1572. if((~sc->lmc_miireg16) & led){ /* Already on! */
  1573. lmc_trace(sc->lmc_device, "lmc_led_on aon out");
  1574. return;
  1575. }
  1576. sc->lmc_miireg16 &= ~led;
  1577. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1578. lmc_trace(sc->lmc_device, "lmc_led_on out");
  1579. }
  1580. void lmc_led_off(lmc_softc_t * const sc, u32 led) /*fold00*/
  1581. {
  1582. lmc_trace(sc->lmc_device, "lmc_led_off in");
  1583. if(sc->lmc_miireg16 & led){ /* Already set don't do anything */
  1584. lmc_trace(sc->lmc_device, "lmc_led_off aoff out");
  1585. return;
  1586. }
  1587. sc->lmc_miireg16 |= led;
  1588. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1589. lmc_trace(sc->lmc_device, "lmc_led_off out");
  1590. }
  1591. static void lmc_reset(lmc_softc_t * const sc) /*fold00*/
  1592. {
  1593. lmc_trace(sc->lmc_device, "lmc_reset in");
  1594. sc->lmc_miireg16 |= LMC_MII16_FIFO_RESET;
  1595. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1596. sc->lmc_miireg16 &= ~LMC_MII16_FIFO_RESET;
  1597. lmc_mii_writereg(sc, 0, 16, sc->lmc_miireg16);
  1598. /*
  1599. * make some of the GPIO pins be outputs
  1600. */
  1601. lmc_gpio_mkoutput(sc, LMC_GEP_RESET);
  1602. /*
  1603. * RESET low to force state reset. This also forces
  1604. * the transmitter clock to be internal, but we expect to reset
  1605. * that later anyway.
  1606. */
  1607. sc->lmc_gpio &= ~(LMC_GEP_RESET);
  1608. LMC_CSR_WRITE(sc, csr_gp, sc->lmc_gpio);
  1609. /*
  1610. * hold for more than 10 microseconds
  1611. */
  1612. udelay(50);
  1613. /*
  1614. * stop driving Xilinx-related signals
  1615. */
  1616. lmc_gpio_mkinput(sc, LMC_GEP_RESET);
  1617. /*
  1618. * Call media specific init routine
  1619. */
  1620. sc->lmc_media->init(sc);
  1621. sc->extra_stats.resetCount++;
  1622. lmc_trace(sc->lmc_device, "lmc_reset out");
  1623. }
  1624. static void lmc_dec_reset(lmc_softc_t * const sc) /*fold00*/
  1625. {
  1626. u32 val;
  1627. lmc_trace(sc->lmc_device, "lmc_dec_reset in");
  1628. /*
  1629. * disable all interrupts
  1630. */
  1631. sc->lmc_intrmask = 0;
  1632. LMC_CSR_WRITE(sc, csr_intr, sc->lmc_intrmask);
  1633. /*
  1634. * Reset the chip with a software reset command.
  1635. * Wait 10 microseconds (actually 50 PCI cycles but at
  1636. * 33MHz that comes to two microseconds but wait a
  1637. * bit longer anyways)
  1638. */
  1639. LMC_CSR_WRITE(sc, csr_busmode, TULIP_BUSMODE_SWRESET);
  1640. udelay(25);
  1641. #ifdef __sparc__
  1642. sc->lmc_busmode = LMC_CSR_READ(sc, csr_busmode);
  1643. sc->lmc_busmode = 0x00100000;
  1644. sc->lmc_busmode &= ~TULIP_BUSMODE_SWRESET;
  1645. LMC_CSR_WRITE(sc, csr_busmode, sc->lmc_busmode);
  1646. #endif
  1647. sc->lmc_cmdmode = LMC_CSR_READ(sc, csr_command);
  1648. /*
  1649. * We want:
  1650. * no ethernet address in frames we write
  1651. * disable padding (txdesc, padding disable)
  1652. * ignore runt frames (rdes0 bit 15)
  1653. * no receiver watchdog or transmitter jabber timer
  1654. * (csr15 bit 0,14 == 1)
  1655. * if using 16-bit CRC, turn off CRC (trans desc, crc disable)
  1656. */
  1657. sc->lmc_cmdmode |= ( TULIP_CMD_PROMISCUOUS
  1658. | TULIP_CMD_FULLDUPLEX
  1659. | TULIP_CMD_PASSBADPKT
  1660. | TULIP_CMD_NOHEARTBEAT
  1661. | TULIP_CMD_PORTSELECT
  1662. | TULIP_CMD_RECEIVEALL
  1663. | TULIP_CMD_MUSTBEONE
  1664. );
  1665. sc->lmc_cmdmode &= ~( TULIP_CMD_OPERMODE
  1666. | TULIP_CMD_THRESHOLDCTL
  1667. | TULIP_CMD_STOREFWD
  1668. | TULIP_CMD_TXTHRSHLDCTL
  1669. );
  1670. LMC_CSR_WRITE(sc, csr_command, sc->lmc_cmdmode);
  1671. /*
  1672. * disable receiver watchdog and transmit jabber
  1673. */
  1674. val = LMC_CSR_READ(sc, csr_sia_general);
  1675. val |= (TULIP_WATCHDOG_TXDISABLE | TULIP_WATCHDOG_RXDISABLE);
  1676. LMC_CSR_WRITE(sc, csr_sia_general, val);
  1677. lmc_trace(sc->lmc_device, "lmc_dec_reset out");
  1678. }
  1679. static void lmc_initcsrs(lmc_softc_t * const sc, lmc_csrptr_t csr_base, /*fold00*/
  1680. size_t csr_size)
  1681. {
  1682. lmc_trace(sc->lmc_device, "lmc_initcsrs in");
  1683. sc->lmc_csrs.csr_busmode = csr_base + 0 * csr_size;
  1684. sc->lmc_csrs.csr_txpoll = csr_base + 1 * csr_size;
  1685. sc->lmc_csrs.csr_rxpoll = csr_base + 2 * csr_size;
  1686. sc->lmc_csrs.csr_rxlist = csr_base + 3 * csr_size;
  1687. sc->lmc_csrs.csr_txlist = csr_base + 4 * csr_size;
  1688. sc->lmc_csrs.csr_status = csr_base + 5 * csr_size;
  1689. sc->lmc_csrs.csr_command = csr_base + 6 * csr_size;
  1690. sc->lmc_csrs.csr_intr = csr_base + 7 * csr_size;
  1691. sc->lmc_csrs.csr_missed_frames = csr_base + 8 * csr_size;
  1692. sc->lmc_csrs.csr_9 = csr_base + 9 * csr_size;
  1693. sc->lmc_csrs.csr_10 = csr_base + 10 * csr_size;
  1694. sc->lmc_csrs.csr_11 = csr_base + 11 * csr_size;
  1695. sc->lmc_csrs.csr_12 = csr_base + 12 * csr_size;
  1696. sc->lmc_csrs.csr_13 = csr_base + 13 * csr_size;
  1697. sc->lmc_csrs.csr_14 = csr_base + 14 * csr_size;
  1698. sc->lmc_csrs.csr_15 = csr_base + 15 * csr_size;
  1699. lmc_trace(sc->lmc_device, "lmc_initcsrs out");
  1700. }
  1701. static void lmc_driver_timeout(struct net_device *dev)
  1702. {
  1703. lmc_softc_t *sc = dev_to_sc(dev);
  1704. u32 csr6;
  1705. unsigned long flags;
  1706. lmc_trace(dev, "lmc_driver_timeout in");
  1707. spin_lock_irqsave(&sc->lmc_lock, flags);
  1708. printk("%s: Xmitter busy|\n", dev->name);
  1709. sc->extra_stats.tx_tbusy_calls++;
  1710. if (jiffies - dev_trans_start(dev) < TX_TIMEOUT)
  1711. goto bug_out;
  1712. /*
  1713. * Chip seems to have locked up
  1714. * Reset it
  1715. * This whips out all our decriptor
  1716. * table and starts from scartch
  1717. */
  1718. LMC_EVENT_LOG(LMC_EVENT_XMTPRCTMO,
  1719. LMC_CSR_READ (sc, csr_status),
  1720. sc->extra_stats.tx_ProcTimeout);
  1721. lmc_running_reset (dev);
  1722. LMC_EVENT_LOG(LMC_EVENT_RESET1, LMC_CSR_READ (sc, csr_status), 0);
  1723. LMC_EVENT_LOG(LMC_EVENT_RESET2,
  1724. lmc_mii_readreg (sc, 0, 16),
  1725. lmc_mii_readreg (sc, 0, 17));
  1726. /* restart the tx processes */
  1727. csr6 = LMC_CSR_READ (sc, csr_command);
  1728. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x0002);
  1729. LMC_CSR_WRITE (sc, csr_command, csr6 | 0x2002);
  1730. /* immediate transmit */
  1731. LMC_CSR_WRITE (sc, csr_txpoll, 0);
  1732. sc->lmc_device->stats.tx_errors++;
  1733. sc->extra_stats.tx_ProcTimeout++; /* -baz */
  1734. dev->trans_start = jiffies; /* prevent tx timeout */
  1735. bug_out:
  1736. spin_unlock_irqrestore(&sc->lmc_lock, flags);
  1737. lmc_trace(dev, "lmc_driver_timeout out");
  1738. }