smsc911x.c 70 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. *
  19. ***************************************************************************
  20. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  21. * Partly uses io macros from smc91x.c by Nicolas Pitre
  22. *
  23. * Supported devices:
  24. * LAN9115, LAN9116, LAN9117, LAN9118
  25. * LAN9215, LAN9216, LAN9217, LAN9218
  26. * LAN9210, LAN9211
  27. * LAN9220, LAN9221
  28. * LAN89218
  29. *
  30. */
  31. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  32. #include <linux/crc32.h>
  33. #include <linux/clk.h>
  34. #include <linux/delay.h>
  35. #include <linux/errno.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/init.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/ioport.h>
  41. #include <linux/kernel.h>
  42. #include <linux/module.h>
  43. #include <linux/netdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/regulator/consumer.h>
  46. #include <linux/sched.h>
  47. #include <linux/timer.h>
  48. #include <linux/bug.h>
  49. #include <linux/bitops.h>
  50. #include <linux/irq.h>
  51. #include <linux/io.h>
  52. #include <linux/swab.h>
  53. #include <linux/phy.h>
  54. #include <linux/smsc911x.h>
  55. #include <linux/device.h>
  56. #include <linux/of.h>
  57. #include <linux/of_device.h>
  58. #include <linux/of_gpio.h>
  59. #include <linux/of_net.h>
  60. #include <linux/pm_runtime.h>
  61. #include "smsc911x.h"
  62. #define SMSC_CHIPNAME "smsc911x"
  63. #define SMSC_MDIONAME "smsc911x-mdio"
  64. #define SMSC_DRV_VERSION "2008-10-21"
  65. MODULE_LICENSE("GPL");
  66. MODULE_VERSION(SMSC_DRV_VERSION);
  67. MODULE_ALIAS("platform:smsc911x");
  68. #if USE_DEBUG > 0
  69. static int debug = 16;
  70. #else
  71. static int debug = 3;
  72. #endif
  73. module_param(debug, int, 0);
  74. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  75. struct smsc911x_data;
  76. struct smsc911x_ops {
  77. u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
  78. void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
  79. void (*rx_readfifo)(struct smsc911x_data *pdata,
  80. unsigned int *buf, unsigned int wordcount);
  81. void (*tx_writefifo)(struct smsc911x_data *pdata,
  82. unsigned int *buf, unsigned int wordcount);
  83. };
  84. #define SMSC911X_NUM_SUPPLIES 2
  85. struct smsc911x_data {
  86. void __iomem *ioaddr;
  87. unsigned int idrev;
  88. /* used to decide which workarounds apply */
  89. unsigned int generation;
  90. /* device configuration (copied from platform_data during probe) */
  91. struct smsc911x_platform_config config;
  92. /* This needs to be acquired before calling any of below:
  93. * smsc911x_mac_read(), smsc911x_mac_write()
  94. */
  95. spinlock_t mac_lock;
  96. /* spinlock to ensure register accesses are serialised */
  97. spinlock_t dev_lock;
  98. struct phy_device *phy_dev;
  99. struct mii_bus *mii_bus;
  100. int phy_irq[PHY_MAX_ADDR];
  101. unsigned int using_extphy;
  102. int last_duplex;
  103. int last_carrier;
  104. u32 msg_enable;
  105. unsigned int gpio_setting;
  106. unsigned int gpio_orig_setting;
  107. struct net_device *dev;
  108. struct napi_struct napi;
  109. unsigned int software_irq_signal;
  110. #ifdef USE_PHY_WORK_AROUND
  111. #define MIN_PACKET_SIZE (64)
  112. char loopback_tx_pkt[MIN_PACKET_SIZE];
  113. char loopback_rx_pkt[MIN_PACKET_SIZE];
  114. unsigned int resetcount;
  115. #endif
  116. /* Members for Multicast filter workaround */
  117. unsigned int multicast_update_pending;
  118. unsigned int set_bits_mask;
  119. unsigned int clear_bits_mask;
  120. unsigned int hashhi;
  121. unsigned int hashlo;
  122. /* register access functions */
  123. const struct smsc911x_ops *ops;
  124. /* regulators */
  125. struct regulator_bulk_data supplies[SMSC911X_NUM_SUPPLIES];
  126. /* clock */
  127. struct clk *clk;
  128. };
  129. /* Easy access to information */
  130. #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
  131. static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  132. {
  133. if (pdata->config.flags & SMSC911X_USE_32BIT)
  134. return readl(pdata->ioaddr + reg);
  135. if (pdata->config.flags & SMSC911X_USE_16BIT)
  136. return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  137. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  138. BUG();
  139. return 0;
  140. }
  141. static inline u32
  142. __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
  143. {
  144. if (pdata->config.flags & SMSC911X_USE_32BIT)
  145. return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
  146. if (pdata->config.flags & SMSC911X_USE_16BIT)
  147. return (readw(pdata->ioaddr +
  148. __smsc_shift(pdata, reg)) & 0xFFFF) |
  149. ((readw(pdata->ioaddr +
  150. __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
  151. BUG();
  152. return 0;
  153. }
  154. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  155. {
  156. u32 data;
  157. unsigned long flags;
  158. spin_lock_irqsave(&pdata->dev_lock, flags);
  159. data = pdata->ops->reg_read(pdata, reg);
  160. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  161. return data;
  162. }
  163. static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  164. u32 val)
  165. {
  166. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  167. writel(val, pdata->ioaddr + reg);
  168. return;
  169. }
  170. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  171. writew(val & 0xFFFF, pdata->ioaddr + reg);
  172. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  173. return;
  174. }
  175. BUG();
  176. }
  177. static inline void
  178. __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
  179. {
  180. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  181. writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
  182. return;
  183. }
  184. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  185. writew(val & 0xFFFF,
  186. pdata->ioaddr + __smsc_shift(pdata, reg));
  187. writew((val >> 16) & 0xFFFF,
  188. pdata->ioaddr + __smsc_shift(pdata, reg + 2));
  189. return;
  190. }
  191. BUG();
  192. }
  193. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  194. u32 val)
  195. {
  196. unsigned long flags;
  197. spin_lock_irqsave(&pdata->dev_lock, flags);
  198. pdata->ops->reg_write(pdata, reg, val);
  199. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  200. }
  201. /* Writes a packet to the TX_DATA_FIFO */
  202. static inline void
  203. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  204. unsigned int wordcount)
  205. {
  206. unsigned long flags;
  207. spin_lock_irqsave(&pdata->dev_lock, flags);
  208. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  209. while (wordcount--)
  210. __smsc911x_reg_write(pdata, TX_DATA_FIFO,
  211. swab32(*buf++));
  212. goto out;
  213. }
  214. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  215. iowrite32_rep(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  216. goto out;
  217. }
  218. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  219. while (wordcount--)
  220. __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  221. goto out;
  222. }
  223. BUG();
  224. out:
  225. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  226. }
  227. /* Writes a packet to the TX_DATA_FIFO - shifted version */
  228. static inline void
  229. smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  230. unsigned int wordcount)
  231. {
  232. unsigned long flags;
  233. spin_lock_irqsave(&pdata->dev_lock, flags);
  234. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  235. while (wordcount--)
  236. __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
  237. swab32(*buf++));
  238. goto out;
  239. }
  240. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  241. iowrite32_rep(pdata->ioaddr + __smsc_shift(pdata,
  242. TX_DATA_FIFO), buf, wordcount);
  243. goto out;
  244. }
  245. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  246. while (wordcount--)
  247. __smsc911x_reg_write_shift(pdata,
  248. TX_DATA_FIFO, *buf++);
  249. goto out;
  250. }
  251. BUG();
  252. out:
  253. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  254. }
  255. /* Reads a packet out of the RX_DATA_FIFO */
  256. static inline void
  257. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  258. unsigned int wordcount)
  259. {
  260. unsigned long flags;
  261. spin_lock_irqsave(&pdata->dev_lock, flags);
  262. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  263. while (wordcount--)
  264. *buf++ = swab32(__smsc911x_reg_read(pdata,
  265. RX_DATA_FIFO));
  266. goto out;
  267. }
  268. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  269. ioread32_rep(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  270. goto out;
  271. }
  272. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  273. while (wordcount--)
  274. *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
  275. goto out;
  276. }
  277. BUG();
  278. out:
  279. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  280. }
  281. /* Reads a packet out of the RX_DATA_FIFO - shifted version */
  282. static inline void
  283. smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  284. unsigned int wordcount)
  285. {
  286. unsigned long flags;
  287. spin_lock_irqsave(&pdata->dev_lock, flags);
  288. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  289. while (wordcount--)
  290. *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
  291. RX_DATA_FIFO));
  292. goto out;
  293. }
  294. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  295. ioread32_rep(pdata->ioaddr + __smsc_shift(pdata,
  296. RX_DATA_FIFO), buf, wordcount);
  297. goto out;
  298. }
  299. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  300. while (wordcount--)
  301. *buf++ = __smsc911x_reg_read_shift(pdata,
  302. RX_DATA_FIFO);
  303. goto out;
  304. }
  305. BUG();
  306. out:
  307. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  308. }
  309. /*
  310. * enable regulator and clock resources.
  311. */
  312. static int smsc911x_enable_resources(struct platform_device *pdev)
  313. {
  314. struct net_device *ndev = platform_get_drvdata(pdev);
  315. struct smsc911x_data *pdata = netdev_priv(ndev);
  316. int ret = 0;
  317. ret = regulator_bulk_enable(ARRAY_SIZE(pdata->supplies),
  318. pdata->supplies);
  319. if (ret)
  320. netdev_err(ndev, "failed to enable regulators %d\n",
  321. ret);
  322. if (!IS_ERR(pdata->clk)) {
  323. ret = clk_prepare_enable(pdata->clk);
  324. if (ret < 0)
  325. netdev_err(ndev, "failed to enable clock %d\n", ret);
  326. }
  327. return ret;
  328. }
  329. /*
  330. * disable resources, currently just regulators.
  331. */
  332. static int smsc911x_disable_resources(struct platform_device *pdev)
  333. {
  334. struct net_device *ndev = platform_get_drvdata(pdev);
  335. struct smsc911x_data *pdata = netdev_priv(ndev);
  336. int ret = 0;
  337. ret = regulator_bulk_disable(ARRAY_SIZE(pdata->supplies),
  338. pdata->supplies);
  339. if (!IS_ERR(pdata->clk))
  340. clk_disable_unprepare(pdata->clk);
  341. return ret;
  342. }
  343. /*
  344. * Request resources, currently just regulators.
  345. *
  346. * The SMSC911x has two power pins: vddvario and vdd33a, in designs where
  347. * these are not always-on we need to request regulators to be turned on
  348. * before we can try to access the device registers.
  349. */
  350. static int smsc911x_request_resources(struct platform_device *pdev)
  351. {
  352. struct net_device *ndev = platform_get_drvdata(pdev);
  353. struct smsc911x_data *pdata = netdev_priv(ndev);
  354. int ret = 0;
  355. /* Request regulators */
  356. pdata->supplies[0].supply = "vdd33a";
  357. pdata->supplies[1].supply = "vddvario";
  358. ret = regulator_bulk_get(&pdev->dev,
  359. ARRAY_SIZE(pdata->supplies),
  360. pdata->supplies);
  361. if (ret)
  362. netdev_err(ndev, "couldn't get regulators %d\n",
  363. ret);
  364. /* Request clock */
  365. pdata->clk = clk_get(&pdev->dev, NULL);
  366. if (IS_ERR(pdata->clk))
  367. dev_dbg(&pdev->dev, "couldn't get clock %li\n",
  368. PTR_ERR(pdata->clk));
  369. return ret;
  370. }
  371. /*
  372. * Free resources, currently just regulators.
  373. *
  374. */
  375. static void smsc911x_free_resources(struct platform_device *pdev)
  376. {
  377. struct net_device *ndev = platform_get_drvdata(pdev);
  378. struct smsc911x_data *pdata = netdev_priv(ndev);
  379. /* Free regulators */
  380. regulator_bulk_free(ARRAY_SIZE(pdata->supplies),
  381. pdata->supplies);
  382. /* Free clock */
  383. if (!IS_ERR(pdata->clk)) {
  384. clk_put(pdata->clk);
  385. pdata->clk = NULL;
  386. }
  387. }
  388. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  389. * and smsc911x_mac_write, so assumes mac_lock is held */
  390. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  391. {
  392. int i;
  393. u32 val;
  394. SMSC_ASSERT_MAC_LOCK(pdata);
  395. for (i = 0; i < 40; i++) {
  396. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  397. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  398. return 0;
  399. }
  400. SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
  401. "MAC_CSR_CMD: 0x%08X", val);
  402. return -EIO;
  403. }
  404. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  405. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  406. {
  407. unsigned int temp;
  408. SMSC_ASSERT_MAC_LOCK(pdata);
  409. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  410. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  411. SMSC_WARN(pdata, hw, "MAC busy at entry");
  412. return 0xFFFFFFFF;
  413. }
  414. /* Send the MAC cmd */
  415. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  416. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  417. /* Workaround for hardware read-after-write restriction */
  418. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  419. /* Wait for the read to complete */
  420. if (likely(smsc911x_mac_complete(pdata) == 0))
  421. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  422. SMSC_WARN(pdata, hw, "MAC busy after read");
  423. return 0xFFFFFFFF;
  424. }
  425. /* Set a mac register, mac_lock must be acquired before calling */
  426. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  427. unsigned int offset, u32 val)
  428. {
  429. unsigned int temp;
  430. SMSC_ASSERT_MAC_LOCK(pdata);
  431. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  432. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  433. SMSC_WARN(pdata, hw,
  434. "smsc911x_mac_write failed, MAC busy at entry");
  435. return;
  436. }
  437. /* Send data to write */
  438. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  439. /* Write the actual data */
  440. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  441. MAC_CSR_CMD_CSR_BUSY_));
  442. /* Workaround for hardware read-after-write restriction */
  443. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  444. /* Wait for the write to complete */
  445. if (likely(smsc911x_mac_complete(pdata) == 0))
  446. return;
  447. SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
  448. }
  449. /* Get a phy register */
  450. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  451. {
  452. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  453. unsigned long flags;
  454. unsigned int addr;
  455. int i, reg;
  456. spin_lock_irqsave(&pdata->mac_lock, flags);
  457. /* Confirm MII not busy */
  458. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  459. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
  460. reg = -EIO;
  461. goto out;
  462. }
  463. /* Set the address, index & direction (read from PHY) */
  464. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  465. smsc911x_mac_write(pdata, MII_ACC, addr);
  466. /* Wait for read to complete w/ timeout */
  467. for (i = 0; i < 100; i++)
  468. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  469. reg = smsc911x_mac_read(pdata, MII_DATA);
  470. goto out;
  471. }
  472. SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
  473. reg = -EIO;
  474. out:
  475. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  476. return reg;
  477. }
  478. /* Set a phy register */
  479. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  480. u16 val)
  481. {
  482. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  483. unsigned long flags;
  484. unsigned int addr;
  485. int i, reg;
  486. spin_lock_irqsave(&pdata->mac_lock, flags);
  487. /* Confirm MII not busy */
  488. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  489. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
  490. reg = -EIO;
  491. goto out;
  492. }
  493. /* Put the data to write in the MAC */
  494. smsc911x_mac_write(pdata, MII_DATA, val);
  495. /* Set the address, index & direction (write to PHY) */
  496. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  497. MII_ACC_MII_WRITE_;
  498. smsc911x_mac_write(pdata, MII_ACC, addr);
  499. /* Wait for write to complete w/ timeout */
  500. for (i = 0; i < 100; i++)
  501. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  502. reg = 0;
  503. goto out;
  504. }
  505. SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
  506. reg = -EIO;
  507. out:
  508. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  509. return reg;
  510. }
  511. /* Switch to external phy. Assumes tx and rx are stopped. */
  512. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  513. {
  514. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  515. /* Disable phy clocks to the MAC */
  516. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  517. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  518. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  519. udelay(10); /* Enough time for clocks to stop */
  520. /* Switch to external phy */
  521. hwcfg |= HW_CFG_EXT_PHY_EN_;
  522. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  523. /* Enable phy clocks to the MAC */
  524. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  525. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  526. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  527. udelay(10); /* Enough time for clocks to restart */
  528. hwcfg |= HW_CFG_SMI_SEL_;
  529. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  530. }
  531. /* Autodetects and enables external phy if present on supported chips.
  532. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  533. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  534. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  535. {
  536. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  537. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  538. SMSC_TRACE(pdata, hw, "Forcing internal PHY");
  539. pdata->using_extphy = 0;
  540. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  541. SMSC_TRACE(pdata, hw, "Forcing external PHY");
  542. smsc911x_phy_enable_external(pdata);
  543. pdata->using_extphy = 1;
  544. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  545. SMSC_TRACE(pdata, hw,
  546. "HW_CFG EXT_PHY_DET set, using external PHY");
  547. smsc911x_phy_enable_external(pdata);
  548. pdata->using_extphy = 1;
  549. } else {
  550. SMSC_TRACE(pdata, hw,
  551. "HW_CFG EXT_PHY_DET clear, using internal PHY");
  552. pdata->using_extphy = 0;
  553. }
  554. }
  555. /* Fetches a tx status out of the status fifo */
  556. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  557. {
  558. unsigned int result =
  559. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  560. if (result != 0)
  561. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  562. return result;
  563. }
  564. /* Fetches the next rx status */
  565. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  566. {
  567. unsigned int result =
  568. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  569. if (result != 0)
  570. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  571. return result;
  572. }
  573. #ifdef USE_PHY_WORK_AROUND
  574. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  575. {
  576. unsigned int tries;
  577. u32 wrsz;
  578. u32 rdsz;
  579. ulong bufp;
  580. for (tries = 0; tries < 10; tries++) {
  581. unsigned int txcmd_a;
  582. unsigned int txcmd_b;
  583. unsigned int status;
  584. unsigned int pktlength;
  585. unsigned int i;
  586. /* Zero-out rx packet memory */
  587. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  588. /* Write tx packet to 118 */
  589. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  590. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  591. txcmd_a |= MIN_PACKET_SIZE;
  592. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  593. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  594. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  595. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  596. wrsz = MIN_PACKET_SIZE + 3;
  597. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  598. wrsz >>= 2;
  599. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  600. /* Wait till transmit is done */
  601. i = 60;
  602. do {
  603. udelay(5);
  604. status = smsc911x_tx_get_txstatus(pdata);
  605. } while ((i--) && (!status));
  606. if (!status) {
  607. SMSC_WARN(pdata, hw,
  608. "Failed to transmit during loopback test");
  609. continue;
  610. }
  611. if (status & TX_STS_ES_) {
  612. SMSC_WARN(pdata, hw,
  613. "Transmit encountered errors during loopback test");
  614. continue;
  615. }
  616. /* Wait till receive is done */
  617. i = 60;
  618. do {
  619. udelay(5);
  620. status = smsc911x_rx_get_rxstatus(pdata);
  621. } while ((i--) && (!status));
  622. if (!status) {
  623. SMSC_WARN(pdata, hw,
  624. "Failed to receive during loopback test");
  625. continue;
  626. }
  627. if (status & RX_STS_ES_) {
  628. SMSC_WARN(pdata, hw,
  629. "Receive encountered errors during loopback test");
  630. continue;
  631. }
  632. pktlength = ((status & 0x3FFF0000UL) >> 16);
  633. bufp = (ulong)pdata->loopback_rx_pkt;
  634. rdsz = pktlength + 3;
  635. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  636. rdsz >>= 2;
  637. pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  638. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  639. SMSC_WARN(pdata, hw, "Unexpected packet size "
  640. "during loop back test, size=%d, will retry",
  641. pktlength);
  642. } else {
  643. unsigned int j;
  644. int mismatch = 0;
  645. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  646. if (pdata->loopback_tx_pkt[j]
  647. != pdata->loopback_rx_pkt[j]) {
  648. mismatch = 1;
  649. break;
  650. }
  651. }
  652. if (!mismatch) {
  653. SMSC_TRACE(pdata, hw, "Successfully verified "
  654. "loopback packet");
  655. return 0;
  656. } else {
  657. SMSC_WARN(pdata, hw, "Data mismatch "
  658. "during loop back test, will retry");
  659. }
  660. }
  661. }
  662. return -EIO;
  663. }
  664. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  665. {
  666. struct phy_device *phy_dev = pdata->phy_dev;
  667. unsigned int temp;
  668. unsigned int i = 100000;
  669. BUG_ON(!phy_dev);
  670. BUG_ON(!phy_dev->bus);
  671. SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
  672. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  673. do {
  674. msleep(1);
  675. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  676. MII_BMCR);
  677. } while ((i--) && (temp & BMCR_RESET));
  678. if (temp & BMCR_RESET) {
  679. SMSC_WARN(pdata, hw, "PHY reset failed to complete");
  680. return -EIO;
  681. }
  682. /* Extra delay required because the phy may not be completed with
  683. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  684. * enough delay but using 1ms here to be safe */
  685. msleep(1);
  686. return 0;
  687. }
  688. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  689. {
  690. struct smsc911x_data *pdata = netdev_priv(dev);
  691. struct phy_device *phy_dev = pdata->phy_dev;
  692. int result = -EIO;
  693. unsigned int i, val;
  694. unsigned long flags;
  695. /* Initialise tx packet using broadcast destination address */
  696. eth_broadcast_addr(pdata->loopback_tx_pkt);
  697. /* Use incrementing source address */
  698. for (i = 6; i < 12; i++)
  699. pdata->loopback_tx_pkt[i] = (char)i;
  700. /* Set length type field */
  701. pdata->loopback_tx_pkt[12] = 0x00;
  702. pdata->loopback_tx_pkt[13] = 0x00;
  703. for (i = 14; i < MIN_PACKET_SIZE; i++)
  704. pdata->loopback_tx_pkt[i] = (char)i;
  705. val = smsc911x_reg_read(pdata, HW_CFG);
  706. val &= HW_CFG_TX_FIF_SZ_;
  707. val |= HW_CFG_SF_;
  708. smsc911x_reg_write(pdata, HW_CFG, val);
  709. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  710. smsc911x_reg_write(pdata, RX_CFG,
  711. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  712. for (i = 0; i < 10; i++) {
  713. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  714. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  715. BMCR_LOOPBACK | BMCR_FULLDPLX);
  716. /* Enable MAC tx/rx, FD */
  717. spin_lock_irqsave(&pdata->mac_lock, flags);
  718. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  719. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  720. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  721. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  722. result = 0;
  723. break;
  724. }
  725. pdata->resetcount++;
  726. /* Disable MAC rx */
  727. spin_lock_irqsave(&pdata->mac_lock, flags);
  728. smsc911x_mac_write(pdata, MAC_CR, 0);
  729. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  730. smsc911x_phy_reset(pdata);
  731. }
  732. /* Disable MAC */
  733. spin_lock_irqsave(&pdata->mac_lock, flags);
  734. smsc911x_mac_write(pdata, MAC_CR, 0);
  735. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  736. /* Cancel PHY loopback mode */
  737. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  738. smsc911x_reg_write(pdata, TX_CFG, 0);
  739. smsc911x_reg_write(pdata, RX_CFG, 0);
  740. return result;
  741. }
  742. #endif /* USE_PHY_WORK_AROUND */
  743. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  744. {
  745. struct phy_device *phy_dev = pdata->phy_dev;
  746. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  747. u32 flow;
  748. unsigned long flags;
  749. if (phy_dev->duplex == DUPLEX_FULL) {
  750. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  751. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  752. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  753. if (cap & FLOW_CTRL_RX)
  754. flow = 0xFFFF0002;
  755. else
  756. flow = 0;
  757. if (cap & FLOW_CTRL_TX)
  758. afc |= 0xF;
  759. else
  760. afc &= ~0xF;
  761. SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
  762. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  763. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  764. } else {
  765. SMSC_TRACE(pdata, hw, "half duplex");
  766. flow = 0;
  767. afc |= 0xF;
  768. }
  769. spin_lock_irqsave(&pdata->mac_lock, flags);
  770. smsc911x_mac_write(pdata, FLOW, flow);
  771. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  772. smsc911x_reg_write(pdata, AFC_CFG, afc);
  773. }
  774. /* Update link mode if anything has changed. Called periodically when the
  775. * PHY is in polling mode, even if nothing has changed. */
  776. static void smsc911x_phy_adjust_link(struct net_device *dev)
  777. {
  778. struct smsc911x_data *pdata = netdev_priv(dev);
  779. struct phy_device *phy_dev = pdata->phy_dev;
  780. unsigned long flags;
  781. int carrier;
  782. if (phy_dev->duplex != pdata->last_duplex) {
  783. unsigned int mac_cr;
  784. SMSC_TRACE(pdata, hw, "duplex state has changed");
  785. spin_lock_irqsave(&pdata->mac_lock, flags);
  786. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  787. if (phy_dev->duplex) {
  788. SMSC_TRACE(pdata, hw,
  789. "configuring for full duplex mode");
  790. mac_cr |= MAC_CR_FDPX_;
  791. } else {
  792. SMSC_TRACE(pdata, hw,
  793. "configuring for half duplex mode");
  794. mac_cr &= ~MAC_CR_FDPX_;
  795. }
  796. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  797. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  798. smsc911x_phy_update_flowcontrol(pdata);
  799. pdata->last_duplex = phy_dev->duplex;
  800. }
  801. carrier = netif_carrier_ok(dev);
  802. if (carrier != pdata->last_carrier) {
  803. SMSC_TRACE(pdata, hw, "carrier state has changed");
  804. if (carrier) {
  805. SMSC_TRACE(pdata, hw, "configuring for carrier OK");
  806. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  807. (!pdata->using_extphy)) {
  808. /* Restore original GPIO configuration */
  809. pdata->gpio_setting = pdata->gpio_orig_setting;
  810. smsc911x_reg_write(pdata, GPIO_CFG,
  811. pdata->gpio_setting);
  812. }
  813. } else {
  814. SMSC_TRACE(pdata, hw, "configuring for no carrier");
  815. /* Check global setting that LED1
  816. * usage is 10/100 indicator */
  817. pdata->gpio_setting = smsc911x_reg_read(pdata,
  818. GPIO_CFG);
  819. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
  820. (!pdata->using_extphy)) {
  821. /* Force 10/100 LED off, after saving
  822. * original GPIO configuration */
  823. pdata->gpio_orig_setting = pdata->gpio_setting;
  824. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  825. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  826. | GPIO_CFG_GPIODIR0_
  827. | GPIO_CFG_GPIOD0_);
  828. smsc911x_reg_write(pdata, GPIO_CFG,
  829. pdata->gpio_setting);
  830. }
  831. }
  832. pdata->last_carrier = carrier;
  833. }
  834. }
  835. static int smsc911x_mii_probe(struct net_device *dev)
  836. {
  837. struct smsc911x_data *pdata = netdev_priv(dev);
  838. struct phy_device *phydev = NULL;
  839. int ret;
  840. /* find the first phy */
  841. phydev = phy_find_first(pdata->mii_bus);
  842. if (!phydev) {
  843. netdev_err(dev, "no PHY found\n");
  844. return -ENODEV;
  845. }
  846. SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
  847. phydev->addr, phydev->phy_id);
  848. ret = phy_connect_direct(dev, phydev, &smsc911x_phy_adjust_link,
  849. pdata->config.phy_interface);
  850. if (ret) {
  851. netdev_err(dev, "Could not attach to PHY\n");
  852. return ret;
  853. }
  854. netdev_info(dev,
  855. "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  856. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  857. /* mask with MAC supported features */
  858. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  859. SUPPORTED_Asym_Pause);
  860. phydev->advertising = phydev->supported;
  861. pdata->phy_dev = phydev;
  862. pdata->last_duplex = -1;
  863. pdata->last_carrier = -1;
  864. #ifdef USE_PHY_WORK_AROUND
  865. if (smsc911x_phy_loopbacktest(dev) < 0) {
  866. SMSC_WARN(pdata, hw, "Failed Loop Back Test");
  867. return -ENODEV;
  868. }
  869. SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
  870. #endif /* USE_PHY_WORK_AROUND */
  871. SMSC_TRACE(pdata, hw, "phy initialised successfully");
  872. return 0;
  873. }
  874. static int smsc911x_mii_init(struct platform_device *pdev,
  875. struct net_device *dev)
  876. {
  877. struct smsc911x_data *pdata = netdev_priv(dev);
  878. int err = -ENXIO, i;
  879. pdata->mii_bus = mdiobus_alloc();
  880. if (!pdata->mii_bus) {
  881. err = -ENOMEM;
  882. goto err_out_1;
  883. }
  884. pdata->mii_bus->name = SMSC_MDIONAME;
  885. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
  886. pdev->name, pdev->id);
  887. pdata->mii_bus->priv = pdata;
  888. pdata->mii_bus->read = smsc911x_mii_read;
  889. pdata->mii_bus->write = smsc911x_mii_write;
  890. pdata->mii_bus->irq = pdata->phy_irq;
  891. for (i = 0; i < PHY_MAX_ADDR; ++i)
  892. pdata->mii_bus->irq[i] = PHY_POLL;
  893. pdata->mii_bus->parent = &pdev->dev;
  894. switch (pdata->idrev & 0xFFFF0000) {
  895. case 0x01170000:
  896. case 0x01150000:
  897. case 0x117A0000:
  898. case 0x115A0000:
  899. /* External PHY supported, try to autodetect */
  900. smsc911x_phy_initialise_external(pdata);
  901. break;
  902. default:
  903. SMSC_TRACE(pdata, hw, "External PHY is not supported, "
  904. "using internal PHY");
  905. pdata->using_extphy = 0;
  906. break;
  907. }
  908. if (!pdata->using_extphy) {
  909. /* Mask all PHYs except ID 1 (internal) */
  910. pdata->mii_bus->phy_mask = ~(1 << 1);
  911. }
  912. if (mdiobus_register(pdata->mii_bus)) {
  913. SMSC_WARN(pdata, probe, "Error registering mii bus");
  914. goto err_out_free_bus_2;
  915. }
  916. if (smsc911x_mii_probe(dev) < 0) {
  917. SMSC_WARN(pdata, probe, "Error registering mii bus");
  918. goto err_out_unregister_bus_3;
  919. }
  920. return 0;
  921. err_out_unregister_bus_3:
  922. mdiobus_unregister(pdata->mii_bus);
  923. err_out_free_bus_2:
  924. mdiobus_free(pdata->mii_bus);
  925. err_out_1:
  926. return err;
  927. }
  928. /* Gets the number of tx statuses in the fifo */
  929. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  930. {
  931. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  932. & TX_FIFO_INF_TSUSED_) >> 16;
  933. }
  934. /* Reads tx statuses and increments counters where necessary */
  935. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  936. {
  937. struct smsc911x_data *pdata = netdev_priv(dev);
  938. unsigned int tx_stat;
  939. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  940. if (unlikely(tx_stat & 0x80000000)) {
  941. /* In this driver the packet tag is used as the packet
  942. * length. Since a packet length can never reach the
  943. * size of 0x8000, this bit is reserved. It is worth
  944. * noting that the "reserved bit" in the warning above
  945. * does not reference a hardware defined reserved bit
  946. * but rather a driver defined one.
  947. */
  948. SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
  949. } else {
  950. if (unlikely(tx_stat & TX_STS_ES_)) {
  951. dev->stats.tx_errors++;
  952. } else {
  953. dev->stats.tx_packets++;
  954. dev->stats.tx_bytes += (tx_stat >> 16);
  955. }
  956. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  957. dev->stats.collisions += 16;
  958. dev->stats.tx_aborted_errors += 1;
  959. } else {
  960. dev->stats.collisions +=
  961. ((tx_stat >> 3) & 0xF);
  962. }
  963. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  964. dev->stats.tx_carrier_errors += 1;
  965. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  966. dev->stats.collisions++;
  967. dev->stats.tx_aborted_errors++;
  968. }
  969. }
  970. }
  971. }
  972. /* Increments the Rx error counters */
  973. static void
  974. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  975. {
  976. int crc_err = 0;
  977. if (unlikely(rxstat & RX_STS_ES_)) {
  978. dev->stats.rx_errors++;
  979. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  980. dev->stats.rx_crc_errors++;
  981. crc_err = 1;
  982. }
  983. }
  984. if (likely(!crc_err)) {
  985. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  986. (rxstat & RX_STS_LENGTH_ERR_)))
  987. dev->stats.rx_length_errors++;
  988. if (rxstat & RX_STS_MCAST_)
  989. dev->stats.multicast++;
  990. }
  991. }
  992. /* Quickly dumps bad packets */
  993. static void
  994. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktwords)
  995. {
  996. if (likely(pktwords >= 4)) {
  997. unsigned int timeout = 500;
  998. unsigned int val;
  999. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  1000. do {
  1001. udelay(1);
  1002. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  1003. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  1004. if (unlikely(timeout == 0))
  1005. SMSC_WARN(pdata, hw, "Timed out waiting for "
  1006. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  1007. } else {
  1008. unsigned int temp;
  1009. while (pktwords--)
  1010. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  1011. }
  1012. }
  1013. /* NAPI poll function */
  1014. static int smsc911x_poll(struct napi_struct *napi, int budget)
  1015. {
  1016. struct smsc911x_data *pdata =
  1017. container_of(napi, struct smsc911x_data, napi);
  1018. struct net_device *dev = pdata->dev;
  1019. int npackets = 0;
  1020. while (npackets < budget) {
  1021. unsigned int pktlength;
  1022. unsigned int pktwords;
  1023. struct sk_buff *skb;
  1024. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  1025. if (!rxstat) {
  1026. unsigned int temp;
  1027. /* We processed all packets available. Tell NAPI it can
  1028. * stop polling then re-enable rx interrupts */
  1029. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  1030. napi_complete(napi);
  1031. temp = smsc911x_reg_read(pdata, INT_EN);
  1032. temp |= INT_EN_RSFL_EN_;
  1033. smsc911x_reg_write(pdata, INT_EN, temp);
  1034. break;
  1035. }
  1036. /* Count packet for NAPI scheduling, even if it has an error.
  1037. * Error packets still require cycles to discard */
  1038. npackets++;
  1039. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  1040. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  1041. smsc911x_rx_counterrors(dev, rxstat);
  1042. if (unlikely(rxstat & RX_STS_ES_)) {
  1043. SMSC_WARN(pdata, rx_err,
  1044. "Discarding packet with error bit set");
  1045. /* Packet has an error, discard it and continue with
  1046. * the next */
  1047. smsc911x_rx_fastforward(pdata, pktwords);
  1048. dev->stats.rx_dropped++;
  1049. continue;
  1050. }
  1051. skb = netdev_alloc_skb(dev, pktwords << 2);
  1052. if (unlikely(!skb)) {
  1053. SMSC_WARN(pdata, rx_err,
  1054. "Unable to allocate skb for rx packet");
  1055. /* Drop the packet and stop this polling iteration */
  1056. smsc911x_rx_fastforward(pdata, pktwords);
  1057. dev->stats.rx_dropped++;
  1058. break;
  1059. }
  1060. pdata->ops->rx_readfifo(pdata,
  1061. (unsigned int *)skb->data, pktwords);
  1062. /* Align IP on 16B boundary */
  1063. skb_reserve(skb, NET_IP_ALIGN);
  1064. skb_put(skb, pktlength - 4);
  1065. skb->protocol = eth_type_trans(skb, dev);
  1066. skb_checksum_none_assert(skb);
  1067. netif_receive_skb(skb);
  1068. /* Update counters */
  1069. dev->stats.rx_packets++;
  1070. dev->stats.rx_bytes += (pktlength - 4);
  1071. }
  1072. /* Return total received packets */
  1073. return npackets;
  1074. }
  1075. /* Returns hash bit number for given MAC address
  1076. * Example:
  1077. * 01 00 5E 00 00 01 -> returns bit number 31 */
  1078. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  1079. {
  1080. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  1081. }
  1082. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  1083. {
  1084. /* Performs the multicast & mac_cr update. This is called when
  1085. * safe on the current hardware, and with the mac_lock held */
  1086. unsigned int mac_cr;
  1087. SMSC_ASSERT_MAC_LOCK(pdata);
  1088. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1089. mac_cr |= pdata->set_bits_mask;
  1090. mac_cr &= ~(pdata->clear_bits_mask);
  1091. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1092. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  1093. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  1094. SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  1095. mac_cr, pdata->hashhi, pdata->hashlo);
  1096. }
  1097. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  1098. {
  1099. unsigned int mac_cr;
  1100. /* This function is only called for older LAN911x devices
  1101. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  1102. * be modified during Rx - newer devices immediately update the
  1103. * registers.
  1104. *
  1105. * This is called from interrupt context */
  1106. spin_lock(&pdata->mac_lock);
  1107. /* Check Rx has stopped */
  1108. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  1109. SMSC_WARN(pdata, drv, "Rx not stopped");
  1110. /* Perform the update - safe to do now Rx has stopped */
  1111. smsc911x_rx_multicast_update(pdata);
  1112. /* Re-enable Rx */
  1113. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1114. mac_cr |= MAC_CR_RXEN_;
  1115. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1116. pdata->multicast_update_pending = 0;
  1117. spin_unlock(&pdata->mac_lock);
  1118. }
  1119. static int smsc911x_phy_general_power_up(struct smsc911x_data *pdata)
  1120. {
  1121. int rc = 0;
  1122. if (!pdata->phy_dev)
  1123. return rc;
  1124. /* If the internal PHY is in General Power-Down mode, all, except the
  1125. * management interface, is powered-down and stays in that condition as
  1126. * long as Phy register bit 0.11 is HIGH.
  1127. *
  1128. * In that case, clear the bit 0.11, so the PHY powers up and we can
  1129. * access to the phy registers.
  1130. */
  1131. rc = phy_read(pdata->phy_dev, MII_BMCR);
  1132. if (rc < 0) {
  1133. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1134. return rc;
  1135. }
  1136. /* If the PHY general power-down bit is not set is not necessary to
  1137. * disable the general power down-mode.
  1138. */
  1139. if (rc & BMCR_PDOWN) {
  1140. rc = phy_write(pdata->phy_dev, MII_BMCR, rc & ~BMCR_PDOWN);
  1141. if (rc < 0) {
  1142. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1143. return rc;
  1144. }
  1145. usleep_range(1000, 1500);
  1146. }
  1147. return 0;
  1148. }
  1149. static int smsc911x_phy_disable_energy_detect(struct smsc911x_data *pdata)
  1150. {
  1151. int rc = 0;
  1152. if (!pdata->phy_dev)
  1153. return rc;
  1154. rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
  1155. if (rc < 0) {
  1156. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1157. return rc;
  1158. }
  1159. /* Only disable if energy detect mode is already enabled */
  1160. if (rc & MII_LAN83C185_EDPWRDOWN) {
  1161. /* Disable energy detect mode for this SMSC Transceivers */
  1162. rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
  1163. rc & (~MII_LAN83C185_EDPWRDOWN));
  1164. if (rc < 0) {
  1165. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1166. return rc;
  1167. }
  1168. /* Allow PHY to wakeup */
  1169. mdelay(2);
  1170. }
  1171. return 0;
  1172. }
  1173. static int smsc911x_phy_enable_energy_detect(struct smsc911x_data *pdata)
  1174. {
  1175. int rc = 0;
  1176. if (!pdata->phy_dev)
  1177. return rc;
  1178. rc = phy_read(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS);
  1179. if (rc < 0) {
  1180. SMSC_WARN(pdata, drv, "Failed reading PHY control reg");
  1181. return rc;
  1182. }
  1183. /* Only enable if energy detect mode is already disabled */
  1184. if (!(rc & MII_LAN83C185_EDPWRDOWN)) {
  1185. /* Enable energy detect mode for this SMSC Transceivers */
  1186. rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS,
  1187. rc | MII_LAN83C185_EDPWRDOWN);
  1188. if (rc < 0) {
  1189. SMSC_WARN(pdata, drv, "Failed writing PHY control reg");
  1190. return rc;
  1191. }
  1192. }
  1193. return 0;
  1194. }
  1195. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  1196. {
  1197. unsigned int timeout;
  1198. unsigned int temp;
  1199. int ret;
  1200. /*
  1201. * Make sure to power-up the PHY chip before doing a reset, otherwise
  1202. * the reset fails.
  1203. */
  1204. ret = smsc911x_phy_general_power_up(pdata);
  1205. if (ret) {
  1206. SMSC_WARN(pdata, drv, "Failed to power-up the PHY chip");
  1207. return ret;
  1208. }
  1209. /*
  1210. * LAN9210/LAN9211/LAN9220/LAN9221 chips have an internal PHY that
  1211. * are initialized in a Energy Detect Power-Down mode that prevents
  1212. * the MAC chip to be software reseted. So we have to wakeup the PHY
  1213. * before.
  1214. */
  1215. if (pdata->generation == 4) {
  1216. ret = smsc911x_phy_disable_energy_detect(pdata);
  1217. if (ret) {
  1218. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1219. return ret;
  1220. }
  1221. }
  1222. /* Reset the LAN911x */
  1223. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  1224. timeout = 10;
  1225. do {
  1226. udelay(10);
  1227. temp = smsc911x_reg_read(pdata, HW_CFG);
  1228. } while ((--timeout) && (temp & HW_CFG_SRST_));
  1229. if (unlikely(temp & HW_CFG_SRST_)) {
  1230. SMSC_WARN(pdata, drv, "Failed to complete reset");
  1231. return -EIO;
  1232. }
  1233. if (pdata->generation == 4) {
  1234. ret = smsc911x_phy_enable_energy_detect(pdata);
  1235. if (ret) {
  1236. SMSC_WARN(pdata, drv, "Failed to wakeup the PHY chip");
  1237. return ret;
  1238. }
  1239. }
  1240. return 0;
  1241. }
  1242. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  1243. static void
  1244. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  1245. {
  1246. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  1247. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  1248. (dev_addr[1] << 8) | dev_addr[0];
  1249. SMSC_ASSERT_MAC_LOCK(pdata);
  1250. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  1251. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  1252. }
  1253. static void smsc911x_disable_irq_chip(struct net_device *dev)
  1254. {
  1255. struct smsc911x_data *pdata = netdev_priv(dev);
  1256. smsc911x_reg_write(pdata, INT_EN, 0);
  1257. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1258. }
  1259. static int smsc911x_open(struct net_device *dev)
  1260. {
  1261. struct smsc911x_data *pdata = netdev_priv(dev);
  1262. unsigned int timeout;
  1263. unsigned int temp;
  1264. unsigned int intcfg;
  1265. /* if the phy is not yet registered, retry later*/
  1266. if (!pdata->phy_dev) {
  1267. SMSC_WARN(pdata, hw, "phy_dev is NULL");
  1268. return -EAGAIN;
  1269. }
  1270. /* Reset the LAN911x */
  1271. if (smsc911x_soft_reset(pdata)) {
  1272. SMSC_WARN(pdata, hw, "soft reset failed");
  1273. return -EIO;
  1274. }
  1275. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  1276. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  1277. /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
  1278. spin_lock_irq(&pdata->mac_lock);
  1279. smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
  1280. spin_unlock_irq(&pdata->mac_lock);
  1281. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  1282. timeout = 50;
  1283. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  1284. --timeout) {
  1285. udelay(10);
  1286. }
  1287. if (unlikely(timeout == 0))
  1288. SMSC_WARN(pdata, ifup,
  1289. "Timed out waiting for EEPROM busy bit to clear");
  1290. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  1291. /* The soft reset above cleared the device's MAC address,
  1292. * restore it from local copy (set in probe) */
  1293. spin_lock_irq(&pdata->mac_lock);
  1294. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1295. spin_unlock_irq(&pdata->mac_lock);
  1296. /* Initialise irqs, but leave all sources disabled */
  1297. smsc911x_disable_irq_chip(dev);
  1298. /* Set interrupt deassertion to 100uS */
  1299. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  1300. if (pdata->config.irq_polarity) {
  1301. SMSC_TRACE(pdata, ifup, "irq polarity: active high");
  1302. intcfg |= INT_CFG_IRQ_POL_;
  1303. } else {
  1304. SMSC_TRACE(pdata, ifup, "irq polarity: active low");
  1305. }
  1306. if (pdata->config.irq_type) {
  1307. SMSC_TRACE(pdata, ifup, "irq type: push-pull");
  1308. intcfg |= INT_CFG_IRQ_TYPE_;
  1309. } else {
  1310. SMSC_TRACE(pdata, ifup, "irq type: open drain");
  1311. }
  1312. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1313. SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
  1314. pdata->software_irq_signal = 0;
  1315. smp_wmb();
  1316. temp = smsc911x_reg_read(pdata, INT_EN);
  1317. temp |= INT_EN_SW_INT_EN_;
  1318. smsc911x_reg_write(pdata, INT_EN, temp);
  1319. timeout = 1000;
  1320. while (timeout--) {
  1321. if (pdata->software_irq_signal)
  1322. break;
  1323. msleep(1);
  1324. }
  1325. if (!pdata->software_irq_signal) {
  1326. netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
  1327. dev->irq);
  1328. return -ENODEV;
  1329. }
  1330. SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
  1331. dev->irq);
  1332. netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1333. (unsigned long)pdata->ioaddr, dev->irq);
  1334. /* Reset the last known duplex and carrier */
  1335. pdata->last_duplex = -1;
  1336. pdata->last_carrier = -1;
  1337. /* Bring the PHY up */
  1338. phy_start(pdata->phy_dev);
  1339. temp = smsc911x_reg_read(pdata, HW_CFG);
  1340. /* Preserve TX FIFO size and external PHY configuration */
  1341. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1342. temp |= HW_CFG_SF_;
  1343. smsc911x_reg_write(pdata, HW_CFG, temp);
  1344. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1345. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1346. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1347. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1348. /* set RX Data offset to 2 bytes for alignment */
  1349. smsc911x_reg_write(pdata, RX_CFG, (NET_IP_ALIGN << 8));
  1350. /* enable NAPI polling before enabling RX interrupts */
  1351. napi_enable(&pdata->napi);
  1352. temp = smsc911x_reg_read(pdata, INT_EN);
  1353. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1354. smsc911x_reg_write(pdata, INT_EN, temp);
  1355. spin_lock_irq(&pdata->mac_lock);
  1356. temp = smsc911x_mac_read(pdata, MAC_CR);
  1357. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1358. smsc911x_mac_write(pdata, MAC_CR, temp);
  1359. spin_unlock_irq(&pdata->mac_lock);
  1360. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1361. netif_start_queue(dev);
  1362. return 0;
  1363. }
  1364. /* Entry point for stopping the interface */
  1365. static int smsc911x_stop(struct net_device *dev)
  1366. {
  1367. struct smsc911x_data *pdata = netdev_priv(dev);
  1368. unsigned int temp;
  1369. /* Disable all device interrupts */
  1370. temp = smsc911x_reg_read(pdata, INT_CFG);
  1371. temp &= ~INT_CFG_IRQ_EN_;
  1372. smsc911x_reg_write(pdata, INT_CFG, temp);
  1373. /* Stop Tx and Rx polling */
  1374. netif_stop_queue(dev);
  1375. napi_disable(&pdata->napi);
  1376. /* At this point all Rx and Tx activity is stopped */
  1377. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1378. smsc911x_tx_update_txcounters(dev);
  1379. /* Bring the PHY down */
  1380. if (pdata->phy_dev)
  1381. phy_stop(pdata->phy_dev);
  1382. SMSC_TRACE(pdata, ifdown, "Interface stopped");
  1383. return 0;
  1384. }
  1385. /* Entry point for transmitting a packet */
  1386. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1387. {
  1388. struct smsc911x_data *pdata = netdev_priv(dev);
  1389. unsigned int freespace;
  1390. unsigned int tx_cmd_a;
  1391. unsigned int tx_cmd_b;
  1392. unsigned int temp;
  1393. u32 wrsz;
  1394. ulong bufp;
  1395. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1396. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1397. SMSC_WARN(pdata, tx_err,
  1398. "Tx data fifo low, space available: %d", freespace);
  1399. /* Word alignment adjustment */
  1400. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1401. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1402. tx_cmd_a |= (unsigned int)skb->len;
  1403. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1404. tx_cmd_b |= (unsigned int)skb->len;
  1405. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1406. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1407. bufp = (ulong)skb->data & (~0x3);
  1408. wrsz = (u32)skb->len + 3;
  1409. wrsz += (u32)((ulong)skb->data & 0x3);
  1410. wrsz >>= 2;
  1411. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1412. freespace -= (skb->len + 32);
  1413. skb_tx_timestamp(skb);
  1414. dev_consume_skb_any(skb);
  1415. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1416. smsc911x_tx_update_txcounters(dev);
  1417. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1418. netif_stop_queue(dev);
  1419. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1420. temp &= 0x00FFFFFF;
  1421. temp |= 0x32000000;
  1422. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1423. }
  1424. return NETDEV_TX_OK;
  1425. }
  1426. /* Entry point for getting status counters */
  1427. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1428. {
  1429. struct smsc911x_data *pdata = netdev_priv(dev);
  1430. smsc911x_tx_update_txcounters(dev);
  1431. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1432. return &dev->stats;
  1433. }
  1434. /* Entry point for setting addressing modes */
  1435. static void smsc911x_set_multicast_list(struct net_device *dev)
  1436. {
  1437. struct smsc911x_data *pdata = netdev_priv(dev);
  1438. unsigned long flags;
  1439. if (dev->flags & IFF_PROMISC) {
  1440. /* Enabling promiscuous mode */
  1441. pdata->set_bits_mask = MAC_CR_PRMS_;
  1442. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1443. pdata->hashhi = 0;
  1444. pdata->hashlo = 0;
  1445. } else if (dev->flags & IFF_ALLMULTI) {
  1446. /* Enabling all multicast mode */
  1447. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1448. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1449. pdata->hashhi = 0;
  1450. pdata->hashlo = 0;
  1451. } else if (!netdev_mc_empty(dev)) {
  1452. /* Enabling specific multicast addresses */
  1453. unsigned int hash_high = 0;
  1454. unsigned int hash_low = 0;
  1455. struct netdev_hw_addr *ha;
  1456. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1457. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1458. netdev_for_each_mc_addr(ha, dev) {
  1459. unsigned int bitnum = smsc911x_hash(ha->addr);
  1460. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1461. if (bitnum & 0x20)
  1462. hash_high |= mask;
  1463. else
  1464. hash_low |= mask;
  1465. }
  1466. pdata->hashhi = hash_high;
  1467. pdata->hashlo = hash_low;
  1468. } else {
  1469. /* Enabling local MAC address only */
  1470. pdata->set_bits_mask = 0;
  1471. pdata->clear_bits_mask =
  1472. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1473. pdata->hashhi = 0;
  1474. pdata->hashlo = 0;
  1475. }
  1476. spin_lock_irqsave(&pdata->mac_lock, flags);
  1477. if (pdata->generation <= 1) {
  1478. /* Older hardware revision - cannot change these flags while
  1479. * receiving data */
  1480. if (!pdata->multicast_update_pending) {
  1481. unsigned int temp;
  1482. SMSC_TRACE(pdata, hw, "scheduling mcast update");
  1483. pdata->multicast_update_pending = 1;
  1484. /* Request the hardware to stop, then perform the
  1485. * update when we get an RX_STOP interrupt */
  1486. temp = smsc911x_mac_read(pdata, MAC_CR);
  1487. temp &= ~(MAC_CR_RXEN_);
  1488. smsc911x_mac_write(pdata, MAC_CR, temp);
  1489. } else {
  1490. /* There is another update pending, this should now
  1491. * use the newer values */
  1492. }
  1493. } else {
  1494. /* Newer hardware revision - can write immediately */
  1495. smsc911x_rx_multicast_update(pdata);
  1496. }
  1497. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1498. }
  1499. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1500. {
  1501. struct net_device *dev = dev_id;
  1502. struct smsc911x_data *pdata = netdev_priv(dev);
  1503. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1504. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1505. int serviced = IRQ_NONE;
  1506. u32 temp;
  1507. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1508. temp = smsc911x_reg_read(pdata, INT_EN);
  1509. temp &= (~INT_EN_SW_INT_EN_);
  1510. smsc911x_reg_write(pdata, INT_EN, temp);
  1511. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1512. pdata->software_irq_signal = 1;
  1513. smp_wmb();
  1514. serviced = IRQ_HANDLED;
  1515. }
  1516. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1517. /* Called when there is a multicast update scheduled and
  1518. * it is now safe to complete the update */
  1519. SMSC_TRACE(pdata, intr, "RX Stop interrupt");
  1520. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1521. if (pdata->multicast_update_pending)
  1522. smsc911x_rx_multicast_update_workaround(pdata);
  1523. serviced = IRQ_HANDLED;
  1524. }
  1525. if (intsts & inten & INT_STS_TDFA_) {
  1526. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1527. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1528. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1529. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1530. netif_wake_queue(dev);
  1531. serviced = IRQ_HANDLED;
  1532. }
  1533. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1534. SMSC_TRACE(pdata, intr, "RX Error interrupt");
  1535. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1536. serviced = IRQ_HANDLED;
  1537. }
  1538. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1539. if (likely(napi_schedule_prep(&pdata->napi))) {
  1540. /* Disable Rx interrupts */
  1541. temp = smsc911x_reg_read(pdata, INT_EN);
  1542. temp &= (~INT_EN_RSFL_EN_);
  1543. smsc911x_reg_write(pdata, INT_EN, temp);
  1544. /* Schedule a NAPI poll */
  1545. __napi_schedule(&pdata->napi);
  1546. } else {
  1547. SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
  1548. }
  1549. serviced = IRQ_HANDLED;
  1550. }
  1551. return serviced;
  1552. }
  1553. #ifdef CONFIG_NET_POLL_CONTROLLER
  1554. static void smsc911x_poll_controller(struct net_device *dev)
  1555. {
  1556. disable_irq(dev->irq);
  1557. smsc911x_irqhandler(0, dev);
  1558. enable_irq(dev->irq);
  1559. }
  1560. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1561. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1562. {
  1563. struct smsc911x_data *pdata = netdev_priv(dev);
  1564. struct sockaddr *addr = p;
  1565. /* On older hardware revisions we cannot change the mac address
  1566. * registers while receiving data. Newer devices can safely change
  1567. * this at any time. */
  1568. if (pdata->generation <= 1 && netif_running(dev))
  1569. return -EBUSY;
  1570. if (!is_valid_ether_addr(addr->sa_data))
  1571. return -EADDRNOTAVAIL;
  1572. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1573. spin_lock_irq(&pdata->mac_lock);
  1574. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1575. spin_unlock_irq(&pdata->mac_lock);
  1576. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  1577. return 0;
  1578. }
  1579. /* Standard ioctls for mii-tool */
  1580. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1581. {
  1582. struct smsc911x_data *pdata = netdev_priv(dev);
  1583. if (!netif_running(dev) || !pdata->phy_dev)
  1584. return -EINVAL;
  1585. return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
  1586. }
  1587. static int
  1588. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1589. {
  1590. struct smsc911x_data *pdata = netdev_priv(dev);
  1591. cmd->maxtxpkt = 1;
  1592. cmd->maxrxpkt = 1;
  1593. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1594. }
  1595. static int
  1596. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1597. {
  1598. struct smsc911x_data *pdata = netdev_priv(dev);
  1599. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1600. }
  1601. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1602. struct ethtool_drvinfo *info)
  1603. {
  1604. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1605. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1606. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1607. sizeof(info->bus_info));
  1608. }
  1609. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1610. {
  1611. struct smsc911x_data *pdata = netdev_priv(dev);
  1612. return phy_start_aneg(pdata->phy_dev);
  1613. }
  1614. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1615. {
  1616. struct smsc911x_data *pdata = netdev_priv(dev);
  1617. return pdata->msg_enable;
  1618. }
  1619. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1620. {
  1621. struct smsc911x_data *pdata = netdev_priv(dev);
  1622. pdata->msg_enable = level;
  1623. }
  1624. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1625. {
  1626. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1627. sizeof(u32);
  1628. }
  1629. static void
  1630. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1631. void *buf)
  1632. {
  1633. struct smsc911x_data *pdata = netdev_priv(dev);
  1634. struct phy_device *phy_dev = pdata->phy_dev;
  1635. unsigned long flags;
  1636. unsigned int i;
  1637. unsigned int j = 0;
  1638. u32 *data = buf;
  1639. regs->version = pdata->idrev;
  1640. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1641. data[j++] = smsc911x_reg_read(pdata, i);
  1642. for (i = MAC_CR; i <= WUCSR; i++) {
  1643. spin_lock_irqsave(&pdata->mac_lock, flags);
  1644. data[j++] = smsc911x_mac_read(pdata, i);
  1645. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1646. }
  1647. for (i = 0; i <= 31; i++)
  1648. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1649. }
  1650. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1651. {
  1652. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1653. temp &= ~GPIO_CFG_EEPR_EN_;
  1654. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1655. msleep(1);
  1656. }
  1657. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1658. {
  1659. int timeout = 100;
  1660. u32 e2cmd;
  1661. SMSC_TRACE(pdata, drv, "op 0x%08x", op);
  1662. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1663. SMSC_WARN(pdata, drv, "Busy at start");
  1664. return -EBUSY;
  1665. }
  1666. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1667. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1668. do {
  1669. msleep(1);
  1670. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1671. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1672. if (!timeout) {
  1673. SMSC_TRACE(pdata, drv, "TIMED OUT");
  1674. return -EAGAIN;
  1675. }
  1676. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1677. SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
  1678. return -EINVAL;
  1679. }
  1680. return 0;
  1681. }
  1682. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1683. u8 address, u8 *data)
  1684. {
  1685. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1686. int ret;
  1687. SMSC_TRACE(pdata, drv, "address 0x%x", address);
  1688. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1689. if (!ret)
  1690. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1691. return ret;
  1692. }
  1693. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1694. u8 address, u8 data)
  1695. {
  1696. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1697. u32 temp;
  1698. int ret;
  1699. SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
  1700. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1701. if (!ret) {
  1702. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1703. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1704. /* Workaround for hardware read-after-write restriction */
  1705. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1706. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1707. }
  1708. return ret;
  1709. }
  1710. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1711. {
  1712. return SMSC911X_EEPROM_SIZE;
  1713. }
  1714. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1715. struct ethtool_eeprom *eeprom, u8 *data)
  1716. {
  1717. struct smsc911x_data *pdata = netdev_priv(dev);
  1718. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1719. int len;
  1720. int i;
  1721. smsc911x_eeprom_enable_access(pdata);
  1722. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1723. for (i = 0; i < len; i++) {
  1724. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1725. if (ret < 0) {
  1726. eeprom->len = 0;
  1727. return ret;
  1728. }
  1729. }
  1730. memcpy(data, &eeprom_data[eeprom->offset], len);
  1731. eeprom->len = len;
  1732. return 0;
  1733. }
  1734. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1735. struct ethtool_eeprom *eeprom, u8 *data)
  1736. {
  1737. int ret;
  1738. struct smsc911x_data *pdata = netdev_priv(dev);
  1739. smsc911x_eeprom_enable_access(pdata);
  1740. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1741. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1742. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1743. /* Single byte write, according to man page */
  1744. eeprom->len = 1;
  1745. return ret;
  1746. }
  1747. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1748. .get_settings = smsc911x_ethtool_getsettings,
  1749. .set_settings = smsc911x_ethtool_setsettings,
  1750. .get_link = ethtool_op_get_link,
  1751. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1752. .nway_reset = smsc911x_ethtool_nwayreset,
  1753. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1754. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1755. .get_regs_len = smsc911x_ethtool_getregslen,
  1756. .get_regs = smsc911x_ethtool_getregs,
  1757. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1758. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1759. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1760. .get_ts_info = ethtool_op_get_ts_info,
  1761. };
  1762. static const struct net_device_ops smsc911x_netdev_ops = {
  1763. .ndo_open = smsc911x_open,
  1764. .ndo_stop = smsc911x_stop,
  1765. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1766. .ndo_get_stats = smsc911x_get_stats,
  1767. .ndo_set_rx_mode = smsc911x_set_multicast_list,
  1768. .ndo_do_ioctl = smsc911x_do_ioctl,
  1769. .ndo_change_mtu = eth_change_mtu,
  1770. .ndo_validate_addr = eth_validate_addr,
  1771. .ndo_set_mac_address = smsc911x_set_mac_address,
  1772. #ifdef CONFIG_NET_POLL_CONTROLLER
  1773. .ndo_poll_controller = smsc911x_poll_controller,
  1774. #endif
  1775. };
  1776. /* copies the current mac address from hardware to dev->dev_addr */
  1777. static void smsc911x_read_mac_address(struct net_device *dev)
  1778. {
  1779. struct smsc911x_data *pdata = netdev_priv(dev);
  1780. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1781. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1782. dev->dev_addr[0] = (u8)(mac_low32);
  1783. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1784. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1785. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1786. dev->dev_addr[4] = (u8)(mac_high16);
  1787. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1788. }
  1789. /* Initializing private device structures, only called from probe */
  1790. static int smsc911x_init(struct net_device *dev)
  1791. {
  1792. struct smsc911x_data *pdata = netdev_priv(dev);
  1793. unsigned int byte_test, mask;
  1794. unsigned int to = 100;
  1795. SMSC_TRACE(pdata, probe, "Driver Parameters:");
  1796. SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
  1797. (unsigned long)pdata->ioaddr);
  1798. SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
  1799. SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
  1800. spin_lock_init(&pdata->dev_lock);
  1801. spin_lock_init(&pdata->mac_lock);
  1802. if (pdata->ioaddr == NULL) {
  1803. SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
  1804. return -ENODEV;
  1805. }
  1806. /*
  1807. * poll the READY bit in PMT_CTRL. Any other access to the device is
  1808. * forbidden while this bit isn't set. Try for 100ms
  1809. *
  1810. * Note that this test is done before the WORD_SWAP register is
  1811. * programmed. So in some configurations the READY bit is at 16 before
  1812. * WORD_SWAP is written to. This issue is worked around by waiting
  1813. * until either bit 0 or bit 16 gets set in PMT_CTRL.
  1814. *
  1815. * SMSC has confirmed that checking bit 16 (marked as reserved in
  1816. * the datasheet) is fine since these bits "will either never be set
  1817. * or can only go high after READY does (so also indicate the device
  1818. * is ready)".
  1819. */
  1820. mask = PMT_CTRL_READY_ | swahw32(PMT_CTRL_READY_);
  1821. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & mask) && --to)
  1822. udelay(1000);
  1823. if (to == 0) {
  1824. netdev_err(dev, "Device not READY in 100ms aborting\n");
  1825. return -ENODEV;
  1826. }
  1827. /* Check byte ordering */
  1828. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1829. SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
  1830. if (byte_test == 0x43218765) {
  1831. SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
  1832. "applying WORD_SWAP");
  1833. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1834. /* 1 dummy read of BYTE_TEST is needed after a write to
  1835. * WORD_SWAP before its contents are valid */
  1836. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1837. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1838. }
  1839. if (byte_test != 0x87654321) {
  1840. SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
  1841. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1842. SMSC_WARN(pdata, probe,
  1843. "top 16 bits equal to bottom 16 bits");
  1844. SMSC_TRACE(pdata, probe,
  1845. "This may mean the chip is set "
  1846. "for 32 bit while the bus is reading 16 bit");
  1847. }
  1848. return -ENODEV;
  1849. }
  1850. /* Default generation to zero (all workarounds apply) */
  1851. pdata->generation = 0;
  1852. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1853. switch (pdata->idrev & 0xFFFF0000) {
  1854. case 0x01180000:
  1855. case 0x01170000:
  1856. case 0x01160000:
  1857. case 0x01150000:
  1858. case 0x218A0000:
  1859. /* LAN911[5678] family */
  1860. pdata->generation = pdata->idrev & 0x0000FFFF;
  1861. break;
  1862. case 0x118A0000:
  1863. case 0x117A0000:
  1864. case 0x116A0000:
  1865. case 0x115A0000:
  1866. /* LAN921[5678] family */
  1867. pdata->generation = 3;
  1868. break;
  1869. case 0x92100000:
  1870. case 0x92110000:
  1871. case 0x92200000:
  1872. case 0x92210000:
  1873. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1874. pdata->generation = 4;
  1875. break;
  1876. default:
  1877. SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
  1878. pdata->idrev);
  1879. return -ENODEV;
  1880. }
  1881. SMSC_TRACE(pdata, probe,
  1882. "LAN911x identified, idrev: 0x%08X, generation: %d",
  1883. pdata->idrev, pdata->generation);
  1884. if (pdata->generation == 0)
  1885. SMSC_WARN(pdata, probe,
  1886. "This driver is not intended for this chip revision");
  1887. /* workaround for platforms without an eeprom, where the mac address
  1888. * is stored elsewhere and set by the bootloader. This saves the
  1889. * mac address before resetting the device */
  1890. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
  1891. spin_lock_irq(&pdata->mac_lock);
  1892. smsc911x_read_mac_address(dev);
  1893. spin_unlock_irq(&pdata->mac_lock);
  1894. }
  1895. /* Reset the LAN911x */
  1896. if (smsc911x_soft_reset(pdata))
  1897. return -ENODEV;
  1898. dev->flags |= IFF_MULTICAST;
  1899. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1900. dev->netdev_ops = &smsc911x_netdev_ops;
  1901. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1902. return 0;
  1903. }
  1904. static int smsc911x_drv_remove(struct platform_device *pdev)
  1905. {
  1906. struct net_device *dev;
  1907. struct smsc911x_data *pdata;
  1908. struct resource *res;
  1909. dev = platform_get_drvdata(pdev);
  1910. BUG_ON(!dev);
  1911. pdata = netdev_priv(dev);
  1912. BUG_ON(!pdata);
  1913. BUG_ON(!pdata->ioaddr);
  1914. BUG_ON(!pdata->phy_dev);
  1915. SMSC_TRACE(pdata, ifdown, "Stopping driver");
  1916. phy_disconnect(pdata->phy_dev);
  1917. pdata->phy_dev = NULL;
  1918. mdiobus_unregister(pdata->mii_bus);
  1919. mdiobus_free(pdata->mii_bus);
  1920. unregister_netdev(dev);
  1921. free_irq(dev->irq, dev);
  1922. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1923. "smsc911x-memory");
  1924. if (!res)
  1925. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1926. release_mem_region(res->start, resource_size(res));
  1927. iounmap(pdata->ioaddr);
  1928. (void)smsc911x_disable_resources(pdev);
  1929. smsc911x_free_resources(pdev);
  1930. free_netdev(dev);
  1931. pm_runtime_put(&pdev->dev);
  1932. pm_runtime_disable(&pdev->dev);
  1933. return 0;
  1934. }
  1935. /* standard register acces */
  1936. static const struct smsc911x_ops standard_smsc911x_ops = {
  1937. .reg_read = __smsc911x_reg_read,
  1938. .reg_write = __smsc911x_reg_write,
  1939. .rx_readfifo = smsc911x_rx_readfifo,
  1940. .tx_writefifo = smsc911x_tx_writefifo,
  1941. };
  1942. /* shifted register access */
  1943. static const struct smsc911x_ops shifted_smsc911x_ops = {
  1944. .reg_read = __smsc911x_reg_read_shift,
  1945. .reg_write = __smsc911x_reg_write_shift,
  1946. .rx_readfifo = smsc911x_rx_readfifo_shift,
  1947. .tx_writefifo = smsc911x_tx_writefifo_shift,
  1948. };
  1949. #ifdef CONFIG_OF
  1950. static int smsc911x_probe_config_dt(struct smsc911x_platform_config *config,
  1951. struct device_node *np)
  1952. {
  1953. const char *mac;
  1954. u32 width = 0;
  1955. if (!np)
  1956. return -ENODEV;
  1957. config->phy_interface = of_get_phy_mode(np);
  1958. mac = of_get_mac_address(np);
  1959. if (mac)
  1960. memcpy(config->mac, mac, ETH_ALEN);
  1961. of_property_read_u32(np, "reg-shift", &config->shift);
  1962. of_property_read_u32(np, "reg-io-width", &width);
  1963. if (width == 4)
  1964. config->flags |= SMSC911X_USE_32BIT;
  1965. else
  1966. config->flags |= SMSC911X_USE_16BIT;
  1967. if (of_get_property(np, "smsc,irq-active-high", NULL))
  1968. config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
  1969. if (of_get_property(np, "smsc,irq-push-pull", NULL))
  1970. config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
  1971. if (of_get_property(np, "smsc,force-internal-phy", NULL))
  1972. config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
  1973. if (of_get_property(np, "smsc,force-external-phy", NULL))
  1974. config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
  1975. if (of_get_property(np, "smsc,save-mac-address", NULL))
  1976. config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
  1977. return 0;
  1978. }
  1979. #else
  1980. static inline int smsc911x_probe_config_dt(
  1981. struct smsc911x_platform_config *config,
  1982. struct device_node *np)
  1983. {
  1984. return -ENODEV;
  1985. }
  1986. #endif /* CONFIG_OF */
  1987. static int smsc911x_drv_probe(struct platform_device *pdev)
  1988. {
  1989. struct device_node *np = pdev->dev.of_node;
  1990. struct net_device *dev;
  1991. struct smsc911x_data *pdata;
  1992. struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev);
  1993. struct resource *res;
  1994. unsigned int intcfg = 0;
  1995. int res_size, irq, irq_flags;
  1996. int retval;
  1997. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1998. "smsc911x-memory");
  1999. if (!res)
  2000. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  2001. if (!res) {
  2002. pr_warn("Could not allocate resource\n");
  2003. retval = -ENODEV;
  2004. goto out_0;
  2005. }
  2006. res_size = resource_size(res);
  2007. irq = platform_get_irq(pdev, 0);
  2008. if (irq <= 0) {
  2009. pr_warn("Could not allocate irq resource\n");
  2010. retval = -ENODEV;
  2011. goto out_0;
  2012. }
  2013. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  2014. retval = -EBUSY;
  2015. goto out_0;
  2016. }
  2017. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  2018. if (!dev) {
  2019. retval = -ENOMEM;
  2020. goto out_release_io_1;
  2021. }
  2022. SET_NETDEV_DEV(dev, &pdev->dev);
  2023. pdata = netdev_priv(dev);
  2024. dev->irq = irq;
  2025. irq_flags = irq_get_trigger_type(irq);
  2026. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  2027. pdata->dev = dev;
  2028. pdata->msg_enable = ((1 << debug) - 1);
  2029. platform_set_drvdata(pdev, dev);
  2030. retval = smsc911x_request_resources(pdev);
  2031. if (retval)
  2032. goto out_request_resources_fail;
  2033. retval = smsc911x_enable_resources(pdev);
  2034. if (retval)
  2035. goto out_enable_resources_fail;
  2036. if (pdata->ioaddr == NULL) {
  2037. SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
  2038. retval = -ENOMEM;
  2039. goto out_disable_resources;
  2040. }
  2041. retval = smsc911x_probe_config_dt(&pdata->config, np);
  2042. if (retval && config) {
  2043. /* copy config parameters across to pdata */
  2044. memcpy(&pdata->config, config, sizeof(pdata->config));
  2045. retval = 0;
  2046. }
  2047. if (retval) {
  2048. SMSC_WARN(pdata, probe, "Error smsc911x config not found");
  2049. goto out_disable_resources;
  2050. }
  2051. /* assume standard, non-shifted, access to HW registers */
  2052. pdata->ops = &standard_smsc911x_ops;
  2053. /* apply the right access if shifting is needed */
  2054. if (pdata->config.shift)
  2055. pdata->ops = &shifted_smsc911x_ops;
  2056. pm_runtime_enable(&pdev->dev);
  2057. pm_runtime_get_sync(&pdev->dev);
  2058. retval = smsc911x_init(dev);
  2059. if (retval < 0)
  2060. goto out_disable_resources;
  2061. /* configure irq polarity and type before connecting isr */
  2062. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  2063. intcfg |= INT_CFG_IRQ_POL_;
  2064. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  2065. intcfg |= INT_CFG_IRQ_TYPE_;
  2066. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  2067. /* Ensure interrupts are globally disabled before connecting ISR */
  2068. smsc911x_disable_irq_chip(dev);
  2069. retval = request_irq(dev->irq, smsc911x_irqhandler,
  2070. irq_flags | IRQF_SHARED, dev->name, dev);
  2071. if (retval) {
  2072. SMSC_WARN(pdata, probe,
  2073. "Unable to claim requested irq: %d", dev->irq);
  2074. goto out_disable_resources;
  2075. }
  2076. netif_carrier_off(dev);
  2077. retval = register_netdev(dev);
  2078. if (retval) {
  2079. SMSC_WARN(pdata, probe, "Error %i registering device", retval);
  2080. goto out_free_irq;
  2081. } else {
  2082. SMSC_TRACE(pdata, probe,
  2083. "Network interface: \"%s\"", dev->name);
  2084. }
  2085. retval = smsc911x_mii_init(pdev, dev);
  2086. if (retval) {
  2087. SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
  2088. goto out_unregister_netdev_5;
  2089. }
  2090. spin_lock_irq(&pdata->mac_lock);
  2091. /* Check if mac address has been specified when bringing interface up */
  2092. if (is_valid_ether_addr(dev->dev_addr)) {
  2093. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2094. SMSC_TRACE(pdata, probe,
  2095. "MAC Address is specified by configuration");
  2096. } else if (is_valid_ether_addr(pdata->config.mac)) {
  2097. memcpy(dev->dev_addr, pdata->config.mac, ETH_ALEN);
  2098. SMSC_TRACE(pdata, probe,
  2099. "MAC Address specified by platform data");
  2100. } else {
  2101. /* Try reading mac address from device. if EEPROM is present
  2102. * it will already have been set */
  2103. smsc_get_mac(dev);
  2104. if (is_valid_ether_addr(dev->dev_addr)) {
  2105. /* eeprom values are valid so use them */
  2106. SMSC_TRACE(pdata, probe,
  2107. "Mac Address is read from LAN911x EEPROM");
  2108. } else {
  2109. /* eeprom values are invalid, generate random MAC */
  2110. eth_hw_addr_random(dev);
  2111. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  2112. SMSC_TRACE(pdata, probe,
  2113. "MAC Address is set to eth_random_addr");
  2114. }
  2115. }
  2116. spin_unlock_irq(&pdata->mac_lock);
  2117. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  2118. return 0;
  2119. out_unregister_netdev_5:
  2120. unregister_netdev(dev);
  2121. out_free_irq:
  2122. free_irq(dev->irq, dev);
  2123. out_disable_resources:
  2124. pm_runtime_put(&pdev->dev);
  2125. pm_runtime_disable(&pdev->dev);
  2126. (void)smsc911x_disable_resources(pdev);
  2127. out_enable_resources_fail:
  2128. smsc911x_free_resources(pdev);
  2129. out_request_resources_fail:
  2130. iounmap(pdata->ioaddr);
  2131. free_netdev(dev);
  2132. out_release_io_1:
  2133. release_mem_region(res->start, resource_size(res));
  2134. out_0:
  2135. return retval;
  2136. }
  2137. #ifdef CONFIG_PM
  2138. /* This implementation assumes the devices remains powered on its VDDVARIO
  2139. * pins during suspend. */
  2140. /* TODO: implement freeze/thaw callbacks for hibernation.*/
  2141. static int smsc911x_suspend(struct device *dev)
  2142. {
  2143. struct net_device *ndev = dev_get_drvdata(dev);
  2144. struct smsc911x_data *pdata = netdev_priv(ndev);
  2145. /* enable wake on LAN, energy detection and the external PME
  2146. * signal. */
  2147. smsc911x_reg_write(pdata, PMT_CTRL,
  2148. PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
  2149. PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
  2150. return 0;
  2151. }
  2152. static int smsc911x_resume(struct device *dev)
  2153. {
  2154. struct net_device *ndev = dev_get_drvdata(dev);
  2155. struct smsc911x_data *pdata = netdev_priv(ndev);
  2156. unsigned int to = 100;
  2157. /* Note 3.11 from the datasheet:
  2158. * "When the LAN9220 is in a power saving state, a write of any
  2159. * data to the BYTE_TEST register will wake-up the device."
  2160. */
  2161. smsc911x_reg_write(pdata, BYTE_TEST, 0);
  2162. /* poll the READY bit in PMT_CTRL. Any other access to the device is
  2163. * forbidden while this bit isn't set. Try for 100ms and return -EIO
  2164. * if it failed. */
  2165. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
  2166. udelay(1000);
  2167. return (to == 0) ? -EIO : 0;
  2168. }
  2169. static const struct dev_pm_ops smsc911x_pm_ops = {
  2170. .suspend = smsc911x_suspend,
  2171. .resume = smsc911x_resume,
  2172. };
  2173. #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
  2174. #else
  2175. #define SMSC911X_PM_OPS NULL
  2176. #endif
  2177. #ifdef CONFIG_OF
  2178. static const struct of_device_id smsc911x_dt_ids[] = {
  2179. { .compatible = "smsc,lan9115", },
  2180. { /* sentinel */ }
  2181. };
  2182. MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
  2183. #endif
  2184. static struct platform_driver smsc911x_driver = {
  2185. .probe = smsc911x_drv_probe,
  2186. .remove = smsc911x_drv_remove,
  2187. .driver = {
  2188. .name = SMSC_CHIPNAME,
  2189. .pm = SMSC911X_PM_OPS,
  2190. .of_match_table = of_match_ptr(smsc911x_dt_ids),
  2191. },
  2192. };
  2193. /* Entry point for loading the module */
  2194. static int __init smsc911x_init_module(void)
  2195. {
  2196. SMSC_INITIALIZE();
  2197. return platform_driver_register(&smsc911x_driver);
  2198. }
  2199. /* entry point for unloading the module */
  2200. static void __exit smsc911x_cleanup_module(void)
  2201. {
  2202. platform_driver_unregister(&smsc911x_driver);
  2203. }
  2204. module_init(smsc911x_init_module);
  2205. module_exit(smsc911x_cleanup_module);