fimc-lite.c 45 KB

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  1. /*
  2. * Samsung EXYNOS FIMC-LITE (camera host interface) driver
  3. *
  4. * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
  5. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  12. #include <linux/bug.h>
  13. #include <linux/clk.h>
  14. #include <linux/device.h>
  15. #include <linux/errno.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/types.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/slab.h>
  25. #include <linux/videodev2.h>
  26. #include <media/v4l2-device.h>
  27. #include <media/v4l2-ioctl.h>
  28. #include <media/v4l2-mem2mem.h>
  29. #include <media/videobuf2-core.h>
  30. #include <media/videobuf2-dma-contig.h>
  31. #include <media/exynos-fimc.h>
  32. #include "common.h"
  33. #include "fimc-core.h"
  34. #include "fimc-lite.h"
  35. #include "fimc-lite-reg.h"
  36. static int debug;
  37. module_param(debug, int, 0644);
  38. static const struct fimc_fmt fimc_lite_formats[] = {
  39. {
  40. .name = "YUV 4:2:2 packed, YCbYCr",
  41. .fourcc = V4L2_PIX_FMT_YUYV,
  42. .colorspace = V4L2_COLORSPACE_JPEG,
  43. .depth = { 16 },
  44. .color = FIMC_FMT_YCBYCR422,
  45. .memplanes = 1,
  46. .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
  47. .flags = FMT_FLAGS_YUV,
  48. }, {
  49. .name = "YUV 4:2:2 packed, CbYCrY",
  50. .fourcc = V4L2_PIX_FMT_UYVY,
  51. .colorspace = V4L2_COLORSPACE_JPEG,
  52. .depth = { 16 },
  53. .color = FIMC_FMT_CBYCRY422,
  54. .memplanes = 1,
  55. .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
  56. .flags = FMT_FLAGS_YUV,
  57. }, {
  58. .name = "YUV 4:2:2 packed, CrYCbY",
  59. .fourcc = V4L2_PIX_FMT_VYUY,
  60. .colorspace = V4L2_COLORSPACE_JPEG,
  61. .depth = { 16 },
  62. .color = FIMC_FMT_CRYCBY422,
  63. .memplanes = 1,
  64. .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
  65. .flags = FMT_FLAGS_YUV,
  66. }, {
  67. .name = "YUV 4:2:2 packed, YCrYCb",
  68. .fourcc = V4L2_PIX_FMT_YVYU,
  69. .colorspace = V4L2_COLORSPACE_JPEG,
  70. .depth = { 16 },
  71. .color = FIMC_FMT_YCRYCB422,
  72. .memplanes = 1,
  73. .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
  74. .flags = FMT_FLAGS_YUV,
  75. }, {
  76. .name = "RAW8 (GRBG)",
  77. .fourcc = V4L2_PIX_FMT_SGRBG8,
  78. .colorspace = V4L2_COLORSPACE_SRGB,
  79. .depth = { 8 },
  80. .color = FIMC_FMT_RAW8,
  81. .memplanes = 1,
  82. .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
  83. .flags = FMT_FLAGS_RAW_BAYER,
  84. }, {
  85. .name = "RAW10 (GRBG)",
  86. .fourcc = V4L2_PIX_FMT_SGRBG10,
  87. .colorspace = V4L2_COLORSPACE_SRGB,
  88. .depth = { 16 },
  89. .color = FIMC_FMT_RAW10,
  90. .memplanes = 1,
  91. .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
  92. .flags = FMT_FLAGS_RAW_BAYER,
  93. }, {
  94. .name = "RAW12 (GRBG)",
  95. .fourcc = V4L2_PIX_FMT_SGRBG12,
  96. .colorspace = V4L2_COLORSPACE_SRGB,
  97. .depth = { 16 },
  98. .color = FIMC_FMT_RAW12,
  99. .memplanes = 1,
  100. .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
  101. .flags = FMT_FLAGS_RAW_BAYER,
  102. },
  103. };
  104. /**
  105. * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
  106. * @pixelformat: fourcc to match, ignored if null
  107. * @mbus_code: media bus code to match, ignored if null
  108. * @mask: the color format flags to match
  109. * @index: index to the fimc_lite_formats array, ignored if negative
  110. */
  111. static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
  112. const u32 *mbus_code, unsigned int mask, int index)
  113. {
  114. const struct fimc_fmt *fmt, *def_fmt = NULL;
  115. unsigned int i;
  116. int id = 0;
  117. if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
  118. return NULL;
  119. for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
  120. fmt = &fimc_lite_formats[i];
  121. if (mask && !(fmt->flags & mask))
  122. continue;
  123. if (pixelformat && fmt->fourcc == *pixelformat)
  124. return fmt;
  125. if (mbus_code && fmt->mbus_code == *mbus_code)
  126. return fmt;
  127. if (index == id)
  128. def_fmt = fmt;
  129. id++;
  130. }
  131. return def_fmt;
  132. }
  133. static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
  134. {
  135. struct fimc_source_info *si;
  136. unsigned long flags;
  137. if (fimc->sensor == NULL)
  138. return -ENXIO;
  139. if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL)
  140. return -EINVAL;
  141. /* Get sensor configuration data from the sensor subdev */
  142. si = v4l2_get_subdev_hostdata(fimc->sensor);
  143. if (!si)
  144. return -EINVAL;
  145. spin_lock_irqsave(&fimc->slock, flags);
  146. flite_hw_set_camera_bus(fimc, si);
  147. flite_hw_set_source_format(fimc, &fimc->inp_frame);
  148. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  149. flite_hw_set_dma_buf_mask(fimc, 0);
  150. flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
  151. flite_hw_set_interrupt_mask(fimc);
  152. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  153. if (debug > 0)
  154. flite_hw_dump_regs(fimc, __func__);
  155. spin_unlock_irqrestore(&fimc->slock, flags);
  156. return 0;
  157. }
  158. /*
  159. * Reinitialize the driver so it is ready to start the streaming again.
  160. * Set fimc->state to indicate stream off and the hardware shut down state.
  161. * If not suspending (@suspend is false), return any buffers to videobuf2.
  162. * Otherwise put any owned buffers onto the pending buffers queue, so they
  163. * can be re-spun when the device is being resumed. Also perform FIMC
  164. * software reset and disable streaming on the whole pipeline if required.
  165. */
  166. static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
  167. {
  168. struct flite_buffer *buf;
  169. unsigned long flags;
  170. bool streaming;
  171. spin_lock_irqsave(&fimc->slock, flags);
  172. streaming = fimc->state & (1 << ST_SENSOR_STREAM);
  173. fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
  174. 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
  175. if (suspend)
  176. fimc->state |= (1 << ST_FLITE_SUSPENDED);
  177. else
  178. fimc->state &= ~(1 << ST_FLITE_PENDING |
  179. 1 << ST_FLITE_SUSPENDED);
  180. /* Release unused buffers */
  181. while (!suspend && !list_empty(&fimc->pending_buf_q)) {
  182. buf = fimc_lite_pending_queue_pop(fimc);
  183. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  184. }
  185. /* If suspending put unused buffers onto pending queue */
  186. while (!list_empty(&fimc->active_buf_q)) {
  187. buf = fimc_lite_active_queue_pop(fimc);
  188. if (suspend)
  189. fimc_lite_pending_queue_add(fimc, buf);
  190. else
  191. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  192. }
  193. spin_unlock_irqrestore(&fimc->slock, flags);
  194. flite_hw_reset(fimc);
  195. if (!streaming)
  196. return 0;
  197. return fimc_pipeline_call(&fimc->ve, set_stream, 0);
  198. }
  199. static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
  200. {
  201. unsigned long flags;
  202. if (!fimc_lite_active(fimc))
  203. return 0;
  204. spin_lock_irqsave(&fimc->slock, flags);
  205. set_bit(ST_FLITE_OFF, &fimc->state);
  206. flite_hw_capture_stop(fimc);
  207. spin_unlock_irqrestore(&fimc->slock, flags);
  208. wait_event_timeout(fimc->irq_queue,
  209. !test_bit(ST_FLITE_OFF, &fimc->state),
  210. (2*HZ/10)); /* 200 ms */
  211. return fimc_lite_reinit(fimc, suspend);
  212. }
  213. /* Must be called with fimc.slock spinlock held. */
  214. static void fimc_lite_config_update(struct fimc_lite *fimc)
  215. {
  216. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  217. flite_hw_set_dma_window(fimc, &fimc->out_frame);
  218. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  219. clear_bit(ST_FLITE_CONFIG, &fimc->state);
  220. }
  221. static irqreturn_t flite_irq_handler(int irq, void *priv)
  222. {
  223. struct fimc_lite *fimc = priv;
  224. struct flite_buffer *vbuf;
  225. unsigned long flags;
  226. struct timeval *tv;
  227. struct timespec ts;
  228. u32 intsrc;
  229. spin_lock_irqsave(&fimc->slock, flags);
  230. intsrc = flite_hw_get_interrupt_source(fimc);
  231. flite_hw_clear_pending_irq(fimc);
  232. if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
  233. wake_up(&fimc->irq_queue);
  234. goto done;
  235. }
  236. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
  237. clear_bit(ST_FLITE_RUN, &fimc->state);
  238. fimc->events.data_overflow++;
  239. }
  240. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
  241. flite_hw_clear_last_capture_end(fimc);
  242. clear_bit(ST_FLITE_STREAM, &fimc->state);
  243. wake_up(&fimc->irq_queue);
  244. }
  245. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  246. goto done;
  247. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
  248. test_bit(ST_FLITE_RUN, &fimc->state) &&
  249. !list_empty(&fimc->pending_buf_q)) {
  250. vbuf = fimc_lite_pending_queue_pop(fimc);
  251. flite_hw_set_dma_buffer(fimc, vbuf);
  252. fimc_lite_active_queue_add(fimc, vbuf);
  253. }
  254. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMEND) &&
  255. test_bit(ST_FLITE_RUN, &fimc->state) &&
  256. !list_empty(&fimc->active_buf_q)) {
  257. vbuf = fimc_lite_active_queue_pop(fimc);
  258. ktime_get_ts(&ts);
  259. tv = &vbuf->vb.v4l2_buf.timestamp;
  260. tv->tv_sec = ts.tv_sec;
  261. tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
  262. vbuf->vb.v4l2_buf.sequence = fimc->frame_count++;
  263. flite_hw_mask_dma_buffer(fimc, vbuf->index);
  264. vb2_buffer_done(&vbuf->vb, VB2_BUF_STATE_DONE);
  265. }
  266. if (test_bit(ST_FLITE_CONFIG, &fimc->state))
  267. fimc_lite_config_update(fimc);
  268. if (list_empty(&fimc->pending_buf_q)) {
  269. flite_hw_capture_stop(fimc);
  270. clear_bit(ST_FLITE_STREAM, &fimc->state);
  271. }
  272. done:
  273. set_bit(ST_FLITE_RUN, &fimc->state);
  274. spin_unlock_irqrestore(&fimc->slock, flags);
  275. return IRQ_HANDLED;
  276. }
  277. static int start_streaming(struct vb2_queue *q, unsigned int count)
  278. {
  279. struct fimc_lite *fimc = q->drv_priv;
  280. unsigned long flags;
  281. int ret;
  282. spin_lock_irqsave(&fimc->slock, flags);
  283. fimc->buf_index = 0;
  284. fimc->frame_count = 0;
  285. spin_unlock_irqrestore(&fimc->slock, flags);
  286. ret = fimc_lite_hw_init(fimc, false);
  287. if (ret) {
  288. fimc_lite_reinit(fimc, false);
  289. return ret;
  290. }
  291. set_bit(ST_FLITE_PENDING, &fimc->state);
  292. if (!list_empty(&fimc->active_buf_q) &&
  293. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  294. flite_hw_capture_start(fimc);
  295. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  296. fimc_pipeline_call(&fimc->ve, set_stream, 1);
  297. }
  298. if (debug > 0)
  299. flite_hw_dump_regs(fimc, __func__);
  300. return 0;
  301. }
  302. static void stop_streaming(struct vb2_queue *q)
  303. {
  304. struct fimc_lite *fimc = q->drv_priv;
  305. if (!fimc_lite_active(fimc))
  306. return;
  307. fimc_lite_stop_capture(fimc, false);
  308. }
  309. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
  310. unsigned int *num_buffers, unsigned int *num_planes,
  311. unsigned int sizes[], void *allocators[])
  312. {
  313. const struct v4l2_pix_format_mplane *pixm = NULL;
  314. struct fimc_lite *fimc = vq->drv_priv;
  315. struct flite_frame *frame = &fimc->out_frame;
  316. const struct fimc_fmt *fmt = frame->fmt;
  317. unsigned long wh;
  318. int i;
  319. if (pfmt) {
  320. pixm = &pfmt->fmt.pix_mp;
  321. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0, -1);
  322. wh = pixm->width * pixm->height;
  323. } else {
  324. wh = frame->f_width * frame->f_height;
  325. }
  326. if (fmt == NULL)
  327. return -EINVAL;
  328. *num_planes = fmt->memplanes;
  329. for (i = 0; i < fmt->memplanes; i++) {
  330. unsigned int size = (wh * fmt->depth[i]) / 8;
  331. if (pixm)
  332. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  333. else
  334. sizes[i] = size;
  335. allocators[i] = fimc->alloc_ctx;
  336. }
  337. return 0;
  338. }
  339. static int buffer_prepare(struct vb2_buffer *vb)
  340. {
  341. struct vb2_queue *vq = vb->vb2_queue;
  342. struct fimc_lite *fimc = vq->drv_priv;
  343. int i;
  344. if (fimc->out_frame.fmt == NULL)
  345. return -EINVAL;
  346. for (i = 0; i < fimc->out_frame.fmt->memplanes; i++) {
  347. unsigned long size = fimc->payload[i];
  348. if (vb2_plane_size(vb, i) < size) {
  349. v4l2_err(&fimc->ve.vdev,
  350. "User buffer too small (%ld < %ld)\n",
  351. vb2_plane_size(vb, i), size);
  352. return -EINVAL;
  353. }
  354. vb2_set_plane_payload(vb, i, size);
  355. }
  356. return 0;
  357. }
  358. static void buffer_queue(struct vb2_buffer *vb)
  359. {
  360. struct flite_buffer *buf
  361. = container_of(vb, struct flite_buffer, vb);
  362. struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
  363. unsigned long flags;
  364. spin_lock_irqsave(&fimc->slock, flags);
  365. buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
  366. buf->index = fimc->buf_index++;
  367. if (fimc->buf_index >= fimc->reqbufs_count)
  368. fimc->buf_index = 0;
  369. if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
  370. !test_bit(ST_FLITE_STREAM, &fimc->state) &&
  371. list_empty(&fimc->active_buf_q)) {
  372. flite_hw_set_dma_buffer(fimc, buf);
  373. fimc_lite_active_queue_add(fimc, buf);
  374. } else {
  375. fimc_lite_pending_queue_add(fimc, buf);
  376. }
  377. if (vb2_is_streaming(&fimc->vb_queue) &&
  378. !list_empty(&fimc->pending_buf_q) &&
  379. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  380. flite_hw_capture_start(fimc);
  381. spin_unlock_irqrestore(&fimc->slock, flags);
  382. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  383. fimc_pipeline_call(&fimc->ve, set_stream, 1);
  384. return;
  385. }
  386. spin_unlock_irqrestore(&fimc->slock, flags);
  387. }
  388. static const struct vb2_ops fimc_lite_qops = {
  389. .queue_setup = queue_setup,
  390. .buf_prepare = buffer_prepare,
  391. .buf_queue = buffer_queue,
  392. .wait_prepare = vb2_ops_wait_prepare,
  393. .wait_finish = vb2_ops_wait_finish,
  394. .start_streaming = start_streaming,
  395. .stop_streaming = stop_streaming,
  396. };
  397. static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
  398. {
  399. unsigned long flags;
  400. spin_lock_irqsave(&fimc->slock, flags);
  401. memset(&fimc->events, 0, sizeof(fimc->events));
  402. spin_unlock_irqrestore(&fimc->slock, flags);
  403. }
  404. static int fimc_lite_open(struct file *file)
  405. {
  406. struct fimc_lite *fimc = video_drvdata(file);
  407. struct media_entity *me = &fimc->ve.vdev.entity;
  408. int ret;
  409. mutex_lock(&fimc->lock);
  410. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) {
  411. ret = -EBUSY;
  412. goto unlock;
  413. }
  414. set_bit(ST_FLITE_IN_USE, &fimc->state);
  415. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  416. if (ret < 0)
  417. goto unlock;
  418. ret = v4l2_fh_open(file);
  419. if (ret < 0)
  420. goto err_pm;
  421. if (!v4l2_fh_is_singular_file(file) ||
  422. atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  423. goto unlock;
  424. mutex_lock(&me->parent->graph_mutex);
  425. ret = fimc_pipeline_call(&fimc->ve, open, me, true);
  426. /* Mark video pipeline ending at this video node as in use. */
  427. if (ret == 0)
  428. me->use_count++;
  429. mutex_unlock(&me->parent->graph_mutex);
  430. if (!ret) {
  431. fimc_lite_clear_event_counters(fimc);
  432. goto unlock;
  433. }
  434. v4l2_fh_release(file);
  435. err_pm:
  436. pm_runtime_put_sync(&fimc->pdev->dev);
  437. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  438. unlock:
  439. mutex_unlock(&fimc->lock);
  440. return ret;
  441. }
  442. static int fimc_lite_release(struct file *file)
  443. {
  444. struct fimc_lite *fimc = video_drvdata(file);
  445. struct media_entity *entity = &fimc->ve.vdev.entity;
  446. mutex_lock(&fimc->lock);
  447. if (v4l2_fh_is_singular_file(file) &&
  448. atomic_read(&fimc->out_path) == FIMC_IO_DMA) {
  449. if (fimc->streaming) {
  450. media_entity_pipeline_stop(entity);
  451. fimc->streaming = false;
  452. }
  453. fimc_lite_stop_capture(fimc, false);
  454. fimc_pipeline_call(&fimc->ve, close);
  455. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  456. mutex_lock(&entity->parent->graph_mutex);
  457. entity->use_count--;
  458. mutex_unlock(&entity->parent->graph_mutex);
  459. }
  460. _vb2_fop_release(file, NULL);
  461. pm_runtime_put(&fimc->pdev->dev);
  462. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  463. mutex_unlock(&fimc->lock);
  464. return 0;
  465. }
  466. static const struct v4l2_file_operations fimc_lite_fops = {
  467. .owner = THIS_MODULE,
  468. .open = fimc_lite_open,
  469. .release = fimc_lite_release,
  470. .poll = vb2_fop_poll,
  471. .unlocked_ioctl = video_ioctl2,
  472. .mmap = vb2_fop_mmap,
  473. };
  474. /*
  475. * Format and crop negotiation helpers
  476. */
  477. static const struct fimc_fmt *fimc_lite_subdev_try_fmt(struct fimc_lite *fimc,
  478. struct v4l2_subdev_pad_config *cfg,
  479. struct v4l2_subdev_format *format)
  480. {
  481. struct flite_drvdata *dd = fimc->dd;
  482. struct v4l2_mbus_framefmt *mf = &format->format;
  483. const struct fimc_fmt *fmt = NULL;
  484. if (format->pad == FLITE_SD_PAD_SINK) {
  485. v4l_bound_align_image(&mf->width, 8, dd->max_width,
  486. ffs(dd->out_width_align) - 1,
  487. &mf->height, 0, dd->max_height, 0, 0);
  488. fmt = fimc_lite_find_format(NULL, &mf->code, 0, 0);
  489. if (WARN_ON(!fmt))
  490. return NULL;
  491. mf->colorspace = fmt->colorspace;
  492. mf->code = fmt->mbus_code;
  493. } else {
  494. struct flite_frame *sink = &fimc->inp_frame;
  495. struct v4l2_mbus_framefmt *sink_fmt;
  496. struct v4l2_rect *rect;
  497. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  498. sink_fmt = v4l2_subdev_get_try_format(&fimc->subdev, cfg,
  499. FLITE_SD_PAD_SINK);
  500. mf->code = sink_fmt->code;
  501. mf->colorspace = sink_fmt->colorspace;
  502. rect = v4l2_subdev_get_try_crop(&fimc->subdev, cfg,
  503. FLITE_SD_PAD_SINK);
  504. } else {
  505. mf->code = sink->fmt->mbus_code;
  506. mf->colorspace = sink->fmt->colorspace;
  507. rect = &sink->rect;
  508. }
  509. /* Allow changing format only on sink pad */
  510. mf->width = rect->width;
  511. mf->height = rect->height;
  512. }
  513. mf->field = V4L2_FIELD_NONE;
  514. v4l2_dbg(1, debug, &fimc->subdev, "code: %#x (%d), %dx%d\n",
  515. mf->code, mf->colorspace, mf->width, mf->height);
  516. return fmt;
  517. }
  518. static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
  519. {
  520. struct flite_frame *frame = &fimc->inp_frame;
  521. v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
  522. &r->height, 0, frame->f_height, 0, 0);
  523. /* Adjust left/top if cropping rectangle got out of bounds */
  524. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  525. r->left = round_down(r->left, fimc->dd->win_hor_offs_align);
  526. r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height);
  527. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d\n",
  528. r->left, r->top, r->width, r->height,
  529. frame->f_width, frame->f_height);
  530. }
  531. static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
  532. {
  533. struct flite_frame *frame = &fimc->out_frame;
  534. struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
  535. /* Scaling is not supported so we enforce compose rectangle size
  536. same as size of the sink crop rectangle. */
  537. r->width = crop_rect->width;
  538. r->height = crop_rect->height;
  539. /* Adjust left/top if the composing rectangle got out of bounds */
  540. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  541. r->left = round_down(r->left, fimc->dd->out_hor_offs_align);
  542. r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
  543. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d\n",
  544. r->left, r->top, r->width, r->height,
  545. frame->f_width, frame->f_height);
  546. }
  547. /*
  548. * Video node ioctl operations
  549. */
  550. static int fimc_lite_querycap(struct file *file, void *priv,
  551. struct v4l2_capability *cap)
  552. {
  553. struct fimc_lite *fimc = video_drvdata(file);
  554. strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
  555. strlcpy(cap->card, FIMC_LITE_DRV_NAME, sizeof(cap->card));
  556. snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
  557. dev_name(&fimc->pdev->dev));
  558. cap->device_caps = V4L2_CAP_STREAMING;
  559. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  560. return 0;
  561. }
  562. static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv,
  563. struct v4l2_fmtdesc *f)
  564. {
  565. const struct fimc_fmt *fmt;
  566. if (f->index >= ARRAY_SIZE(fimc_lite_formats))
  567. return -EINVAL;
  568. fmt = &fimc_lite_formats[f->index];
  569. strlcpy(f->description, fmt->name, sizeof(f->description));
  570. f->pixelformat = fmt->fourcc;
  571. return 0;
  572. }
  573. static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
  574. struct v4l2_format *f)
  575. {
  576. struct fimc_lite *fimc = video_drvdata(file);
  577. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  578. struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
  579. struct flite_frame *frame = &fimc->out_frame;
  580. const struct fimc_fmt *fmt = frame->fmt;
  581. plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
  582. plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
  583. pixm->num_planes = fmt->memplanes;
  584. pixm->pixelformat = fmt->fourcc;
  585. pixm->width = frame->f_width;
  586. pixm->height = frame->f_height;
  587. pixm->field = V4L2_FIELD_NONE;
  588. pixm->colorspace = fmt->colorspace;
  589. return 0;
  590. }
  591. static int fimc_lite_try_fmt(struct fimc_lite *fimc,
  592. struct v4l2_pix_format_mplane *pixm,
  593. const struct fimc_fmt **ffmt)
  594. {
  595. u32 bpl = pixm->plane_fmt[0].bytesperline;
  596. struct flite_drvdata *dd = fimc->dd;
  597. const struct fimc_fmt *inp_fmt = fimc->inp_frame.fmt;
  598. const struct fimc_fmt *fmt;
  599. if (WARN_ON(inp_fmt == NULL))
  600. return -EINVAL;
  601. /*
  602. * We allow some flexibility only for YUV formats. In case of raw
  603. * raw Bayer the FIMC-LITE's output format must match its camera
  604. * interface input format.
  605. */
  606. if (inp_fmt->flags & FMT_FLAGS_YUV)
  607. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL,
  608. inp_fmt->flags, 0);
  609. else
  610. fmt = inp_fmt;
  611. if (WARN_ON(fmt == NULL))
  612. return -EINVAL;
  613. if (ffmt)
  614. *ffmt = fmt;
  615. v4l_bound_align_image(&pixm->width, 8, dd->max_width,
  616. ffs(dd->out_width_align) - 1,
  617. &pixm->height, 0, dd->max_height, 0, 0);
  618. if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
  619. pixm->plane_fmt[0].bytesperline = (pixm->width *
  620. fmt->depth[0]) / 8;
  621. if (pixm->plane_fmt[0].sizeimage == 0)
  622. pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
  623. fmt->depth[0]) / 8;
  624. pixm->num_planes = fmt->memplanes;
  625. pixm->pixelformat = fmt->fourcc;
  626. pixm->colorspace = fmt->colorspace;
  627. pixm->field = V4L2_FIELD_NONE;
  628. return 0;
  629. }
  630. static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
  631. struct v4l2_format *f)
  632. {
  633. struct fimc_lite *fimc = video_drvdata(file);
  634. return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
  635. }
  636. static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
  637. struct v4l2_format *f)
  638. {
  639. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  640. struct fimc_lite *fimc = video_drvdata(file);
  641. struct flite_frame *frame = &fimc->out_frame;
  642. const struct fimc_fmt *fmt = NULL;
  643. int ret;
  644. if (vb2_is_busy(&fimc->vb_queue))
  645. return -EBUSY;
  646. ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
  647. if (ret < 0)
  648. return ret;
  649. frame->fmt = fmt;
  650. fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
  651. pixm->plane_fmt[0].sizeimage);
  652. frame->f_width = pixm->width;
  653. frame->f_height = pixm->height;
  654. return 0;
  655. }
  656. static int fimc_pipeline_validate(struct fimc_lite *fimc)
  657. {
  658. struct v4l2_subdev *sd = &fimc->subdev;
  659. struct v4l2_subdev_format sink_fmt, src_fmt;
  660. struct media_pad *pad;
  661. int ret;
  662. while (1) {
  663. /* Retrieve format at the sink pad */
  664. pad = &sd->entity.pads[0];
  665. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  666. break;
  667. /* Don't call FIMC subdev operation to avoid nested locking */
  668. if (sd == &fimc->subdev) {
  669. struct flite_frame *ff = &fimc->out_frame;
  670. sink_fmt.format.width = ff->f_width;
  671. sink_fmt.format.height = ff->f_height;
  672. sink_fmt.format.code = fimc->inp_frame.fmt->mbus_code;
  673. } else {
  674. sink_fmt.pad = pad->index;
  675. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  676. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
  677. &sink_fmt);
  678. if (ret < 0 && ret != -ENOIOCTLCMD)
  679. return -EPIPE;
  680. }
  681. /* Retrieve format at the source pad */
  682. pad = media_entity_remote_pad(pad);
  683. if (pad == NULL ||
  684. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  685. break;
  686. sd = media_entity_to_v4l2_subdev(pad->entity);
  687. src_fmt.pad = pad->index;
  688. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  689. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  690. if (ret < 0 && ret != -ENOIOCTLCMD)
  691. return -EPIPE;
  692. if (src_fmt.format.width != sink_fmt.format.width ||
  693. src_fmt.format.height != sink_fmt.format.height ||
  694. src_fmt.format.code != sink_fmt.format.code)
  695. return -EPIPE;
  696. }
  697. return 0;
  698. }
  699. static int fimc_lite_streamon(struct file *file, void *priv,
  700. enum v4l2_buf_type type)
  701. {
  702. struct fimc_lite *fimc = video_drvdata(file);
  703. struct media_entity *entity = &fimc->ve.vdev.entity;
  704. int ret;
  705. if (fimc_lite_active(fimc))
  706. return -EBUSY;
  707. ret = media_entity_pipeline_start(entity, &fimc->ve.pipe->mp);
  708. if (ret < 0)
  709. return ret;
  710. ret = fimc_pipeline_validate(fimc);
  711. if (ret < 0)
  712. goto err_p_stop;
  713. fimc->sensor = fimc_find_remote_sensor(&fimc->subdev.entity);
  714. ret = vb2_ioctl_streamon(file, priv, type);
  715. if (!ret) {
  716. fimc->streaming = true;
  717. return ret;
  718. }
  719. err_p_stop:
  720. media_entity_pipeline_stop(entity);
  721. return 0;
  722. }
  723. static int fimc_lite_streamoff(struct file *file, void *priv,
  724. enum v4l2_buf_type type)
  725. {
  726. struct fimc_lite *fimc = video_drvdata(file);
  727. int ret;
  728. ret = vb2_ioctl_streamoff(file, priv, type);
  729. if (ret < 0)
  730. return ret;
  731. media_entity_pipeline_stop(&fimc->ve.vdev.entity);
  732. fimc->streaming = false;
  733. return 0;
  734. }
  735. static int fimc_lite_reqbufs(struct file *file, void *priv,
  736. struct v4l2_requestbuffers *reqbufs)
  737. {
  738. struct fimc_lite *fimc = video_drvdata(file);
  739. int ret;
  740. reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
  741. ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
  742. if (!ret)
  743. fimc->reqbufs_count = reqbufs->count;
  744. return ret;
  745. }
  746. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  747. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  748. {
  749. if (a->left < b->left || a->top < b->top)
  750. return 0;
  751. if (a->left + a->width > b->left + b->width)
  752. return 0;
  753. if (a->top + a->height > b->top + b->height)
  754. return 0;
  755. return 1;
  756. }
  757. static int fimc_lite_g_selection(struct file *file, void *fh,
  758. struct v4l2_selection *sel)
  759. {
  760. struct fimc_lite *fimc = video_drvdata(file);
  761. struct flite_frame *f = &fimc->out_frame;
  762. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  763. return -EINVAL;
  764. switch (sel->target) {
  765. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  766. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  767. sel->r.left = 0;
  768. sel->r.top = 0;
  769. sel->r.width = f->f_width;
  770. sel->r.height = f->f_height;
  771. return 0;
  772. case V4L2_SEL_TGT_COMPOSE:
  773. sel->r = f->rect;
  774. return 0;
  775. }
  776. return -EINVAL;
  777. }
  778. static int fimc_lite_s_selection(struct file *file, void *fh,
  779. struct v4l2_selection *sel)
  780. {
  781. struct fimc_lite *fimc = video_drvdata(file);
  782. struct flite_frame *f = &fimc->out_frame;
  783. struct v4l2_rect rect = sel->r;
  784. unsigned long flags;
  785. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
  786. sel->target != V4L2_SEL_TGT_COMPOSE)
  787. return -EINVAL;
  788. fimc_lite_try_compose(fimc, &rect);
  789. if ((sel->flags & V4L2_SEL_FLAG_LE) &&
  790. !enclosed_rectangle(&rect, &sel->r))
  791. return -ERANGE;
  792. if ((sel->flags & V4L2_SEL_FLAG_GE) &&
  793. !enclosed_rectangle(&sel->r, &rect))
  794. return -ERANGE;
  795. sel->r = rect;
  796. spin_lock_irqsave(&fimc->slock, flags);
  797. f->rect = rect;
  798. set_bit(ST_FLITE_CONFIG, &fimc->state);
  799. spin_unlock_irqrestore(&fimc->slock, flags);
  800. return 0;
  801. }
  802. static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
  803. .vidioc_querycap = fimc_lite_querycap,
  804. .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane,
  805. .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane,
  806. .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane,
  807. .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane,
  808. .vidioc_g_selection = fimc_lite_g_selection,
  809. .vidioc_s_selection = fimc_lite_s_selection,
  810. .vidioc_reqbufs = fimc_lite_reqbufs,
  811. .vidioc_querybuf = vb2_ioctl_querybuf,
  812. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  813. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  814. .vidioc_qbuf = vb2_ioctl_qbuf,
  815. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  816. .vidioc_streamon = fimc_lite_streamon,
  817. .vidioc_streamoff = fimc_lite_streamoff,
  818. };
  819. /* Capture subdev media entity operations */
  820. static int fimc_lite_link_setup(struct media_entity *entity,
  821. const struct media_pad *local,
  822. const struct media_pad *remote, u32 flags)
  823. {
  824. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  825. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  826. unsigned int remote_ent_type = media_entity_type(remote->entity);
  827. int ret = 0;
  828. if (WARN_ON(fimc == NULL))
  829. return 0;
  830. v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x\n",
  831. __func__, remote->entity->name, local->entity->name,
  832. flags, fimc->source_subdev_grp_id);
  833. switch (local->index) {
  834. case FLITE_SD_PAD_SINK:
  835. if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV) {
  836. ret = -EINVAL;
  837. break;
  838. }
  839. if (flags & MEDIA_LNK_FL_ENABLED) {
  840. if (fimc->source_subdev_grp_id == 0)
  841. fimc->source_subdev_grp_id = sd->grp_id;
  842. else
  843. ret = -EBUSY;
  844. } else {
  845. fimc->source_subdev_grp_id = 0;
  846. fimc->sensor = NULL;
  847. }
  848. break;
  849. case FLITE_SD_PAD_SOURCE_DMA:
  850. if (!(flags & MEDIA_LNK_FL_ENABLED))
  851. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  852. else if (remote_ent_type == MEDIA_ENT_T_DEVNODE)
  853. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  854. else
  855. ret = -EINVAL;
  856. break;
  857. case FLITE_SD_PAD_SOURCE_ISP:
  858. if (!(flags & MEDIA_LNK_FL_ENABLED))
  859. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  860. else if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV)
  861. atomic_set(&fimc->out_path, FIMC_IO_ISP);
  862. else
  863. ret = -EINVAL;
  864. break;
  865. default:
  866. v4l2_err(sd, "Invalid pad index\n");
  867. ret = -EINVAL;
  868. }
  869. mb();
  870. return ret;
  871. }
  872. static const struct media_entity_operations fimc_lite_subdev_media_ops = {
  873. .link_setup = fimc_lite_link_setup,
  874. };
  875. static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  876. struct v4l2_subdev_pad_config *cfg,
  877. struct v4l2_subdev_mbus_code_enum *code)
  878. {
  879. const struct fimc_fmt *fmt;
  880. fmt = fimc_lite_find_format(NULL, NULL, 0, code->index);
  881. if (!fmt)
  882. return -EINVAL;
  883. code->code = fmt->mbus_code;
  884. return 0;
  885. }
  886. static struct v4l2_mbus_framefmt *__fimc_lite_subdev_get_try_fmt(
  887. struct v4l2_subdev *sd,
  888. struct v4l2_subdev_pad_config *cfg, unsigned int pad)
  889. {
  890. if (pad != FLITE_SD_PAD_SINK)
  891. pad = FLITE_SD_PAD_SOURCE_DMA;
  892. return v4l2_subdev_get_try_format(sd, cfg, pad);
  893. }
  894. static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
  895. struct v4l2_subdev_pad_config *cfg,
  896. struct v4l2_subdev_format *fmt)
  897. {
  898. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  899. struct v4l2_mbus_framefmt *mf = &fmt->format;
  900. struct flite_frame *f = &fimc->inp_frame;
  901. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  902. mf = __fimc_lite_subdev_get_try_fmt(sd, cfg, fmt->pad);
  903. fmt->format = *mf;
  904. return 0;
  905. }
  906. mutex_lock(&fimc->lock);
  907. mf->colorspace = f->fmt->colorspace;
  908. mf->code = f->fmt->mbus_code;
  909. if (fmt->pad == FLITE_SD_PAD_SINK) {
  910. /* full camera input frame size */
  911. mf->width = f->f_width;
  912. mf->height = f->f_height;
  913. } else {
  914. /* crop size */
  915. mf->width = f->rect.width;
  916. mf->height = f->rect.height;
  917. }
  918. mutex_unlock(&fimc->lock);
  919. return 0;
  920. }
  921. static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
  922. struct v4l2_subdev_pad_config *cfg,
  923. struct v4l2_subdev_format *fmt)
  924. {
  925. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  926. struct v4l2_mbus_framefmt *mf = &fmt->format;
  927. struct flite_frame *sink = &fimc->inp_frame;
  928. struct flite_frame *source = &fimc->out_frame;
  929. const struct fimc_fmt *ffmt;
  930. v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d\n",
  931. fmt->pad, mf->code, mf->width, mf->height);
  932. mutex_lock(&fimc->lock);
  933. if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP &&
  934. sd->entity.stream_count > 0) ||
  935. (atomic_read(&fimc->out_path) == FIMC_IO_DMA &&
  936. vb2_is_busy(&fimc->vb_queue))) {
  937. mutex_unlock(&fimc->lock);
  938. return -EBUSY;
  939. }
  940. ffmt = fimc_lite_subdev_try_fmt(fimc, cfg, fmt);
  941. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  942. struct v4l2_mbus_framefmt *src_fmt;
  943. mf = __fimc_lite_subdev_get_try_fmt(sd, cfg, fmt->pad);
  944. *mf = fmt->format;
  945. if (fmt->pad == FLITE_SD_PAD_SINK) {
  946. unsigned int pad = FLITE_SD_PAD_SOURCE_DMA;
  947. src_fmt = __fimc_lite_subdev_get_try_fmt(sd, cfg, pad);
  948. *src_fmt = *mf;
  949. }
  950. mutex_unlock(&fimc->lock);
  951. return 0;
  952. }
  953. if (fmt->pad == FLITE_SD_PAD_SINK) {
  954. sink->f_width = mf->width;
  955. sink->f_height = mf->height;
  956. sink->fmt = ffmt;
  957. /* Set sink crop rectangle */
  958. sink->rect.width = mf->width;
  959. sink->rect.height = mf->height;
  960. sink->rect.left = 0;
  961. sink->rect.top = 0;
  962. /* Reset source format and crop rectangle */
  963. source->rect = sink->rect;
  964. source->f_width = mf->width;
  965. source->f_height = mf->height;
  966. }
  967. mutex_unlock(&fimc->lock);
  968. return 0;
  969. }
  970. static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
  971. struct v4l2_subdev_pad_config *cfg,
  972. struct v4l2_subdev_selection *sel)
  973. {
  974. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  975. struct flite_frame *f = &fimc->inp_frame;
  976. if ((sel->target != V4L2_SEL_TGT_CROP &&
  977. sel->target != V4L2_SEL_TGT_CROP_BOUNDS) ||
  978. sel->pad != FLITE_SD_PAD_SINK)
  979. return -EINVAL;
  980. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  981. sel->r = *v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
  982. return 0;
  983. }
  984. mutex_lock(&fimc->lock);
  985. if (sel->target == V4L2_SEL_TGT_CROP) {
  986. sel->r = f->rect;
  987. } else {
  988. sel->r.left = 0;
  989. sel->r.top = 0;
  990. sel->r.width = f->f_width;
  991. sel->r.height = f->f_height;
  992. }
  993. mutex_unlock(&fimc->lock);
  994. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  995. __func__, f->rect.left, f->rect.top, f->rect.width,
  996. f->rect.height, f->f_width, f->f_height);
  997. return 0;
  998. }
  999. static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
  1000. struct v4l2_subdev_pad_config *cfg,
  1001. struct v4l2_subdev_selection *sel)
  1002. {
  1003. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1004. struct flite_frame *f = &fimc->inp_frame;
  1005. int ret = 0;
  1006. if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK)
  1007. return -EINVAL;
  1008. mutex_lock(&fimc->lock);
  1009. fimc_lite_try_crop(fimc, &sel->r);
  1010. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  1011. *v4l2_subdev_get_try_crop(sd, cfg, sel->pad) = sel->r;
  1012. } else {
  1013. unsigned long flags;
  1014. spin_lock_irqsave(&fimc->slock, flags);
  1015. f->rect = sel->r;
  1016. /* Same crop rectangle on the source pad */
  1017. fimc->out_frame.rect = sel->r;
  1018. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1019. spin_unlock_irqrestore(&fimc->slock, flags);
  1020. }
  1021. mutex_unlock(&fimc->lock);
  1022. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  1023. __func__, f->rect.left, f->rect.top, f->rect.width,
  1024. f->rect.height, f->f_width, f->f_height);
  1025. return ret;
  1026. }
  1027. static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
  1028. {
  1029. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1030. unsigned long flags;
  1031. int ret;
  1032. /*
  1033. * Find sensor subdev linked to FIMC-LITE directly or through
  1034. * MIPI-CSIS. This is required for configuration where FIMC-LITE
  1035. * is used as a subdev only and feeds data internally to FIMC-IS.
  1036. * The pipeline links are protected through entity.stream_count
  1037. * so there is no need to take the media graph mutex here.
  1038. */
  1039. fimc->sensor = fimc_find_remote_sensor(&sd->entity);
  1040. if (atomic_read(&fimc->out_path) != FIMC_IO_ISP)
  1041. return -ENOIOCTLCMD;
  1042. mutex_lock(&fimc->lock);
  1043. if (on) {
  1044. flite_hw_reset(fimc);
  1045. ret = fimc_lite_hw_init(fimc, true);
  1046. if (!ret) {
  1047. spin_lock_irqsave(&fimc->slock, flags);
  1048. flite_hw_capture_start(fimc);
  1049. spin_unlock_irqrestore(&fimc->slock, flags);
  1050. }
  1051. } else {
  1052. set_bit(ST_FLITE_OFF, &fimc->state);
  1053. spin_lock_irqsave(&fimc->slock, flags);
  1054. flite_hw_capture_stop(fimc);
  1055. spin_unlock_irqrestore(&fimc->slock, flags);
  1056. ret = wait_event_timeout(fimc->irq_queue,
  1057. !test_bit(ST_FLITE_OFF, &fimc->state),
  1058. msecs_to_jiffies(200));
  1059. if (ret == 0)
  1060. v4l2_err(sd, "s_stream(0) timeout\n");
  1061. clear_bit(ST_FLITE_RUN, &fimc->state);
  1062. }
  1063. mutex_unlock(&fimc->lock);
  1064. return ret;
  1065. }
  1066. static int fimc_lite_log_status(struct v4l2_subdev *sd)
  1067. {
  1068. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1069. flite_hw_dump_regs(fimc, __func__);
  1070. return 0;
  1071. }
  1072. static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
  1073. {
  1074. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1075. struct vb2_queue *q = &fimc->vb_queue;
  1076. struct video_device *vfd = &fimc->ve.vdev;
  1077. int ret;
  1078. memset(vfd, 0, sizeof(*vfd));
  1079. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  1080. snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
  1081. fimc->index);
  1082. vfd->fops = &fimc_lite_fops;
  1083. vfd->ioctl_ops = &fimc_lite_ioctl_ops;
  1084. vfd->v4l2_dev = sd->v4l2_dev;
  1085. vfd->minor = -1;
  1086. vfd->release = video_device_release_empty;
  1087. vfd->queue = q;
  1088. fimc->reqbufs_count = 0;
  1089. INIT_LIST_HEAD(&fimc->pending_buf_q);
  1090. INIT_LIST_HEAD(&fimc->active_buf_q);
  1091. memset(q, 0, sizeof(*q));
  1092. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1093. q->io_modes = VB2_MMAP | VB2_USERPTR;
  1094. q->ops = &fimc_lite_qops;
  1095. q->mem_ops = &vb2_dma_contig_memops;
  1096. q->buf_struct_size = sizeof(struct flite_buffer);
  1097. q->drv_priv = fimc;
  1098. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1099. q->lock = &fimc->lock;
  1100. ret = vb2_queue_init(q);
  1101. if (ret < 0)
  1102. return ret;
  1103. fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1104. ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
  1105. if (ret < 0)
  1106. return ret;
  1107. video_set_drvdata(vfd, fimc);
  1108. fimc->ve.pipe = v4l2_get_subdev_hostdata(sd);
  1109. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1110. if (ret < 0) {
  1111. media_entity_cleanup(&vfd->entity);
  1112. fimc->ve.pipe = NULL;
  1113. return ret;
  1114. }
  1115. v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
  1116. vfd->name, video_device_node_name(vfd));
  1117. return 0;
  1118. }
  1119. static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
  1120. {
  1121. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1122. if (fimc == NULL)
  1123. return;
  1124. mutex_lock(&fimc->lock);
  1125. if (video_is_registered(&fimc->ve.vdev)) {
  1126. video_unregister_device(&fimc->ve.vdev);
  1127. media_entity_cleanup(&fimc->ve.vdev.entity);
  1128. fimc->ve.pipe = NULL;
  1129. }
  1130. mutex_unlock(&fimc->lock);
  1131. }
  1132. static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
  1133. .registered = fimc_lite_subdev_registered,
  1134. .unregistered = fimc_lite_subdev_unregistered,
  1135. };
  1136. static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
  1137. .enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
  1138. .get_selection = fimc_lite_subdev_get_selection,
  1139. .set_selection = fimc_lite_subdev_set_selection,
  1140. .get_fmt = fimc_lite_subdev_get_fmt,
  1141. .set_fmt = fimc_lite_subdev_set_fmt,
  1142. };
  1143. static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
  1144. .s_stream = fimc_lite_subdev_s_stream,
  1145. };
  1146. static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
  1147. .log_status = fimc_lite_log_status,
  1148. };
  1149. static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
  1150. .core = &fimc_lite_core_ops,
  1151. .video = &fimc_lite_subdev_video_ops,
  1152. .pad = &fimc_lite_subdev_pad_ops,
  1153. };
  1154. static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
  1155. {
  1156. struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
  1157. ctrl_handler);
  1158. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1159. return 0;
  1160. }
  1161. static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
  1162. .s_ctrl = fimc_lite_s_ctrl,
  1163. };
  1164. static const struct v4l2_ctrl_config fimc_lite_ctrl = {
  1165. .ops = &fimc_lite_ctrl_ops,
  1166. .id = V4L2_CTRL_CLASS_USER | 0x1001,
  1167. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1168. .name = "Test Pattern 640x480",
  1169. .step = 1,
  1170. };
  1171. static void fimc_lite_set_default_config(struct fimc_lite *fimc)
  1172. {
  1173. struct flite_frame *sink = &fimc->inp_frame;
  1174. struct flite_frame *source = &fimc->out_frame;
  1175. sink->fmt = &fimc_lite_formats[0];
  1176. sink->f_width = FLITE_DEFAULT_WIDTH;
  1177. sink->f_height = FLITE_DEFAULT_HEIGHT;
  1178. sink->rect.width = FLITE_DEFAULT_WIDTH;
  1179. sink->rect.height = FLITE_DEFAULT_HEIGHT;
  1180. sink->rect.left = 0;
  1181. sink->rect.top = 0;
  1182. *source = *sink;
  1183. }
  1184. static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
  1185. {
  1186. struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
  1187. struct v4l2_subdev *sd = &fimc->subdev;
  1188. int ret;
  1189. v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
  1190. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1191. snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
  1192. fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  1193. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE;
  1194. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE;
  1195. ret = media_entity_init(&sd->entity, FLITE_SD_PADS_NUM,
  1196. fimc->subdev_pads, 0);
  1197. if (ret)
  1198. return ret;
  1199. v4l2_ctrl_handler_init(handler, 1);
  1200. fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
  1201. NULL);
  1202. if (handler->error) {
  1203. media_entity_cleanup(&sd->entity);
  1204. return handler->error;
  1205. }
  1206. sd->ctrl_handler = handler;
  1207. sd->internal_ops = &fimc_lite_subdev_internal_ops;
  1208. sd->entity.ops = &fimc_lite_subdev_media_ops;
  1209. sd->owner = THIS_MODULE;
  1210. v4l2_set_subdevdata(sd, fimc);
  1211. return 0;
  1212. }
  1213. static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
  1214. {
  1215. struct v4l2_subdev *sd = &fimc->subdev;
  1216. v4l2_device_unregister_subdev(sd);
  1217. media_entity_cleanup(&sd->entity);
  1218. v4l2_ctrl_handler_free(&fimc->ctrl_handler);
  1219. v4l2_set_subdevdata(sd, NULL);
  1220. }
  1221. static void fimc_lite_clk_put(struct fimc_lite *fimc)
  1222. {
  1223. if (IS_ERR(fimc->clock))
  1224. return;
  1225. clk_unprepare(fimc->clock);
  1226. clk_put(fimc->clock);
  1227. fimc->clock = ERR_PTR(-EINVAL);
  1228. }
  1229. static int fimc_lite_clk_get(struct fimc_lite *fimc)
  1230. {
  1231. int ret;
  1232. fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
  1233. if (IS_ERR(fimc->clock))
  1234. return PTR_ERR(fimc->clock);
  1235. ret = clk_prepare(fimc->clock);
  1236. if (ret < 0) {
  1237. clk_put(fimc->clock);
  1238. fimc->clock = ERR_PTR(-EINVAL);
  1239. }
  1240. return ret;
  1241. }
  1242. static const struct of_device_id flite_of_match[];
  1243. static int fimc_lite_probe(struct platform_device *pdev)
  1244. {
  1245. struct flite_drvdata *drv_data = NULL;
  1246. struct device *dev = &pdev->dev;
  1247. const struct of_device_id *of_id;
  1248. struct fimc_lite *fimc;
  1249. struct resource *res;
  1250. int ret;
  1251. if (!dev->of_node)
  1252. return -ENODEV;
  1253. fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
  1254. if (!fimc)
  1255. return -ENOMEM;
  1256. of_id = of_match_node(flite_of_match, dev->of_node);
  1257. if (of_id)
  1258. drv_data = (struct flite_drvdata *)of_id->data;
  1259. fimc->index = of_alias_get_id(dev->of_node, "fimc-lite");
  1260. if (!drv_data || fimc->index >= drv_data->num_instances ||
  1261. fimc->index < 0) {
  1262. dev_err(dev, "Wrong %s node alias\n",
  1263. dev->of_node->full_name);
  1264. return -EINVAL;
  1265. }
  1266. fimc->dd = drv_data;
  1267. fimc->pdev = pdev;
  1268. init_waitqueue_head(&fimc->irq_queue);
  1269. spin_lock_init(&fimc->slock);
  1270. mutex_init(&fimc->lock);
  1271. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1272. fimc->regs = devm_ioremap_resource(dev, res);
  1273. if (IS_ERR(fimc->regs))
  1274. return PTR_ERR(fimc->regs);
  1275. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1276. if (res == NULL) {
  1277. dev_err(dev, "Failed to get IRQ resource\n");
  1278. return -ENXIO;
  1279. }
  1280. ret = fimc_lite_clk_get(fimc);
  1281. if (ret)
  1282. return ret;
  1283. ret = devm_request_irq(dev, res->start, flite_irq_handler,
  1284. 0, dev_name(dev), fimc);
  1285. if (ret) {
  1286. dev_err(dev, "Failed to install irq (%d)\n", ret);
  1287. goto err_clk_put;
  1288. }
  1289. /* The video node will be created within the subdev's registered() op */
  1290. ret = fimc_lite_create_capture_subdev(fimc);
  1291. if (ret)
  1292. goto err_clk_put;
  1293. platform_set_drvdata(pdev, fimc);
  1294. pm_runtime_enable(dev);
  1295. if (!pm_runtime_enabled(dev)) {
  1296. ret = clk_enable(fimc->clock);
  1297. if (ret < 0)
  1298. goto err_sd;
  1299. }
  1300. fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
  1301. if (IS_ERR(fimc->alloc_ctx)) {
  1302. ret = PTR_ERR(fimc->alloc_ctx);
  1303. goto err_clk_dis;
  1304. }
  1305. fimc_lite_set_default_config(fimc);
  1306. dev_dbg(dev, "FIMC-LITE.%d registered successfully\n",
  1307. fimc->index);
  1308. return 0;
  1309. err_clk_dis:
  1310. if (!pm_runtime_enabled(dev))
  1311. clk_disable(fimc->clock);
  1312. err_sd:
  1313. fimc_lite_unregister_capture_subdev(fimc);
  1314. err_clk_put:
  1315. fimc_lite_clk_put(fimc);
  1316. return ret;
  1317. }
  1318. #ifdef CONFIG_PM
  1319. static int fimc_lite_runtime_resume(struct device *dev)
  1320. {
  1321. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1322. clk_enable(fimc->clock);
  1323. return 0;
  1324. }
  1325. static int fimc_lite_runtime_suspend(struct device *dev)
  1326. {
  1327. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1328. clk_disable(fimc->clock);
  1329. return 0;
  1330. }
  1331. #endif
  1332. #ifdef CONFIG_PM_SLEEP
  1333. static int fimc_lite_resume(struct device *dev)
  1334. {
  1335. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1336. struct flite_buffer *buf;
  1337. unsigned long flags;
  1338. int i;
  1339. spin_lock_irqsave(&fimc->slock, flags);
  1340. if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
  1341. !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
  1342. spin_unlock_irqrestore(&fimc->slock, flags);
  1343. return 0;
  1344. }
  1345. flite_hw_reset(fimc);
  1346. spin_unlock_irqrestore(&fimc->slock, flags);
  1347. if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
  1348. return 0;
  1349. INIT_LIST_HEAD(&fimc->active_buf_q);
  1350. fimc_pipeline_call(&fimc->ve, open,
  1351. &fimc->ve.vdev.entity, false);
  1352. fimc_lite_hw_init(fimc, atomic_read(&fimc->out_path) == FIMC_IO_ISP);
  1353. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  1354. for (i = 0; i < fimc->reqbufs_count; i++) {
  1355. if (list_empty(&fimc->pending_buf_q))
  1356. break;
  1357. buf = fimc_lite_pending_queue_pop(fimc);
  1358. buffer_queue(&buf->vb);
  1359. }
  1360. return 0;
  1361. }
  1362. static int fimc_lite_suspend(struct device *dev)
  1363. {
  1364. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1365. bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
  1366. int ret;
  1367. if (test_and_set_bit(ST_LPM, &fimc->state))
  1368. return 0;
  1369. ret = fimc_lite_stop_capture(fimc, suspend);
  1370. if (ret < 0 || !fimc_lite_active(fimc))
  1371. return ret;
  1372. return fimc_pipeline_call(&fimc->ve, close);
  1373. }
  1374. #endif /* CONFIG_PM_SLEEP */
  1375. static int fimc_lite_remove(struct platform_device *pdev)
  1376. {
  1377. struct fimc_lite *fimc = platform_get_drvdata(pdev);
  1378. struct device *dev = &pdev->dev;
  1379. pm_runtime_disable(dev);
  1380. pm_runtime_set_suspended(dev);
  1381. fimc_lite_unregister_capture_subdev(fimc);
  1382. vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
  1383. fimc_lite_clk_put(fimc);
  1384. dev_info(dev, "Driver unloaded\n");
  1385. return 0;
  1386. }
  1387. static const struct dev_pm_ops fimc_lite_pm_ops = {
  1388. SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
  1389. SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
  1390. NULL)
  1391. };
  1392. /* EXYNOS4212, EXYNOS4412 */
  1393. static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
  1394. .max_width = 8192,
  1395. .max_height = 8192,
  1396. .out_width_align = 8,
  1397. .win_hor_offs_align = 2,
  1398. .out_hor_offs_align = 8,
  1399. .max_dma_bufs = 1,
  1400. .num_instances = 2,
  1401. };
  1402. /* EXYNOS5250 */
  1403. static struct flite_drvdata fimc_lite_drvdata_exynos5 = {
  1404. .max_width = 8192,
  1405. .max_height = 8192,
  1406. .out_width_align = 8,
  1407. .win_hor_offs_align = 2,
  1408. .out_hor_offs_align = 8,
  1409. .max_dma_bufs = 32,
  1410. .num_instances = 3,
  1411. };
  1412. static const struct of_device_id flite_of_match[] = {
  1413. {
  1414. .compatible = "samsung,exynos4212-fimc-lite",
  1415. .data = &fimc_lite_drvdata_exynos4,
  1416. },
  1417. {
  1418. .compatible = "samsung,exynos5250-fimc-lite",
  1419. .data = &fimc_lite_drvdata_exynos5,
  1420. },
  1421. { /* sentinel */ },
  1422. };
  1423. MODULE_DEVICE_TABLE(of, flite_of_match);
  1424. static struct platform_driver fimc_lite_driver = {
  1425. .probe = fimc_lite_probe,
  1426. .remove = fimc_lite_remove,
  1427. .driver = {
  1428. .of_match_table = flite_of_match,
  1429. .name = FIMC_LITE_DRV_NAME,
  1430. .pm = &fimc_lite_pm_ops,
  1431. }
  1432. };
  1433. module_platform_driver(fimc_lite_driver);
  1434. MODULE_LICENSE("GPL");
  1435. MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);