vf610_adc.c 20 KB

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  1. /*
  2. * Freescale Vybrid vf610 ADC driver
  3. *
  4. * Copyright 2013 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/delay.h>
  24. #include <linux/kernel.h>
  25. #include <linux/slab.h>
  26. #include <linux/io.h>
  27. #include <linux/clk.h>
  28. #include <linux/completion.h>
  29. #include <linux/of.h>
  30. #include <linux/of_irq.h>
  31. #include <linux/regulator/consumer.h>
  32. #include <linux/of_platform.h>
  33. #include <linux/err.h>
  34. #include <linux/iio/iio.h>
  35. #include <linux/iio/sysfs.h>
  36. #include <linux/iio/driver.h>
  37. /* This will be the driver name the kernel reports */
  38. #define DRIVER_NAME "vf610-adc"
  39. /* Vybrid/IMX ADC registers */
  40. #define VF610_REG_ADC_HC0 0x00
  41. #define VF610_REG_ADC_HC1 0x04
  42. #define VF610_REG_ADC_HS 0x08
  43. #define VF610_REG_ADC_R0 0x0c
  44. #define VF610_REG_ADC_R1 0x10
  45. #define VF610_REG_ADC_CFG 0x14
  46. #define VF610_REG_ADC_GC 0x18
  47. #define VF610_REG_ADC_GS 0x1c
  48. #define VF610_REG_ADC_CV 0x20
  49. #define VF610_REG_ADC_OFS 0x24
  50. #define VF610_REG_ADC_CAL 0x28
  51. #define VF610_REG_ADC_PCTL 0x30
  52. /* Configuration register field define */
  53. #define VF610_ADC_MODE_BIT8 0x00
  54. #define VF610_ADC_MODE_BIT10 0x04
  55. #define VF610_ADC_MODE_BIT12 0x08
  56. #define VF610_ADC_MODE_MASK 0x0c
  57. #define VF610_ADC_BUSCLK2_SEL 0x01
  58. #define VF610_ADC_ALTCLK_SEL 0x02
  59. #define VF610_ADC_ADACK_SEL 0x03
  60. #define VF610_ADC_ADCCLK_MASK 0x03
  61. #define VF610_ADC_CLK_DIV2 0x20
  62. #define VF610_ADC_CLK_DIV4 0x40
  63. #define VF610_ADC_CLK_DIV8 0x60
  64. #define VF610_ADC_CLK_MASK 0x60
  65. #define VF610_ADC_ADLSMP_LONG 0x10
  66. #define VF610_ADC_ADSTS_MASK 0x300
  67. #define VF610_ADC_ADLPC_EN 0x80
  68. #define VF610_ADC_ADHSC_EN 0x400
  69. #define VF610_ADC_REFSEL_VALT 0x100
  70. #define VF610_ADC_REFSEL_VBG 0x1000
  71. #define VF610_ADC_ADTRG_HARD 0x2000
  72. #define VF610_ADC_AVGS_8 0x4000
  73. #define VF610_ADC_AVGS_16 0x8000
  74. #define VF610_ADC_AVGS_32 0xC000
  75. #define VF610_ADC_AVGS_MASK 0xC000
  76. #define VF610_ADC_OVWREN 0x10000
  77. /* General control register field define */
  78. #define VF610_ADC_ADACKEN 0x1
  79. #define VF610_ADC_DMAEN 0x2
  80. #define VF610_ADC_ACREN 0x4
  81. #define VF610_ADC_ACFGT 0x8
  82. #define VF610_ADC_ACFE 0x10
  83. #define VF610_ADC_AVGEN 0x20
  84. #define VF610_ADC_ADCON 0x40
  85. #define VF610_ADC_CAL 0x80
  86. /* Other field define */
  87. #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
  88. #define VF610_ADC_AIEN (0x1 << 7)
  89. #define VF610_ADC_CONV_DISABLE 0x1F
  90. #define VF610_ADC_HS_COCO0 0x1
  91. #define VF610_ADC_CALF 0x2
  92. #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
  93. enum clk_sel {
  94. VF610_ADCIOC_BUSCLK_SET,
  95. VF610_ADCIOC_ALTCLK_SET,
  96. VF610_ADCIOC_ADACK_SET,
  97. };
  98. enum vol_ref {
  99. VF610_ADCIOC_VR_VREF_SET,
  100. VF610_ADCIOC_VR_VALT_SET,
  101. VF610_ADCIOC_VR_VBG_SET,
  102. };
  103. enum average_sel {
  104. VF610_ADC_SAMPLE_1,
  105. VF610_ADC_SAMPLE_4,
  106. VF610_ADC_SAMPLE_8,
  107. VF610_ADC_SAMPLE_16,
  108. VF610_ADC_SAMPLE_32,
  109. };
  110. enum conversion_mode_sel {
  111. VF610_ADC_CONV_NORMAL,
  112. VF610_ADC_CONV_HIGH_SPEED,
  113. VF610_ADC_CONV_LOW_POWER,
  114. };
  115. struct vf610_adc_feature {
  116. enum clk_sel clk_sel;
  117. enum vol_ref vol_ref;
  118. enum conversion_mode_sel conv_mode;
  119. int clk_div;
  120. int sample_rate;
  121. int res_mode;
  122. bool calibration;
  123. bool ovwren;
  124. };
  125. struct vf610_adc {
  126. struct device *dev;
  127. void __iomem *regs;
  128. struct clk *clk;
  129. u32 vref_uv;
  130. u32 value;
  131. struct regulator *vref;
  132. u32 max_adck_rate[3];
  133. struct vf610_adc_feature adc_feature;
  134. u32 sample_freq_avail[5];
  135. struct completion completion;
  136. };
  137. static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
  138. static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
  139. {
  140. struct vf610_adc_feature *adc_feature = &info->adc_feature;
  141. unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
  142. int divisor, i;
  143. adck_rate = info->max_adck_rate[adc_feature->conv_mode];
  144. if (adck_rate) {
  145. /* calculate clk divider which is within specification */
  146. divisor = ipg_rate / adck_rate;
  147. adc_feature->clk_div = 1 << fls(divisor + 1);
  148. } else {
  149. /* fall-back value using a safe divisor */
  150. adc_feature->clk_div = 8;
  151. }
  152. /*
  153. * Calculate ADC sample frequencies
  154. * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
  155. * which is the same as bus clock.
  156. *
  157. * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
  158. * SFCAdder: fixed to 6 ADCK cycles
  159. * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
  160. * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
  161. * LSTAdder(Long Sample Time): fixed to 3 ADCK cycles
  162. */
  163. adck_rate = ipg_rate / info->adc_feature.clk_div;
  164. for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
  165. info->sample_freq_avail[i] =
  166. adck_rate / (6 + vf610_hw_avgs[i] * (25 + 3));
  167. }
  168. static inline void vf610_adc_cfg_init(struct vf610_adc *info)
  169. {
  170. struct vf610_adc_feature *adc_feature = &info->adc_feature;
  171. /* set default Configuration for ADC controller */
  172. adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
  173. adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
  174. adc_feature->calibration = true;
  175. adc_feature->ovwren = true;
  176. adc_feature->res_mode = 12;
  177. adc_feature->sample_rate = 1;
  178. adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
  179. vf610_adc_calculate_rates(info);
  180. }
  181. static void vf610_adc_cfg_post_set(struct vf610_adc *info)
  182. {
  183. struct vf610_adc_feature *adc_feature = &info->adc_feature;
  184. int cfg_data = 0;
  185. int gc_data = 0;
  186. switch (adc_feature->clk_sel) {
  187. case VF610_ADCIOC_ALTCLK_SET:
  188. cfg_data |= VF610_ADC_ALTCLK_SEL;
  189. break;
  190. case VF610_ADCIOC_ADACK_SET:
  191. cfg_data |= VF610_ADC_ADACK_SEL;
  192. break;
  193. default:
  194. break;
  195. }
  196. /* low power set for calibration */
  197. cfg_data |= VF610_ADC_ADLPC_EN;
  198. /* enable high speed for calibration */
  199. cfg_data |= VF610_ADC_ADHSC_EN;
  200. /* voltage reference */
  201. switch (adc_feature->vol_ref) {
  202. case VF610_ADCIOC_VR_VREF_SET:
  203. break;
  204. case VF610_ADCIOC_VR_VALT_SET:
  205. cfg_data |= VF610_ADC_REFSEL_VALT;
  206. break;
  207. case VF610_ADCIOC_VR_VBG_SET:
  208. cfg_data |= VF610_ADC_REFSEL_VBG;
  209. break;
  210. default:
  211. dev_err(info->dev, "error voltage reference\n");
  212. }
  213. /* data overwrite enable */
  214. if (adc_feature->ovwren)
  215. cfg_data |= VF610_ADC_OVWREN;
  216. writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
  217. writel(gc_data, info->regs + VF610_REG_ADC_GC);
  218. }
  219. static void vf610_adc_calibration(struct vf610_adc *info)
  220. {
  221. int adc_gc, hc_cfg;
  222. if (!info->adc_feature.calibration)
  223. return;
  224. /* enable calibration interrupt */
  225. hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
  226. writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
  227. adc_gc = readl(info->regs + VF610_REG_ADC_GC);
  228. writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
  229. if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
  230. dev_err(info->dev, "Timeout for adc calibration\n");
  231. adc_gc = readl(info->regs + VF610_REG_ADC_GS);
  232. if (adc_gc & VF610_ADC_CALF)
  233. dev_err(info->dev, "ADC calibration failed\n");
  234. info->adc_feature.calibration = false;
  235. }
  236. static void vf610_adc_cfg_set(struct vf610_adc *info)
  237. {
  238. struct vf610_adc_feature *adc_feature = &(info->adc_feature);
  239. int cfg_data;
  240. cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
  241. cfg_data &= ~VF610_ADC_ADLPC_EN;
  242. if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
  243. cfg_data |= VF610_ADC_ADLPC_EN;
  244. cfg_data &= ~VF610_ADC_ADHSC_EN;
  245. if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
  246. cfg_data |= VF610_ADC_ADHSC_EN;
  247. writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
  248. }
  249. static void vf610_adc_sample_set(struct vf610_adc *info)
  250. {
  251. struct vf610_adc_feature *adc_feature = &(info->adc_feature);
  252. int cfg_data, gc_data;
  253. cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
  254. gc_data = readl(info->regs + VF610_REG_ADC_GC);
  255. /* resolution mode */
  256. cfg_data &= ~VF610_ADC_MODE_MASK;
  257. switch (adc_feature->res_mode) {
  258. case 8:
  259. cfg_data |= VF610_ADC_MODE_BIT8;
  260. break;
  261. case 10:
  262. cfg_data |= VF610_ADC_MODE_BIT10;
  263. break;
  264. case 12:
  265. cfg_data |= VF610_ADC_MODE_BIT12;
  266. break;
  267. default:
  268. dev_err(info->dev, "error resolution mode\n");
  269. break;
  270. }
  271. /* clock select and clock divider */
  272. cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
  273. switch (adc_feature->clk_div) {
  274. case 1:
  275. break;
  276. case 2:
  277. cfg_data |= VF610_ADC_CLK_DIV2;
  278. break;
  279. case 4:
  280. cfg_data |= VF610_ADC_CLK_DIV4;
  281. break;
  282. case 8:
  283. cfg_data |= VF610_ADC_CLK_DIV8;
  284. break;
  285. case 16:
  286. switch (adc_feature->clk_sel) {
  287. case VF610_ADCIOC_BUSCLK_SET:
  288. cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
  289. break;
  290. default:
  291. dev_err(info->dev, "error clk divider\n");
  292. break;
  293. }
  294. break;
  295. }
  296. /* Use the short sample mode */
  297. cfg_data &= ~(VF610_ADC_ADLSMP_LONG | VF610_ADC_ADSTS_MASK);
  298. /* update hardware average selection */
  299. cfg_data &= ~VF610_ADC_AVGS_MASK;
  300. gc_data &= ~VF610_ADC_AVGEN;
  301. switch (adc_feature->sample_rate) {
  302. case VF610_ADC_SAMPLE_1:
  303. break;
  304. case VF610_ADC_SAMPLE_4:
  305. gc_data |= VF610_ADC_AVGEN;
  306. break;
  307. case VF610_ADC_SAMPLE_8:
  308. gc_data |= VF610_ADC_AVGEN;
  309. cfg_data |= VF610_ADC_AVGS_8;
  310. break;
  311. case VF610_ADC_SAMPLE_16:
  312. gc_data |= VF610_ADC_AVGEN;
  313. cfg_data |= VF610_ADC_AVGS_16;
  314. break;
  315. case VF610_ADC_SAMPLE_32:
  316. gc_data |= VF610_ADC_AVGEN;
  317. cfg_data |= VF610_ADC_AVGS_32;
  318. break;
  319. default:
  320. dev_err(info->dev,
  321. "error hardware sample average select\n");
  322. }
  323. writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
  324. writel(gc_data, info->regs + VF610_REG_ADC_GC);
  325. }
  326. static void vf610_adc_hw_init(struct vf610_adc *info)
  327. {
  328. /* CFG: Feature set */
  329. vf610_adc_cfg_post_set(info);
  330. vf610_adc_sample_set(info);
  331. /* adc calibration */
  332. vf610_adc_calibration(info);
  333. /* CFG: power and speed set */
  334. vf610_adc_cfg_set(info);
  335. }
  336. static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
  337. const struct iio_chan_spec *chan,
  338. unsigned int mode)
  339. {
  340. struct vf610_adc *info = iio_priv(indio_dev);
  341. mutex_lock(&indio_dev->mlock);
  342. info->adc_feature.conv_mode = mode;
  343. vf610_adc_calculate_rates(info);
  344. vf610_adc_hw_init(info);
  345. mutex_unlock(&indio_dev->mlock);
  346. return 0;
  347. }
  348. static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
  349. const struct iio_chan_spec *chan)
  350. {
  351. struct vf610_adc *info = iio_priv(indio_dev);
  352. return info->adc_feature.conv_mode;
  353. }
  354. static const char * const vf610_conv_modes[] = { "normal", "high-speed",
  355. "low-power" };
  356. static const struct iio_enum vf610_conversion_mode = {
  357. .items = vf610_conv_modes,
  358. .num_items = ARRAY_SIZE(vf610_conv_modes),
  359. .get = vf610_get_conversion_mode,
  360. .set = vf610_set_conversion_mode,
  361. };
  362. static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
  363. IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
  364. {},
  365. };
  366. #define VF610_ADC_CHAN(_idx, _chan_type) { \
  367. .type = (_chan_type), \
  368. .indexed = 1, \
  369. .channel = (_idx), \
  370. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  371. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  372. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  373. .ext_info = vf610_ext_info, \
  374. }
  375. #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
  376. .type = (_chan_type), \
  377. .channel = (_idx), \
  378. .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
  379. }
  380. static const struct iio_chan_spec vf610_adc_iio_channels[] = {
  381. VF610_ADC_CHAN(0, IIO_VOLTAGE),
  382. VF610_ADC_CHAN(1, IIO_VOLTAGE),
  383. VF610_ADC_CHAN(2, IIO_VOLTAGE),
  384. VF610_ADC_CHAN(3, IIO_VOLTAGE),
  385. VF610_ADC_CHAN(4, IIO_VOLTAGE),
  386. VF610_ADC_CHAN(5, IIO_VOLTAGE),
  387. VF610_ADC_CHAN(6, IIO_VOLTAGE),
  388. VF610_ADC_CHAN(7, IIO_VOLTAGE),
  389. VF610_ADC_CHAN(8, IIO_VOLTAGE),
  390. VF610_ADC_CHAN(9, IIO_VOLTAGE),
  391. VF610_ADC_CHAN(10, IIO_VOLTAGE),
  392. VF610_ADC_CHAN(11, IIO_VOLTAGE),
  393. VF610_ADC_CHAN(12, IIO_VOLTAGE),
  394. VF610_ADC_CHAN(13, IIO_VOLTAGE),
  395. VF610_ADC_CHAN(14, IIO_VOLTAGE),
  396. VF610_ADC_CHAN(15, IIO_VOLTAGE),
  397. VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
  398. /* sentinel */
  399. };
  400. static int vf610_adc_read_data(struct vf610_adc *info)
  401. {
  402. int result;
  403. result = readl(info->regs + VF610_REG_ADC_R0);
  404. switch (info->adc_feature.res_mode) {
  405. case 8:
  406. result &= 0xFF;
  407. break;
  408. case 10:
  409. result &= 0x3FF;
  410. break;
  411. case 12:
  412. result &= 0xFFF;
  413. break;
  414. default:
  415. break;
  416. }
  417. return result;
  418. }
  419. static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
  420. {
  421. struct vf610_adc *info = (struct vf610_adc *)dev_id;
  422. int coco;
  423. coco = readl(info->regs + VF610_REG_ADC_HS);
  424. if (coco & VF610_ADC_HS_COCO0) {
  425. info->value = vf610_adc_read_data(info);
  426. complete(&info->completion);
  427. }
  428. return IRQ_HANDLED;
  429. }
  430. static ssize_t vf610_show_samp_freq_avail(struct device *dev,
  431. struct device_attribute *attr, char *buf)
  432. {
  433. struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
  434. size_t len = 0;
  435. int i;
  436. for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
  437. len += scnprintf(buf + len, PAGE_SIZE - len,
  438. "%u ", info->sample_freq_avail[i]);
  439. /* replace trailing space by newline */
  440. buf[len - 1] = '\n';
  441. return len;
  442. }
  443. static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
  444. static struct attribute *vf610_attributes[] = {
  445. &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
  446. NULL
  447. };
  448. static const struct attribute_group vf610_attribute_group = {
  449. .attrs = vf610_attributes,
  450. };
  451. static int vf610_read_raw(struct iio_dev *indio_dev,
  452. struct iio_chan_spec const *chan,
  453. int *val,
  454. int *val2,
  455. long mask)
  456. {
  457. struct vf610_adc *info = iio_priv(indio_dev);
  458. unsigned int hc_cfg;
  459. long ret;
  460. switch (mask) {
  461. case IIO_CHAN_INFO_RAW:
  462. case IIO_CHAN_INFO_PROCESSED:
  463. mutex_lock(&indio_dev->mlock);
  464. reinit_completion(&info->completion);
  465. hc_cfg = VF610_ADC_ADCHC(chan->channel);
  466. hc_cfg |= VF610_ADC_AIEN;
  467. writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
  468. ret = wait_for_completion_interruptible_timeout
  469. (&info->completion, VF610_ADC_TIMEOUT);
  470. if (ret == 0) {
  471. mutex_unlock(&indio_dev->mlock);
  472. return -ETIMEDOUT;
  473. }
  474. if (ret < 0) {
  475. mutex_unlock(&indio_dev->mlock);
  476. return ret;
  477. }
  478. switch (chan->type) {
  479. case IIO_VOLTAGE:
  480. *val = info->value;
  481. break;
  482. case IIO_TEMP:
  483. /*
  484. * Calculate in degree Celsius times 1000
  485. * Using sensor slope of 1.84 mV/°C and
  486. * V at 25°C of 696 mV
  487. */
  488. *val = 25000 - ((int)info->value - 864) * 1000000 / 1840;
  489. break;
  490. default:
  491. mutex_unlock(&indio_dev->mlock);
  492. return -EINVAL;
  493. }
  494. mutex_unlock(&indio_dev->mlock);
  495. return IIO_VAL_INT;
  496. case IIO_CHAN_INFO_SCALE:
  497. *val = info->vref_uv / 1000;
  498. *val2 = info->adc_feature.res_mode;
  499. return IIO_VAL_FRACTIONAL_LOG2;
  500. case IIO_CHAN_INFO_SAMP_FREQ:
  501. *val = info->sample_freq_avail[info->adc_feature.sample_rate];
  502. *val2 = 0;
  503. return IIO_VAL_INT;
  504. default:
  505. break;
  506. }
  507. return -EINVAL;
  508. }
  509. static int vf610_write_raw(struct iio_dev *indio_dev,
  510. struct iio_chan_spec const *chan,
  511. int val,
  512. int val2,
  513. long mask)
  514. {
  515. struct vf610_adc *info = iio_priv(indio_dev);
  516. int i;
  517. switch (mask) {
  518. case IIO_CHAN_INFO_SAMP_FREQ:
  519. for (i = 0;
  520. i < ARRAY_SIZE(info->sample_freq_avail);
  521. i++)
  522. if (val == info->sample_freq_avail[i]) {
  523. info->adc_feature.sample_rate = i;
  524. vf610_adc_sample_set(info);
  525. return 0;
  526. }
  527. break;
  528. default:
  529. break;
  530. }
  531. return -EINVAL;
  532. }
  533. static int vf610_adc_reg_access(struct iio_dev *indio_dev,
  534. unsigned reg, unsigned writeval,
  535. unsigned *readval)
  536. {
  537. struct vf610_adc *info = iio_priv(indio_dev);
  538. if ((readval == NULL) ||
  539. (!(reg % 4) || (reg > VF610_REG_ADC_PCTL)))
  540. return -EINVAL;
  541. *readval = readl(info->regs + reg);
  542. return 0;
  543. }
  544. static const struct iio_info vf610_adc_iio_info = {
  545. .driver_module = THIS_MODULE,
  546. .read_raw = &vf610_read_raw,
  547. .write_raw = &vf610_write_raw,
  548. .debugfs_reg_access = &vf610_adc_reg_access,
  549. .attrs = &vf610_attribute_group,
  550. };
  551. static const struct of_device_id vf610_adc_match[] = {
  552. { .compatible = "fsl,vf610-adc", },
  553. { /* sentinel */ }
  554. };
  555. MODULE_DEVICE_TABLE(of, vf610_adc_match);
  556. static int vf610_adc_probe(struct platform_device *pdev)
  557. {
  558. struct vf610_adc *info;
  559. struct iio_dev *indio_dev;
  560. struct resource *mem;
  561. int irq;
  562. int ret;
  563. indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
  564. if (!indio_dev) {
  565. dev_err(&pdev->dev, "Failed allocating iio device\n");
  566. return -ENOMEM;
  567. }
  568. info = iio_priv(indio_dev);
  569. info->dev = &pdev->dev;
  570. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  571. info->regs = devm_ioremap_resource(&pdev->dev, mem);
  572. if (IS_ERR(info->regs))
  573. return PTR_ERR(info->regs);
  574. irq = platform_get_irq(pdev, 0);
  575. if (irq < 0) {
  576. dev_err(&pdev->dev, "no irq resource?\n");
  577. return irq;
  578. }
  579. ret = devm_request_irq(info->dev, irq,
  580. vf610_adc_isr, 0,
  581. dev_name(&pdev->dev), info);
  582. if (ret < 0) {
  583. dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
  584. return ret;
  585. }
  586. info->clk = devm_clk_get(&pdev->dev, "adc");
  587. if (IS_ERR(info->clk)) {
  588. dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
  589. PTR_ERR(info->clk));
  590. return PTR_ERR(info->clk);
  591. }
  592. info->vref = devm_regulator_get(&pdev->dev, "vref");
  593. if (IS_ERR(info->vref))
  594. return PTR_ERR(info->vref);
  595. ret = regulator_enable(info->vref);
  596. if (ret)
  597. return ret;
  598. info->vref_uv = regulator_get_voltage(info->vref);
  599. of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
  600. info->max_adck_rate, 3);
  601. platform_set_drvdata(pdev, indio_dev);
  602. init_completion(&info->completion);
  603. indio_dev->name = dev_name(&pdev->dev);
  604. indio_dev->dev.parent = &pdev->dev;
  605. indio_dev->dev.of_node = pdev->dev.of_node;
  606. indio_dev->info = &vf610_adc_iio_info;
  607. indio_dev->modes = INDIO_DIRECT_MODE;
  608. indio_dev->channels = vf610_adc_iio_channels;
  609. indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
  610. ret = clk_prepare_enable(info->clk);
  611. if (ret) {
  612. dev_err(&pdev->dev,
  613. "Could not prepare or enable the clock.\n");
  614. goto error_adc_clk_enable;
  615. }
  616. vf610_adc_cfg_init(info);
  617. vf610_adc_hw_init(info);
  618. ret = iio_device_register(indio_dev);
  619. if (ret) {
  620. dev_err(&pdev->dev, "Couldn't register the device.\n");
  621. goto error_iio_device_register;
  622. }
  623. return 0;
  624. error_iio_device_register:
  625. clk_disable_unprepare(info->clk);
  626. error_adc_clk_enable:
  627. regulator_disable(info->vref);
  628. return ret;
  629. }
  630. static int vf610_adc_remove(struct platform_device *pdev)
  631. {
  632. struct iio_dev *indio_dev = platform_get_drvdata(pdev);
  633. struct vf610_adc *info = iio_priv(indio_dev);
  634. iio_device_unregister(indio_dev);
  635. regulator_disable(info->vref);
  636. clk_disable_unprepare(info->clk);
  637. return 0;
  638. }
  639. #ifdef CONFIG_PM_SLEEP
  640. static int vf610_adc_suspend(struct device *dev)
  641. {
  642. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  643. struct vf610_adc *info = iio_priv(indio_dev);
  644. int hc_cfg;
  645. /* ADC controller enters to stop mode */
  646. hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
  647. hc_cfg |= VF610_ADC_CONV_DISABLE;
  648. writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
  649. clk_disable_unprepare(info->clk);
  650. regulator_disable(info->vref);
  651. return 0;
  652. }
  653. static int vf610_adc_resume(struct device *dev)
  654. {
  655. struct iio_dev *indio_dev = dev_get_drvdata(dev);
  656. struct vf610_adc *info = iio_priv(indio_dev);
  657. int ret;
  658. ret = regulator_enable(info->vref);
  659. if (ret)
  660. return ret;
  661. ret = clk_prepare_enable(info->clk);
  662. if (ret)
  663. goto disable_reg;
  664. vf610_adc_hw_init(info);
  665. return 0;
  666. disable_reg:
  667. regulator_disable(info->vref);
  668. return ret;
  669. }
  670. #endif
  671. static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
  672. static struct platform_driver vf610_adc_driver = {
  673. .probe = vf610_adc_probe,
  674. .remove = vf610_adc_remove,
  675. .driver = {
  676. .name = DRIVER_NAME,
  677. .of_match_table = vf610_adc_match,
  678. .pm = &vf610_adc_pm_ops,
  679. },
  680. };
  681. module_platform_driver(vf610_adc_driver);
  682. MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
  683. MODULE_DESCRIPTION("Freescale VF610 ADC driver");
  684. MODULE_LICENSE("GPL v2");