kxcjk-1013.c 34 KB

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  1. /*
  2. * KXCJK-1013 3-axis accelerometer driver
  3. * Copyright (c) 2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/i2c.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/delay.h>
  18. #include <linux/bitops.h>
  19. #include <linux/slab.h>
  20. #include <linux/string.h>
  21. #include <linux/acpi.h>
  22. #include <linux/gpio/consumer.h>
  23. #include <linux/pm.h>
  24. #include <linux/pm_runtime.h>
  25. #include <linux/iio/iio.h>
  26. #include <linux/iio/sysfs.h>
  27. #include <linux/iio/buffer.h>
  28. #include <linux/iio/trigger.h>
  29. #include <linux/iio/events.h>
  30. #include <linux/iio/trigger_consumer.h>
  31. #include <linux/iio/triggered_buffer.h>
  32. #include <linux/iio/accel/kxcjk_1013.h>
  33. #define KXCJK1013_DRV_NAME "kxcjk1013"
  34. #define KXCJK1013_IRQ_NAME "kxcjk1013_event"
  35. #define KXCJK1013_REG_XOUT_L 0x06
  36. /*
  37. * From low byte X axis register, all the other addresses of Y and Z can be
  38. * obtained by just applying axis offset. The following axis defines are just
  39. * provide clarity, but not used.
  40. */
  41. #define KXCJK1013_REG_XOUT_H 0x07
  42. #define KXCJK1013_REG_YOUT_L 0x08
  43. #define KXCJK1013_REG_YOUT_H 0x09
  44. #define KXCJK1013_REG_ZOUT_L 0x0A
  45. #define KXCJK1013_REG_ZOUT_H 0x0B
  46. #define KXCJK1013_REG_DCST_RESP 0x0C
  47. #define KXCJK1013_REG_WHO_AM_I 0x0F
  48. #define KXCJK1013_REG_INT_SRC1 0x16
  49. #define KXCJK1013_REG_INT_SRC2 0x17
  50. #define KXCJK1013_REG_STATUS_REG 0x18
  51. #define KXCJK1013_REG_INT_REL 0x1A
  52. #define KXCJK1013_REG_CTRL1 0x1B
  53. #define KXCJK1013_REG_CTRL2 0x1D
  54. #define KXCJK1013_REG_INT_CTRL1 0x1E
  55. #define KXCJK1013_REG_INT_CTRL2 0x1F
  56. #define KXCJK1013_REG_DATA_CTRL 0x21
  57. #define KXCJK1013_REG_WAKE_TIMER 0x29
  58. #define KXCJK1013_REG_SELF_TEST 0x3A
  59. #define KXCJK1013_REG_WAKE_THRES 0x6A
  60. #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
  61. #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6)
  62. #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5)
  63. #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
  64. #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
  65. #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
  66. #define KXCJK1013_REG_INT_REG1_BIT_IEA BIT(4)
  67. #define KXCJK1013_REG_INT_REG1_BIT_IEN BIT(5)
  68. #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
  69. #define KXCJK1013_MAX_STARTUP_TIME_US 100000
  70. #define KXCJK1013_SLEEP_DELAY_MS 2000
  71. #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
  72. #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
  73. #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
  74. #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3)
  75. #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4)
  76. #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5)
  77. #define KXCJK1013_DEFAULT_WAKE_THRES 1
  78. enum kx_chipset {
  79. KXCJK1013,
  80. KXCJ91008,
  81. KXTJ21009,
  82. KX_MAX_CHIPS /* this must be last */
  83. };
  84. struct kxcjk1013_data {
  85. struct i2c_client *client;
  86. struct iio_trigger *dready_trig;
  87. struct iio_trigger *motion_trig;
  88. struct mutex mutex;
  89. s16 buffer[8];
  90. u8 odr_bits;
  91. u8 range;
  92. int wake_thres;
  93. int wake_dur;
  94. bool active_high_intr;
  95. bool dready_trigger_on;
  96. int ev_enable_state;
  97. bool motion_trigger_on;
  98. int64_t timestamp;
  99. enum kx_chipset chipset;
  100. bool is_smo8500_device;
  101. };
  102. enum kxcjk1013_axis {
  103. AXIS_X,
  104. AXIS_Y,
  105. AXIS_Z,
  106. };
  107. enum kxcjk1013_mode {
  108. STANDBY,
  109. OPERATION,
  110. };
  111. enum kxcjk1013_range {
  112. KXCJK1013_RANGE_2G,
  113. KXCJK1013_RANGE_4G,
  114. KXCJK1013_RANGE_8G,
  115. };
  116. static const struct {
  117. int val;
  118. int val2;
  119. int odr_bits;
  120. } samp_freq_table[] = { {0, 781000, 0x08}, {1, 563000, 0x09},
  121. {3, 125000, 0x0A}, {6, 250000, 0x0B}, {12, 500000, 0},
  122. {25, 0, 0x01}, {50, 0, 0x02}, {100, 0, 0x03},
  123. {200, 0, 0x04}, {400, 0, 0x05}, {800, 0, 0x06},
  124. {1600, 0, 0x07} };
  125. /* Refer to section 4 of the specification */
  126. static const struct {
  127. int odr_bits;
  128. int usec;
  129. } odr_start_up_times[KX_MAX_CHIPS][12] = {
  130. /* KXCJK-1013 */
  131. {
  132. {0x08, 100000},
  133. {0x09, 100000},
  134. {0x0A, 100000},
  135. {0x0B, 100000},
  136. {0, 80000},
  137. {0x01, 41000},
  138. {0x02, 21000},
  139. {0x03, 11000},
  140. {0x04, 6400},
  141. {0x05, 3900},
  142. {0x06, 2700},
  143. {0x07, 2100},
  144. },
  145. /* KXCJ9-1008 */
  146. {
  147. {0x08, 100000},
  148. {0x09, 100000},
  149. {0x0A, 100000},
  150. {0x0B, 100000},
  151. {0, 80000},
  152. {0x01, 41000},
  153. {0x02, 21000},
  154. {0x03, 11000},
  155. {0x04, 6400},
  156. {0x05, 3900},
  157. {0x06, 2700},
  158. {0x07, 2100},
  159. },
  160. /* KXCTJ2-1009 */
  161. {
  162. {0x08, 1240000},
  163. {0x09, 621000},
  164. {0x0A, 309000},
  165. {0x0B, 151000},
  166. {0, 80000},
  167. {0x01, 41000},
  168. {0x02, 21000},
  169. {0x03, 11000},
  170. {0x04, 6000},
  171. {0x05, 4000},
  172. {0x06, 3000},
  173. {0x07, 2000},
  174. },
  175. };
  176. static const struct {
  177. u16 scale;
  178. u8 gsel_0;
  179. u8 gsel_1;
  180. } KXCJK1013_scale_table[] = { {9582, 0, 0},
  181. {19163, 1, 0},
  182. {38326, 0, 1} };
  183. static const struct {
  184. int val;
  185. int val2;
  186. int odr_bits;
  187. } wake_odr_data_rate_table[] = { {0, 781000, 0x00},
  188. {1, 563000, 0x01},
  189. {3, 125000, 0x02},
  190. {6, 250000, 0x03},
  191. {12, 500000, 0x04},
  192. {25, 0, 0x05},
  193. {50, 0, 0x06},
  194. {100, 0, 0x06},
  195. {200, 0, 0x06},
  196. {400, 0, 0x06},
  197. {800, 0, 0x06},
  198. {1600, 0, 0x06} };
  199. static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
  200. enum kxcjk1013_mode mode)
  201. {
  202. int ret;
  203. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  204. if (ret < 0) {
  205. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  206. return ret;
  207. }
  208. if (mode == STANDBY)
  209. ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1;
  210. else
  211. ret |= KXCJK1013_REG_CTRL1_BIT_PC1;
  212. ret = i2c_smbus_write_byte_data(data->client,
  213. KXCJK1013_REG_CTRL1, ret);
  214. if (ret < 0) {
  215. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  216. return ret;
  217. }
  218. return 0;
  219. }
  220. static int kxcjk1013_get_mode(struct kxcjk1013_data *data,
  221. enum kxcjk1013_mode *mode)
  222. {
  223. int ret;
  224. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  225. if (ret < 0) {
  226. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  227. return ret;
  228. }
  229. if (ret & KXCJK1013_REG_CTRL1_BIT_PC1)
  230. *mode = OPERATION;
  231. else
  232. *mode = STANDBY;
  233. return 0;
  234. }
  235. static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
  236. {
  237. int ret;
  238. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  239. if (ret < 0) {
  240. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  241. return ret;
  242. }
  243. ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 |
  244. KXCJK1013_REG_CTRL1_BIT_GSEL1);
  245. ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
  246. ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
  247. ret = i2c_smbus_write_byte_data(data->client,
  248. KXCJK1013_REG_CTRL1,
  249. ret);
  250. if (ret < 0) {
  251. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  252. return ret;
  253. }
  254. data->range = range_index;
  255. return 0;
  256. }
  257. static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
  258. {
  259. int ret;
  260. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
  261. if (ret < 0) {
  262. dev_err(&data->client->dev, "Error reading who_am_i\n");
  263. return ret;
  264. }
  265. dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret);
  266. ret = kxcjk1013_set_mode(data, STANDBY);
  267. if (ret < 0)
  268. return ret;
  269. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  270. if (ret < 0) {
  271. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  272. return ret;
  273. }
  274. /* Set 12 bit mode */
  275. ret |= KXCJK1013_REG_CTRL1_BIT_RES;
  276. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL1,
  277. ret);
  278. if (ret < 0) {
  279. dev_err(&data->client->dev, "Error reading reg_ctrl\n");
  280. return ret;
  281. }
  282. /* Setting range to 4G */
  283. ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);
  284. if (ret < 0)
  285. return ret;
  286. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_DATA_CTRL);
  287. if (ret < 0) {
  288. dev_err(&data->client->dev, "Error reading reg_data_ctrl\n");
  289. return ret;
  290. }
  291. data->odr_bits = ret;
  292. /* Set up INT polarity */
  293. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
  294. if (ret < 0) {
  295. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  296. return ret;
  297. }
  298. if (data->active_high_intr)
  299. ret |= KXCJK1013_REG_INT_REG1_BIT_IEA;
  300. else
  301. ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEA;
  302. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
  303. ret);
  304. if (ret < 0) {
  305. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  306. return ret;
  307. }
  308. ret = kxcjk1013_set_mode(data, OPERATION);
  309. if (ret < 0)
  310. return ret;
  311. data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;
  312. return 0;
  313. }
  314. #ifdef CONFIG_PM
  315. static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data)
  316. {
  317. int i;
  318. int idx = data->chipset;
  319. for (i = 0; i < ARRAY_SIZE(odr_start_up_times[idx]); ++i) {
  320. if (odr_start_up_times[idx][i].odr_bits == data->odr_bits)
  321. return odr_start_up_times[idx][i].usec;
  322. }
  323. return KXCJK1013_MAX_STARTUP_TIME_US;
  324. }
  325. #endif
  326. static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
  327. {
  328. #ifdef CONFIG_PM
  329. int ret;
  330. if (on)
  331. ret = pm_runtime_get_sync(&data->client->dev);
  332. else {
  333. pm_runtime_mark_last_busy(&data->client->dev);
  334. ret = pm_runtime_put_autosuspend(&data->client->dev);
  335. }
  336. if (ret < 0) {
  337. dev_err(&data->client->dev,
  338. "Failed: kxcjk1013_set_power_state for %d\n", on);
  339. if (on)
  340. pm_runtime_put_noidle(&data->client->dev);
  341. return ret;
  342. }
  343. #endif
  344. return 0;
  345. }
  346. static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
  347. {
  348. int ret;
  349. ret = i2c_smbus_write_byte_data(data->client,
  350. KXCJK1013_REG_WAKE_TIMER,
  351. data->wake_dur);
  352. if (ret < 0) {
  353. dev_err(&data->client->dev,
  354. "Error writing reg_wake_timer\n");
  355. return ret;
  356. }
  357. ret = i2c_smbus_write_byte_data(data->client,
  358. KXCJK1013_REG_WAKE_THRES,
  359. data->wake_thres);
  360. if (ret < 0) {
  361. dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
  362. return ret;
  363. }
  364. return 0;
  365. }
  366. static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data,
  367. bool status)
  368. {
  369. int ret;
  370. enum kxcjk1013_mode store_mode;
  371. ret = kxcjk1013_get_mode(data, &store_mode);
  372. if (ret < 0)
  373. return ret;
  374. /* This is requirement by spec to change state to STANDBY */
  375. ret = kxcjk1013_set_mode(data, STANDBY);
  376. if (ret < 0)
  377. return ret;
  378. ret = kxcjk1013_chip_update_thresholds(data);
  379. if (ret < 0)
  380. return ret;
  381. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
  382. if (ret < 0) {
  383. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  384. return ret;
  385. }
  386. if (status)
  387. ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
  388. else
  389. ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
  390. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
  391. ret);
  392. if (ret < 0) {
  393. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  394. return ret;
  395. }
  396. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  397. if (ret < 0) {
  398. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  399. return ret;
  400. }
  401. if (status)
  402. ret |= KXCJK1013_REG_CTRL1_BIT_WUFE;
  403. else
  404. ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE;
  405. ret = i2c_smbus_write_byte_data(data->client,
  406. KXCJK1013_REG_CTRL1, ret);
  407. if (ret < 0) {
  408. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  409. return ret;
  410. }
  411. if (store_mode == OPERATION) {
  412. ret = kxcjk1013_set_mode(data, OPERATION);
  413. if (ret < 0)
  414. return ret;
  415. }
  416. return 0;
  417. }
  418. static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
  419. bool status)
  420. {
  421. int ret;
  422. enum kxcjk1013_mode store_mode;
  423. ret = kxcjk1013_get_mode(data, &store_mode);
  424. if (ret < 0)
  425. return ret;
  426. /* This is requirement by spec to change state to STANDBY */
  427. ret = kxcjk1013_set_mode(data, STANDBY);
  428. if (ret < 0)
  429. return ret;
  430. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
  431. if (ret < 0) {
  432. dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
  433. return ret;
  434. }
  435. if (status)
  436. ret |= KXCJK1013_REG_INT_REG1_BIT_IEN;
  437. else
  438. ret &= ~KXCJK1013_REG_INT_REG1_BIT_IEN;
  439. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
  440. ret);
  441. if (ret < 0) {
  442. dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
  443. return ret;
  444. }
  445. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
  446. if (ret < 0) {
  447. dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
  448. return ret;
  449. }
  450. if (status)
  451. ret |= KXCJK1013_REG_CTRL1_BIT_DRDY;
  452. else
  453. ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY;
  454. ret = i2c_smbus_write_byte_data(data->client,
  455. KXCJK1013_REG_CTRL1, ret);
  456. if (ret < 0) {
  457. dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
  458. return ret;
  459. }
  460. if (store_mode == OPERATION) {
  461. ret = kxcjk1013_set_mode(data, OPERATION);
  462. if (ret < 0)
  463. return ret;
  464. }
  465. return 0;
  466. }
  467. static int kxcjk1013_convert_freq_to_bit(int val, int val2)
  468. {
  469. int i;
  470. for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
  471. if (samp_freq_table[i].val == val &&
  472. samp_freq_table[i].val2 == val2) {
  473. return samp_freq_table[i].odr_bits;
  474. }
  475. }
  476. return -EINVAL;
  477. }
  478. static int kxcjk1013_convert_wake_odr_to_bit(int val, int val2)
  479. {
  480. int i;
  481. for (i = 0; i < ARRAY_SIZE(wake_odr_data_rate_table); ++i) {
  482. if (wake_odr_data_rate_table[i].val == val &&
  483. wake_odr_data_rate_table[i].val2 == val2) {
  484. return wake_odr_data_rate_table[i].odr_bits;
  485. }
  486. }
  487. return -EINVAL;
  488. }
  489. static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
  490. {
  491. int ret;
  492. int odr_bits;
  493. enum kxcjk1013_mode store_mode;
  494. ret = kxcjk1013_get_mode(data, &store_mode);
  495. if (ret < 0)
  496. return ret;
  497. odr_bits = kxcjk1013_convert_freq_to_bit(val, val2);
  498. if (odr_bits < 0)
  499. return odr_bits;
  500. /* To change ODR, the chip must be set to STANDBY as per spec */
  501. ret = kxcjk1013_set_mode(data, STANDBY);
  502. if (ret < 0)
  503. return ret;
  504. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL,
  505. odr_bits);
  506. if (ret < 0) {
  507. dev_err(&data->client->dev, "Error writing data_ctrl\n");
  508. return ret;
  509. }
  510. data->odr_bits = odr_bits;
  511. odr_bits = kxcjk1013_convert_wake_odr_to_bit(val, val2);
  512. if (odr_bits < 0)
  513. return odr_bits;
  514. ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2,
  515. odr_bits);
  516. if (ret < 0) {
  517. dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
  518. return ret;
  519. }
  520. if (store_mode == OPERATION) {
  521. ret = kxcjk1013_set_mode(data, OPERATION);
  522. if (ret < 0)
  523. return ret;
  524. }
  525. return 0;
  526. }
  527. static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
  528. {
  529. int i;
  530. for (i = 0; i < ARRAY_SIZE(samp_freq_table); ++i) {
  531. if (samp_freq_table[i].odr_bits == data->odr_bits) {
  532. *val = samp_freq_table[i].val;
  533. *val2 = samp_freq_table[i].val2;
  534. return IIO_VAL_INT_PLUS_MICRO;
  535. }
  536. }
  537. return -EINVAL;
  538. }
  539. static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
  540. {
  541. u8 reg = KXCJK1013_REG_XOUT_L + axis * 2;
  542. int ret;
  543. ret = i2c_smbus_read_word_data(data->client, reg);
  544. if (ret < 0) {
  545. dev_err(&data->client->dev,
  546. "failed to read accel_%c registers\n", 'x' + axis);
  547. return ret;
  548. }
  549. return ret;
  550. }
  551. static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
  552. {
  553. int ret, i;
  554. enum kxcjk1013_mode store_mode;
  555. for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) {
  556. if (KXCJK1013_scale_table[i].scale == val) {
  557. ret = kxcjk1013_get_mode(data, &store_mode);
  558. if (ret < 0)
  559. return ret;
  560. ret = kxcjk1013_set_mode(data, STANDBY);
  561. if (ret < 0)
  562. return ret;
  563. ret = kxcjk1013_set_range(data, i);
  564. if (ret < 0)
  565. return ret;
  566. if (store_mode == OPERATION) {
  567. ret = kxcjk1013_set_mode(data, OPERATION);
  568. if (ret)
  569. return ret;
  570. }
  571. return 0;
  572. }
  573. }
  574. return -EINVAL;
  575. }
  576. static int kxcjk1013_read_raw(struct iio_dev *indio_dev,
  577. struct iio_chan_spec const *chan, int *val,
  578. int *val2, long mask)
  579. {
  580. struct kxcjk1013_data *data = iio_priv(indio_dev);
  581. int ret;
  582. switch (mask) {
  583. case IIO_CHAN_INFO_RAW:
  584. mutex_lock(&data->mutex);
  585. if (iio_buffer_enabled(indio_dev))
  586. ret = -EBUSY;
  587. else {
  588. ret = kxcjk1013_set_power_state(data, true);
  589. if (ret < 0) {
  590. mutex_unlock(&data->mutex);
  591. return ret;
  592. }
  593. ret = kxcjk1013_get_acc_reg(data, chan->scan_index);
  594. if (ret < 0) {
  595. kxcjk1013_set_power_state(data, false);
  596. mutex_unlock(&data->mutex);
  597. return ret;
  598. }
  599. *val = sign_extend32(ret >> 4, 11);
  600. ret = kxcjk1013_set_power_state(data, false);
  601. }
  602. mutex_unlock(&data->mutex);
  603. if (ret < 0)
  604. return ret;
  605. return IIO_VAL_INT;
  606. case IIO_CHAN_INFO_SCALE:
  607. *val = 0;
  608. *val2 = KXCJK1013_scale_table[data->range].scale;
  609. return IIO_VAL_INT_PLUS_MICRO;
  610. case IIO_CHAN_INFO_SAMP_FREQ:
  611. mutex_lock(&data->mutex);
  612. ret = kxcjk1013_get_odr(data, val, val2);
  613. mutex_unlock(&data->mutex);
  614. return ret;
  615. default:
  616. return -EINVAL;
  617. }
  618. }
  619. static int kxcjk1013_write_raw(struct iio_dev *indio_dev,
  620. struct iio_chan_spec const *chan, int val,
  621. int val2, long mask)
  622. {
  623. struct kxcjk1013_data *data = iio_priv(indio_dev);
  624. int ret;
  625. switch (mask) {
  626. case IIO_CHAN_INFO_SAMP_FREQ:
  627. mutex_lock(&data->mutex);
  628. ret = kxcjk1013_set_odr(data, val, val2);
  629. mutex_unlock(&data->mutex);
  630. break;
  631. case IIO_CHAN_INFO_SCALE:
  632. if (val)
  633. return -EINVAL;
  634. mutex_lock(&data->mutex);
  635. ret = kxcjk1013_set_scale(data, val2);
  636. mutex_unlock(&data->mutex);
  637. break;
  638. default:
  639. ret = -EINVAL;
  640. }
  641. return ret;
  642. }
  643. static int kxcjk1013_read_event(struct iio_dev *indio_dev,
  644. const struct iio_chan_spec *chan,
  645. enum iio_event_type type,
  646. enum iio_event_direction dir,
  647. enum iio_event_info info,
  648. int *val, int *val2)
  649. {
  650. struct kxcjk1013_data *data = iio_priv(indio_dev);
  651. *val2 = 0;
  652. switch (info) {
  653. case IIO_EV_INFO_VALUE:
  654. *val = data->wake_thres;
  655. break;
  656. case IIO_EV_INFO_PERIOD:
  657. *val = data->wake_dur;
  658. break;
  659. default:
  660. return -EINVAL;
  661. }
  662. return IIO_VAL_INT;
  663. }
  664. static int kxcjk1013_write_event(struct iio_dev *indio_dev,
  665. const struct iio_chan_spec *chan,
  666. enum iio_event_type type,
  667. enum iio_event_direction dir,
  668. enum iio_event_info info,
  669. int val, int val2)
  670. {
  671. struct kxcjk1013_data *data = iio_priv(indio_dev);
  672. if (data->ev_enable_state)
  673. return -EBUSY;
  674. switch (info) {
  675. case IIO_EV_INFO_VALUE:
  676. data->wake_thres = val;
  677. break;
  678. case IIO_EV_INFO_PERIOD:
  679. data->wake_dur = val;
  680. break;
  681. default:
  682. return -EINVAL;
  683. }
  684. return 0;
  685. }
  686. static int kxcjk1013_read_event_config(struct iio_dev *indio_dev,
  687. const struct iio_chan_spec *chan,
  688. enum iio_event_type type,
  689. enum iio_event_direction dir)
  690. {
  691. struct kxcjk1013_data *data = iio_priv(indio_dev);
  692. return data->ev_enable_state;
  693. }
  694. static int kxcjk1013_write_event_config(struct iio_dev *indio_dev,
  695. const struct iio_chan_spec *chan,
  696. enum iio_event_type type,
  697. enum iio_event_direction dir,
  698. int state)
  699. {
  700. struct kxcjk1013_data *data = iio_priv(indio_dev);
  701. int ret;
  702. if (state && data->ev_enable_state)
  703. return 0;
  704. mutex_lock(&data->mutex);
  705. if (!state && data->motion_trigger_on) {
  706. data->ev_enable_state = 0;
  707. mutex_unlock(&data->mutex);
  708. return 0;
  709. }
  710. /*
  711. * We will expect the enable and disable to do operation in
  712. * in reverse order. This will happen here anyway as our
  713. * resume operation uses sync mode runtime pm calls, the
  714. * suspend operation will be delayed by autosuspend delay
  715. * So the disable operation will still happen in reverse of
  716. * enable operation. When runtime pm is disabled the mode
  717. * is always on so sequence doesn't matter
  718. */
  719. ret = kxcjk1013_set_power_state(data, state);
  720. if (ret < 0) {
  721. mutex_unlock(&data->mutex);
  722. return ret;
  723. }
  724. ret = kxcjk1013_setup_any_motion_interrupt(data, state);
  725. if (ret < 0) {
  726. kxcjk1013_set_power_state(data, false);
  727. data->ev_enable_state = 0;
  728. mutex_unlock(&data->mutex);
  729. return ret;
  730. }
  731. data->ev_enable_state = state;
  732. mutex_unlock(&data->mutex);
  733. return 0;
  734. }
  735. static int kxcjk1013_buffer_preenable(struct iio_dev *indio_dev)
  736. {
  737. struct kxcjk1013_data *data = iio_priv(indio_dev);
  738. return kxcjk1013_set_power_state(data, true);
  739. }
  740. static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev)
  741. {
  742. struct kxcjk1013_data *data = iio_priv(indio_dev);
  743. return kxcjk1013_set_power_state(data, false);
  744. }
  745. static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
  746. "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600");
  747. static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
  748. static struct attribute *kxcjk1013_attributes[] = {
  749. &iio_const_attr_sampling_frequency_available.dev_attr.attr,
  750. &iio_const_attr_in_accel_scale_available.dev_attr.attr,
  751. NULL,
  752. };
  753. static const struct attribute_group kxcjk1013_attrs_group = {
  754. .attrs = kxcjk1013_attributes,
  755. };
  756. static const struct iio_event_spec kxcjk1013_event = {
  757. .type = IIO_EV_TYPE_THRESH,
  758. .dir = IIO_EV_DIR_EITHER,
  759. .mask_separate = BIT(IIO_EV_INFO_VALUE) |
  760. BIT(IIO_EV_INFO_ENABLE) |
  761. BIT(IIO_EV_INFO_PERIOD)
  762. };
  763. #define KXCJK1013_CHANNEL(_axis) { \
  764. .type = IIO_ACCEL, \
  765. .modified = 1, \
  766. .channel2 = IIO_MOD_##_axis, \
  767. .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
  768. .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
  769. BIT(IIO_CHAN_INFO_SAMP_FREQ), \
  770. .scan_index = AXIS_##_axis, \
  771. .scan_type = { \
  772. .sign = 's', \
  773. .realbits = 12, \
  774. .storagebits = 16, \
  775. .shift = 4, \
  776. .endianness = IIO_CPU, \
  777. }, \
  778. .event_spec = &kxcjk1013_event, \
  779. .num_event_specs = 1 \
  780. }
  781. static const struct iio_chan_spec kxcjk1013_channels[] = {
  782. KXCJK1013_CHANNEL(X),
  783. KXCJK1013_CHANNEL(Y),
  784. KXCJK1013_CHANNEL(Z),
  785. IIO_CHAN_SOFT_TIMESTAMP(3),
  786. };
  787. static const struct iio_buffer_setup_ops kxcjk1013_buffer_setup_ops = {
  788. .preenable = kxcjk1013_buffer_preenable,
  789. .postenable = iio_triggered_buffer_postenable,
  790. .postdisable = kxcjk1013_buffer_postdisable,
  791. .predisable = iio_triggered_buffer_predisable,
  792. };
  793. static const struct iio_info kxcjk1013_info = {
  794. .attrs = &kxcjk1013_attrs_group,
  795. .read_raw = kxcjk1013_read_raw,
  796. .write_raw = kxcjk1013_write_raw,
  797. .read_event_value = kxcjk1013_read_event,
  798. .write_event_value = kxcjk1013_write_event,
  799. .write_event_config = kxcjk1013_write_event_config,
  800. .read_event_config = kxcjk1013_read_event_config,
  801. .driver_module = THIS_MODULE,
  802. };
  803. static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p)
  804. {
  805. struct iio_poll_func *pf = p;
  806. struct iio_dev *indio_dev = pf->indio_dev;
  807. struct kxcjk1013_data *data = iio_priv(indio_dev);
  808. int bit, ret, i = 0;
  809. mutex_lock(&data->mutex);
  810. for_each_set_bit(bit, indio_dev->active_scan_mask,
  811. indio_dev->masklength) {
  812. ret = kxcjk1013_get_acc_reg(data, bit);
  813. if (ret < 0) {
  814. mutex_unlock(&data->mutex);
  815. goto err;
  816. }
  817. data->buffer[i++] = ret;
  818. }
  819. mutex_unlock(&data->mutex);
  820. iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
  821. data->timestamp);
  822. err:
  823. iio_trigger_notify_done(indio_dev->trig);
  824. return IRQ_HANDLED;
  825. }
  826. static int kxcjk1013_trig_try_reen(struct iio_trigger *trig)
  827. {
  828. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  829. struct kxcjk1013_data *data = iio_priv(indio_dev);
  830. int ret;
  831. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
  832. if (ret < 0) {
  833. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  834. return ret;
  835. }
  836. return 0;
  837. }
  838. static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
  839. bool state)
  840. {
  841. struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
  842. struct kxcjk1013_data *data = iio_priv(indio_dev);
  843. int ret;
  844. mutex_lock(&data->mutex);
  845. if (!state && data->ev_enable_state && data->motion_trigger_on) {
  846. data->motion_trigger_on = false;
  847. mutex_unlock(&data->mutex);
  848. return 0;
  849. }
  850. ret = kxcjk1013_set_power_state(data, state);
  851. if (ret < 0) {
  852. mutex_unlock(&data->mutex);
  853. return ret;
  854. }
  855. if (data->motion_trig == trig)
  856. ret = kxcjk1013_setup_any_motion_interrupt(data, state);
  857. else
  858. ret = kxcjk1013_setup_new_data_interrupt(data, state);
  859. if (ret < 0) {
  860. kxcjk1013_set_power_state(data, false);
  861. mutex_unlock(&data->mutex);
  862. return ret;
  863. }
  864. if (data->motion_trig == trig)
  865. data->motion_trigger_on = state;
  866. else
  867. data->dready_trigger_on = state;
  868. mutex_unlock(&data->mutex);
  869. return 0;
  870. }
  871. static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
  872. .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
  873. .try_reenable = kxcjk1013_trig_try_reen,
  874. .owner = THIS_MODULE,
  875. };
  876. static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
  877. {
  878. struct iio_dev *indio_dev = private;
  879. struct kxcjk1013_data *data = iio_priv(indio_dev);
  880. int ret;
  881. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_SRC1);
  882. if (ret < 0) {
  883. dev_err(&data->client->dev, "Error reading reg_int_src1\n");
  884. goto ack_intr;
  885. }
  886. if (ret & 0x02) {
  887. ret = i2c_smbus_read_byte_data(data->client,
  888. KXCJK1013_REG_INT_SRC2);
  889. if (ret < 0) {
  890. dev_err(&data->client->dev,
  891. "Error reading reg_int_src2\n");
  892. goto ack_intr;
  893. }
  894. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
  895. iio_push_event(indio_dev,
  896. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  897. 0,
  898. IIO_MOD_X,
  899. IIO_EV_TYPE_THRESH,
  900. IIO_EV_DIR_FALLING),
  901. data->timestamp);
  902. if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
  903. iio_push_event(indio_dev,
  904. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  905. 0,
  906. IIO_MOD_X,
  907. IIO_EV_TYPE_THRESH,
  908. IIO_EV_DIR_RISING),
  909. data->timestamp);
  910. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
  911. iio_push_event(indio_dev,
  912. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  913. 0,
  914. IIO_MOD_Y,
  915. IIO_EV_TYPE_THRESH,
  916. IIO_EV_DIR_FALLING),
  917. data->timestamp);
  918. if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
  919. iio_push_event(indio_dev,
  920. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  921. 0,
  922. IIO_MOD_Y,
  923. IIO_EV_TYPE_THRESH,
  924. IIO_EV_DIR_RISING),
  925. data->timestamp);
  926. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
  927. iio_push_event(indio_dev,
  928. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  929. 0,
  930. IIO_MOD_Z,
  931. IIO_EV_TYPE_THRESH,
  932. IIO_EV_DIR_FALLING),
  933. data->timestamp);
  934. if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
  935. iio_push_event(indio_dev,
  936. IIO_MOD_EVENT_CODE(IIO_ACCEL,
  937. 0,
  938. IIO_MOD_Z,
  939. IIO_EV_TYPE_THRESH,
  940. IIO_EV_DIR_RISING),
  941. data->timestamp);
  942. }
  943. ack_intr:
  944. if (data->dready_trigger_on)
  945. return IRQ_HANDLED;
  946. ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
  947. if (ret < 0)
  948. dev_err(&data->client->dev, "Error reading reg_int_rel\n");
  949. return IRQ_HANDLED;
  950. }
  951. static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private)
  952. {
  953. struct iio_dev *indio_dev = private;
  954. struct kxcjk1013_data *data = iio_priv(indio_dev);
  955. data->timestamp = iio_get_time_ns();
  956. if (data->dready_trigger_on)
  957. iio_trigger_poll(data->dready_trig);
  958. else if (data->motion_trigger_on)
  959. iio_trigger_poll(data->motion_trig);
  960. if (data->ev_enable_state)
  961. return IRQ_WAKE_THREAD;
  962. else
  963. return IRQ_HANDLED;
  964. }
  965. static const char *kxcjk1013_match_acpi_device(struct device *dev,
  966. enum kx_chipset *chipset,
  967. bool *is_smo8500_device)
  968. {
  969. const struct acpi_device_id *id;
  970. id = acpi_match_device(dev->driver->acpi_match_table, dev);
  971. if (!id)
  972. return NULL;
  973. if (strcmp(id->id, "SMO8500") == 0)
  974. *is_smo8500_device = true;
  975. *chipset = (enum kx_chipset)id->driver_data;
  976. return dev_name(dev);
  977. }
  978. static int kxcjk1013_gpio_probe(struct i2c_client *client,
  979. struct kxcjk1013_data *data)
  980. {
  981. struct device *dev;
  982. struct gpio_desc *gpio;
  983. int ret;
  984. if (!client)
  985. return -EINVAL;
  986. if (data->is_smo8500_device)
  987. return -ENOTSUPP;
  988. dev = &client->dev;
  989. /* data ready gpio interrupt pin */
  990. gpio = devm_gpiod_get_index(dev, "kxcjk1013_int", 0, GPIOD_IN);
  991. if (IS_ERR(gpio)) {
  992. dev_err(dev, "acpi gpio get index failed\n");
  993. return PTR_ERR(gpio);
  994. }
  995. ret = gpiod_to_irq(gpio);
  996. dev_dbg(dev, "GPIO resource, no:%d irq:%d\n", desc_to_gpio(gpio), ret);
  997. return ret;
  998. }
  999. static int kxcjk1013_probe(struct i2c_client *client,
  1000. const struct i2c_device_id *id)
  1001. {
  1002. struct kxcjk1013_data *data;
  1003. struct iio_dev *indio_dev;
  1004. struct kxcjk_1013_platform_data *pdata;
  1005. const char *name;
  1006. int ret;
  1007. indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
  1008. if (!indio_dev)
  1009. return -ENOMEM;
  1010. data = iio_priv(indio_dev);
  1011. i2c_set_clientdata(client, indio_dev);
  1012. data->client = client;
  1013. pdata = dev_get_platdata(&client->dev);
  1014. if (pdata)
  1015. data->active_high_intr = pdata->active_high_intr;
  1016. else
  1017. data->active_high_intr = true; /* default polarity */
  1018. if (id) {
  1019. data->chipset = (enum kx_chipset)(id->driver_data);
  1020. name = id->name;
  1021. } else if (ACPI_HANDLE(&client->dev)) {
  1022. name = kxcjk1013_match_acpi_device(&client->dev,
  1023. &data->chipset,
  1024. &data->is_smo8500_device);
  1025. } else
  1026. return -ENODEV;
  1027. ret = kxcjk1013_chip_init(data);
  1028. if (ret < 0)
  1029. return ret;
  1030. mutex_init(&data->mutex);
  1031. indio_dev->dev.parent = &client->dev;
  1032. indio_dev->channels = kxcjk1013_channels;
  1033. indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels);
  1034. indio_dev->name = name;
  1035. indio_dev->modes = INDIO_DIRECT_MODE;
  1036. indio_dev->info = &kxcjk1013_info;
  1037. if (client->irq < 0)
  1038. client->irq = kxcjk1013_gpio_probe(client, data);
  1039. if (client->irq >= 0) {
  1040. ret = devm_request_threaded_irq(&client->dev, client->irq,
  1041. kxcjk1013_data_rdy_trig_poll,
  1042. kxcjk1013_event_handler,
  1043. IRQF_TRIGGER_RISING,
  1044. KXCJK1013_IRQ_NAME,
  1045. indio_dev);
  1046. if (ret)
  1047. goto err_poweroff;
  1048. data->dready_trig = devm_iio_trigger_alloc(&client->dev,
  1049. "%s-dev%d",
  1050. indio_dev->name,
  1051. indio_dev->id);
  1052. if (!data->dready_trig) {
  1053. ret = -ENOMEM;
  1054. goto err_poweroff;
  1055. }
  1056. data->motion_trig = devm_iio_trigger_alloc(&client->dev,
  1057. "%s-any-motion-dev%d",
  1058. indio_dev->name,
  1059. indio_dev->id);
  1060. if (!data->motion_trig) {
  1061. ret = -ENOMEM;
  1062. goto err_poweroff;
  1063. }
  1064. data->dready_trig->dev.parent = &client->dev;
  1065. data->dready_trig->ops = &kxcjk1013_trigger_ops;
  1066. iio_trigger_set_drvdata(data->dready_trig, indio_dev);
  1067. indio_dev->trig = data->dready_trig;
  1068. iio_trigger_get(indio_dev->trig);
  1069. ret = iio_trigger_register(data->dready_trig);
  1070. if (ret)
  1071. goto err_poweroff;
  1072. data->motion_trig->dev.parent = &client->dev;
  1073. data->motion_trig->ops = &kxcjk1013_trigger_ops;
  1074. iio_trigger_set_drvdata(data->motion_trig, indio_dev);
  1075. ret = iio_trigger_register(data->motion_trig);
  1076. if (ret) {
  1077. data->motion_trig = NULL;
  1078. goto err_trigger_unregister;
  1079. }
  1080. }
  1081. ret = iio_triggered_buffer_setup(indio_dev,
  1082. &iio_pollfunc_store_time,
  1083. kxcjk1013_trigger_handler,
  1084. &kxcjk1013_buffer_setup_ops);
  1085. if (ret < 0) {
  1086. dev_err(&client->dev, "iio triggered buffer setup failed\n");
  1087. goto err_trigger_unregister;
  1088. }
  1089. ret = iio_device_register(indio_dev);
  1090. if (ret < 0) {
  1091. dev_err(&client->dev, "unable to register iio device\n");
  1092. goto err_buffer_cleanup;
  1093. }
  1094. ret = pm_runtime_set_active(&client->dev);
  1095. if (ret)
  1096. goto err_iio_unregister;
  1097. pm_runtime_enable(&client->dev);
  1098. pm_runtime_set_autosuspend_delay(&client->dev,
  1099. KXCJK1013_SLEEP_DELAY_MS);
  1100. pm_runtime_use_autosuspend(&client->dev);
  1101. return 0;
  1102. err_iio_unregister:
  1103. iio_device_unregister(indio_dev);
  1104. err_buffer_cleanup:
  1105. if (data->dready_trig)
  1106. iio_triggered_buffer_cleanup(indio_dev);
  1107. err_trigger_unregister:
  1108. if (data->dready_trig)
  1109. iio_trigger_unregister(data->dready_trig);
  1110. if (data->motion_trig)
  1111. iio_trigger_unregister(data->motion_trig);
  1112. err_poweroff:
  1113. kxcjk1013_set_mode(data, STANDBY);
  1114. return ret;
  1115. }
  1116. static int kxcjk1013_remove(struct i2c_client *client)
  1117. {
  1118. struct iio_dev *indio_dev = i2c_get_clientdata(client);
  1119. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1120. pm_runtime_disable(&client->dev);
  1121. pm_runtime_set_suspended(&client->dev);
  1122. pm_runtime_put_noidle(&client->dev);
  1123. iio_device_unregister(indio_dev);
  1124. if (data->dready_trig) {
  1125. iio_triggered_buffer_cleanup(indio_dev);
  1126. iio_trigger_unregister(data->dready_trig);
  1127. iio_trigger_unregister(data->motion_trig);
  1128. }
  1129. mutex_lock(&data->mutex);
  1130. kxcjk1013_set_mode(data, STANDBY);
  1131. mutex_unlock(&data->mutex);
  1132. return 0;
  1133. }
  1134. #ifdef CONFIG_PM_SLEEP
  1135. static int kxcjk1013_suspend(struct device *dev)
  1136. {
  1137. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1138. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1139. int ret;
  1140. mutex_lock(&data->mutex);
  1141. ret = kxcjk1013_set_mode(data, STANDBY);
  1142. mutex_unlock(&data->mutex);
  1143. return ret;
  1144. }
  1145. static int kxcjk1013_resume(struct device *dev)
  1146. {
  1147. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1148. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1149. int ret = 0;
  1150. mutex_lock(&data->mutex);
  1151. ret = kxcjk1013_set_mode(data, OPERATION);
  1152. mutex_unlock(&data->mutex);
  1153. return ret;
  1154. }
  1155. #endif
  1156. #ifdef CONFIG_PM
  1157. static int kxcjk1013_runtime_suspend(struct device *dev)
  1158. {
  1159. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1160. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1161. int ret;
  1162. ret = kxcjk1013_set_mode(data, STANDBY);
  1163. if (ret < 0) {
  1164. dev_err(&data->client->dev, "powering off device failed\n");
  1165. return -EAGAIN;
  1166. }
  1167. return 0;
  1168. }
  1169. static int kxcjk1013_runtime_resume(struct device *dev)
  1170. {
  1171. struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
  1172. struct kxcjk1013_data *data = iio_priv(indio_dev);
  1173. int ret;
  1174. int sleep_val;
  1175. ret = kxcjk1013_set_mode(data, OPERATION);
  1176. if (ret < 0)
  1177. return ret;
  1178. sleep_val = kxcjk1013_get_startup_times(data);
  1179. if (sleep_val < 20000)
  1180. usleep_range(sleep_val, 20000);
  1181. else
  1182. msleep_interruptible(sleep_val/1000);
  1183. return 0;
  1184. }
  1185. #endif
  1186. static const struct dev_pm_ops kxcjk1013_pm_ops = {
  1187. SET_SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume)
  1188. SET_RUNTIME_PM_OPS(kxcjk1013_runtime_suspend,
  1189. kxcjk1013_runtime_resume, NULL)
  1190. };
  1191. static const struct acpi_device_id kx_acpi_match[] = {
  1192. {"KXCJ1013", KXCJK1013},
  1193. {"KXCJ1008", KXCJ91008},
  1194. {"KXCJ9000", KXCJ91008},
  1195. {"KXTJ1009", KXTJ21009},
  1196. {"SMO8500", KXCJ91008},
  1197. { },
  1198. };
  1199. MODULE_DEVICE_TABLE(acpi, kx_acpi_match);
  1200. static const struct i2c_device_id kxcjk1013_id[] = {
  1201. {"kxcjk1013", KXCJK1013},
  1202. {"kxcj91008", KXCJ91008},
  1203. {"kxtj21009", KXTJ21009},
  1204. {"SMO8500", KXCJ91008},
  1205. {}
  1206. };
  1207. MODULE_DEVICE_TABLE(i2c, kxcjk1013_id);
  1208. static struct i2c_driver kxcjk1013_driver = {
  1209. .driver = {
  1210. .name = KXCJK1013_DRV_NAME,
  1211. .acpi_match_table = ACPI_PTR(kx_acpi_match),
  1212. .pm = &kxcjk1013_pm_ops,
  1213. },
  1214. .probe = kxcjk1013_probe,
  1215. .remove = kxcjk1013_remove,
  1216. .id_table = kxcjk1013_id,
  1217. };
  1218. module_i2c_driver(kxcjk1013_driver);
  1219. MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
  1220. MODULE_LICENSE("GPL v2");
  1221. MODULE_DESCRIPTION("KXCJK1013 accelerometer driver");