gpio-tz1090-pdc.c 6.0 KB

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  1. /*
  2. * Toumaz Xenif TZ1090 PDC GPIO handling.
  3. *
  4. * Copyright (C) 2012-2013 Imagination Technologies Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/bitops.h>
  11. #include <linux/gpio.h>
  12. #include <linux/io.h>
  13. #include <linux/module.h>
  14. #include <linux/of_irq.h>
  15. #include <linux/pinctrl/consumer.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include <linux/syscore_ops.h>
  19. #include <asm/global_lock.h>
  20. /* Register offsets from SOC_GPIO_CONTROL0 */
  21. #define REG_SOC_GPIO_CONTROL0 0x00
  22. #define REG_SOC_GPIO_CONTROL1 0x04
  23. #define REG_SOC_GPIO_CONTROL2 0x08
  24. #define REG_SOC_GPIO_CONTROL3 0x0c
  25. #define REG_SOC_GPIO_STATUS 0x80
  26. /* PDC GPIOs go after normal GPIOs */
  27. #define GPIO_PDC_BASE 90
  28. #define GPIO_PDC_NGPIO 7
  29. /* Out of PDC gpios, only syswakes have irqs */
  30. #define GPIO_PDC_IRQ_FIRST 2
  31. #define GPIO_PDC_NIRQ 3
  32. /**
  33. * struct tz1090_pdc_gpio - GPIO bank private data
  34. * @chip: Generic GPIO chip for GPIO bank
  35. * @reg: Base of registers, offset for this GPIO bank
  36. * @irq: IRQ numbers for Syswake GPIOs
  37. *
  38. * This is the main private data for the PDC GPIO driver. It encapsulates a
  39. * gpio_chip, and the callbacks for the gpio_chip can access the private data
  40. * with the to_pdc() macro below.
  41. */
  42. struct tz1090_pdc_gpio {
  43. struct gpio_chip chip;
  44. void __iomem *reg;
  45. int irq[GPIO_PDC_NIRQ];
  46. };
  47. #define to_pdc(c) container_of(c, struct tz1090_pdc_gpio, chip)
  48. /* Register accesses into the PDC MMIO area */
  49. static inline void pdc_write(struct tz1090_pdc_gpio *priv, unsigned int reg_offs,
  50. unsigned int data)
  51. {
  52. writel(data, priv->reg + reg_offs);
  53. }
  54. static inline unsigned int pdc_read(struct tz1090_pdc_gpio *priv,
  55. unsigned int reg_offs)
  56. {
  57. return readl(priv->reg + reg_offs);
  58. }
  59. /* Generic GPIO interface */
  60. static int tz1090_pdc_gpio_direction_input(struct gpio_chip *chip,
  61. unsigned int offset)
  62. {
  63. struct tz1090_pdc_gpio *priv = to_pdc(chip);
  64. u32 value;
  65. int lstat;
  66. __global_lock2(lstat);
  67. value = pdc_read(priv, REG_SOC_GPIO_CONTROL1);
  68. value |= BIT(offset);
  69. pdc_write(priv, REG_SOC_GPIO_CONTROL1, value);
  70. __global_unlock2(lstat);
  71. return 0;
  72. }
  73. static int tz1090_pdc_gpio_direction_output(struct gpio_chip *chip,
  74. unsigned int offset,
  75. int output_value)
  76. {
  77. struct tz1090_pdc_gpio *priv = to_pdc(chip);
  78. u32 value;
  79. int lstat;
  80. __global_lock2(lstat);
  81. /* EXT_POWER doesn't seem to have an output value bit */
  82. if (offset < 6) {
  83. value = pdc_read(priv, REG_SOC_GPIO_CONTROL0);
  84. if (output_value)
  85. value |= BIT(offset);
  86. else
  87. value &= ~BIT(offset);
  88. pdc_write(priv, REG_SOC_GPIO_CONTROL0, value);
  89. }
  90. value = pdc_read(priv, REG_SOC_GPIO_CONTROL1);
  91. value &= ~BIT(offset);
  92. pdc_write(priv, REG_SOC_GPIO_CONTROL1, value);
  93. __global_unlock2(lstat);
  94. return 0;
  95. }
  96. static int tz1090_pdc_gpio_get(struct gpio_chip *chip, unsigned int offset)
  97. {
  98. struct tz1090_pdc_gpio *priv = to_pdc(chip);
  99. return pdc_read(priv, REG_SOC_GPIO_STATUS) & BIT(offset);
  100. }
  101. static void tz1090_pdc_gpio_set(struct gpio_chip *chip, unsigned int offset,
  102. int output_value)
  103. {
  104. struct tz1090_pdc_gpio *priv = to_pdc(chip);
  105. u32 value;
  106. int lstat;
  107. /* EXT_POWER doesn't seem to have an output value bit */
  108. if (offset >= 6)
  109. return;
  110. __global_lock2(lstat);
  111. value = pdc_read(priv, REG_SOC_GPIO_CONTROL0);
  112. if (output_value)
  113. value |= BIT(offset);
  114. else
  115. value &= ~BIT(offset);
  116. pdc_write(priv, REG_SOC_GPIO_CONTROL0, value);
  117. __global_unlock2(lstat);
  118. }
  119. static int tz1090_pdc_gpio_request(struct gpio_chip *chip, unsigned int offset)
  120. {
  121. return pinctrl_request_gpio(chip->base + offset);
  122. }
  123. static void tz1090_pdc_gpio_free(struct gpio_chip *chip, unsigned int offset)
  124. {
  125. pinctrl_free_gpio(chip->base + offset);
  126. }
  127. static int tz1090_pdc_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
  128. {
  129. struct tz1090_pdc_gpio *priv = to_pdc(chip);
  130. unsigned int syswake = offset - GPIO_PDC_IRQ_FIRST;
  131. int irq;
  132. /* only syswakes have irqs */
  133. if (syswake >= GPIO_PDC_NIRQ)
  134. return -EINVAL;
  135. irq = priv->irq[syswake];
  136. if (!irq)
  137. return -EINVAL;
  138. return irq;
  139. }
  140. static int tz1090_pdc_gpio_probe(struct platform_device *pdev)
  141. {
  142. struct device_node *np = pdev->dev.of_node;
  143. struct resource *res_regs;
  144. struct tz1090_pdc_gpio *priv;
  145. unsigned int i;
  146. if (!np) {
  147. dev_err(&pdev->dev, "must be instantiated via devicetree\n");
  148. return -ENOENT;
  149. }
  150. res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  151. if (!res_regs) {
  152. dev_err(&pdev->dev, "cannot find registers resource\n");
  153. return -ENOENT;
  154. }
  155. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  156. if (!priv) {
  157. dev_err(&pdev->dev, "unable to allocate driver data\n");
  158. return -ENOMEM;
  159. }
  160. /* Ioremap the registers */
  161. priv->reg = devm_ioremap(&pdev->dev, res_regs->start,
  162. resource_size(res_regs));
  163. if (!priv->reg) {
  164. dev_err(&pdev->dev, "unable to ioremap registers\n");
  165. return -ENOMEM;
  166. }
  167. /* Set up GPIO chip */
  168. priv->chip.label = "tz1090-pdc-gpio";
  169. priv->chip.dev = &pdev->dev;
  170. priv->chip.direction_input = tz1090_pdc_gpio_direction_input;
  171. priv->chip.direction_output = tz1090_pdc_gpio_direction_output;
  172. priv->chip.get = tz1090_pdc_gpio_get;
  173. priv->chip.set = tz1090_pdc_gpio_set;
  174. priv->chip.free = tz1090_pdc_gpio_free;
  175. priv->chip.request = tz1090_pdc_gpio_request;
  176. priv->chip.to_irq = tz1090_pdc_gpio_to_irq;
  177. priv->chip.of_node = np;
  178. /* GPIO numbering */
  179. priv->chip.base = GPIO_PDC_BASE;
  180. priv->chip.ngpio = GPIO_PDC_NGPIO;
  181. /* Map the syswake irqs */
  182. for (i = 0; i < GPIO_PDC_NIRQ; ++i)
  183. priv->irq[i] = irq_of_parse_and_map(np, i);
  184. /* Add the GPIO bank */
  185. gpiochip_add(&priv->chip);
  186. return 0;
  187. }
  188. static struct of_device_id tz1090_pdc_gpio_of_match[] = {
  189. { .compatible = "img,tz1090-pdc-gpio" },
  190. { },
  191. };
  192. static struct platform_driver tz1090_pdc_gpio_driver = {
  193. .driver = {
  194. .name = "tz1090-pdc-gpio",
  195. .of_match_table = tz1090_pdc_gpio_of_match,
  196. },
  197. .probe = tz1090_pdc_gpio_probe,
  198. };
  199. static int __init tz1090_pdc_gpio_init(void)
  200. {
  201. return platform_driver_register(&tz1090_pdc_gpio_driver);
  202. }
  203. subsys_initcall(tz1090_pdc_gpio_init);