gpio-tc3589x.c 8.5 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License, version 2
  5. * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #include <linux/gpio.h>
  13. #include <linux/of.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mfd/tc3589x.h>
  16. /*
  17. * These registers are modified under the irq bus lock and cached to avoid
  18. * unnecessary writes in bus_sync_unlock.
  19. */
  20. enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
  21. #define CACHE_NR_REGS 4
  22. #define CACHE_NR_BANKS 3
  23. struct tc3589x_gpio {
  24. struct gpio_chip chip;
  25. struct tc3589x *tc3589x;
  26. struct device *dev;
  27. struct mutex irq_lock;
  28. /* Caches of interrupt control registers for bus_lock */
  29. u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  30. u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  31. };
  32. static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip)
  33. {
  34. return container_of(chip, struct tc3589x_gpio, chip);
  35. }
  36. static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
  37. {
  38. struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
  39. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  40. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  41. u8 mask = 1 << (offset % 8);
  42. int ret;
  43. ret = tc3589x_reg_read(tc3589x, reg);
  44. if (ret < 0)
  45. return ret;
  46. return ret & mask;
  47. }
  48. static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  49. {
  50. struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
  51. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  52. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  53. unsigned pos = offset % 8;
  54. u8 data[] = {!!val << pos, 1 << pos};
  55. tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
  56. }
  57. static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
  58. unsigned offset, int val)
  59. {
  60. struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
  61. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  62. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  63. unsigned pos = offset % 8;
  64. tc3589x_gpio_set(chip, offset, val);
  65. return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos);
  66. }
  67. static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
  68. unsigned offset)
  69. {
  70. struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
  71. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  72. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  73. unsigned pos = offset % 8;
  74. return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
  75. }
  76. static struct gpio_chip template_chip = {
  77. .label = "tc3589x",
  78. .owner = THIS_MODULE,
  79. .direction_input = tc3589x_gpio_direction_input,
  80. .get = tc3589x_gpio_get,
  81. .direction_output = tc3589x_gpio_direction_output,
  82. .set = tc3589x_gpio_set,
  83. .can_sleep = true,
  84. };
  85. static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  86. {
  87. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  88. struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
  89. int offset = d->hwirq;
  90. int regoffset = offset / 8;
  91. int mask = 1 << (offset % 8);
  92. if (type == IRQ_TYPE_EDGE_BOTH) {
  93. tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
  94. return 0;
  95. }
  96. tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
  97. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
  98. tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
  99. else
  100. tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
  101. if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
  102. tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
  103. else
  104. tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
  105. return 0;
  106. }
  107. static void tc3589x_gpio_irq_lock(struct irq_data *d)
  108. {
  109. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  110. struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
  111. mutex_lock(&tc3589x_gpio->irq_lock);
  112. }
  113. static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
  114. {
  115. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  116. struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
  117. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  118. static const u8 regmap[] = {
  119. [REG_IBE] = TC3589x_GPIOIBE0,
  120. [REG_IEV] = TC3589x_GPIOIEV0,
  121. [REG_IS] = TC3589x_GPIOIS0,
  122. [REG_IE] = TC3589x_GPIOIE0,
  123. };
  124. int i, j;
  125. for (i = 0; i < CACHE_NR_REGS; i++) {
  126. for (j = 0; j < CACHE_NR_BANKS; j++) {
  127. u8 old = tc3589x_gpio->oldregs[i][j];
  128. u8 new = tc3589x_gpio->regs[i][j];
  129. if (new == old)
  130. continue;
  131. tc3589x_gpio->oldregs[i][j] = new;
  132. tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
  133. }
  134. }
  135. mutex_unlock(&tc3589x_gpio->irq_lock);
  136. }
  137. static void tc3589x_gpio_irq_mask(struct irq_data *d)
  138. {
  139. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  140. struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
  141. int offset = d->hwirq;
  142. int regoffset = offset / 8;
  143. int mask = 1 << (offset % 8);
  144. tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
  145. }
  146. static void tc3589x_gpio_irq_unmask(struct irq_data *d)
  147. {
  148. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  149. struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
  150. int offset = d->hwirq;
  151. int regoffset = offset / 8;
  152. int mask = 1 << (offset % 8);
  153. tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
  154. }
  155. static struct irq_chip tc3589x_gpio_irq_chip = {
  156. .name = "tc3589x-gpio",
  157. .irq_bus_lock = tc3589x_gpio_irq_lock,
  158. .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
  159. .irq_mask = tc3589x_gpio_irq_mask,
  160. .irq_unmask = tc3589x_gpio_irq_unmask,
  161. .irq_set_type = tc3589x_gpio_irq_set_type,
  162. };
  163. static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
  164. {
  165. struct tc3589x_gpio *tc3589x_gpio = dev;
  166. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  167. u8 status[CACHE_NR_BANKS];
  168. int ret;
  169. int i;
  170. ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
  171. ARRAY_SIZE(status), status);
  172. if (ret < 0)
  173. return IRQ_NONE;
  174. for (i = 0; i < ARRAY_SIZE(status); i++) {
  175. unsigned int stat = status[i];
  176. if (!stat)
  177. continue;
  178. while (stat) {
  179. int bit = __ffs(stat);
  180. int line = i * 8 + bit;
  181. int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
  182. line);
  183. handle_nested_irq(irq);
  184. stat &= ~(1 << bit);
  185. }
  186. tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
  187. }
  188. return IRQ_HANDLED;
  189. }
  190. static int tc3589x_gpio_probe(struct platform_device *pdev)
  191. {
  192. struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
  193. struct device_node *np = pdev->dev.of_node;
  194. struct tc3589x_gpio *tc3589x_gpio;
  195. int ret;
  196. int irq;
  197. if (!np) {
  198. dev_err(&pdev->dev, "No Device Tree node found\n");
  199. return -EINVAL;
  200. }
  201. irq = platform_get_irq(pdev, 0);
  202. if (irq < 0)
  203. return irq;
  204. tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
  205. GFP_KERNEL);
  206. if (!tc3589x_gpio)
  207. return -ENOMEM;
  208. mutex_init(&tc3589x_gpio->irq_lock);
  209. tc3589x_gpio->dev = &pdev->dev;
  210. tc3589x_gpio->tc3589x = tc3589x;
  211. tc3589x_gpio->chip = template_chip;
  212. tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
  213. tc3589x_gpio->chip.dev = &pdev->dev;
  214. tc3589x_gpio->chip.base = -1;
  215. tc3589x_gpio->chip.of_node = np;
  216. /* Bring the GPIO module out of reset */
  217. ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
  218. TC3589x_RSTCTRL_GPIRST, 0);
  219. if (ret < 0)
  220. return ret;
  221. ret = devm_request_threaded_irq(&pdev->dev,
  222. irq, NULL, tc3589x_gpio_irq,
  223. IRQF_ONESHOT, "tc3589x-gpio",
  224. tc3589x_gpio);
  225. if (ret) {
  226. dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
  227. return ret;
  228. }
  229. ret = gpiochip_add(&tc3589x_gpio->chip);
  230. if (ret) {
  231. dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
  232. return ret;
  233. }
  234. ret = gpiochip_irqchip_add(&tc3589x_gpio->chip,
  235. &tc3589x_gpio_irq_chip,
  236. 0,
  237. handle_simple_irq,
  238. IRQ_TYPE_NONE);
  239. if (ret) {
  240. dev_err(&pdev->dev,
  241. "could not connect irqchip to gpiochip\n");
  242. return ret;
  243. }
  244. gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
  245. &tc3589x_gpio_irq_chip,
  246. irq,
  247. NULL);
  248. platform_set_drvdata(pdev, tc3589x_gpio);
  249. return 0;
  250. }
  251. static int tc3589x_gpio_remove(struct platform_device *pdev)
  252. {
  253. struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev);
  254. gpiochip_remove(&tc3589x_gpio->chip);
  255. return 0;
  256. }
  257. static struct platform_driver tc3589x_gpio_driver = {
  258. .driver.name = "tc3589x-gpio",
  259. .driver.owner = THIS_MODULE,
  260. .probe = tc3589x_gpio_probe,
  261. .remove = tc3589x_gpio_remove,
  262. };
  263. static int __init tc3589x_gpio_init(void)
  264. {
  265. return platform_driver_register(&tc3589x_gpio_driver);
  266. }
  267. subsys_initcall(tc3589x_gpio_init);
  268. static void __exit tc3589x_gpio_exit(void)
  269. {
  270. platform_driver_unregister(&tc3589x_gpio_driver);
  271. }
  272. module_exit(tc3589x_gpio_exit);
  273. MODULE_LICENSE("GPL v2");
  274. MODULE_DESCRIPTION("TC3589x GPIO driver");
  275. MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");