gpio-pca953x.c 18 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #ifdef CONFIG_OF_GPIO
  21. #include <linux/of_platform.h>
  22. #endif
  23. #define PCA953X_INPUT 0
  24. #define PCA953X_OUTPUT 1
  25. #define PCA953X_INVERT 2
  26. #define PCA953X_DIRECTION 3
  27. #define REG_ADDR_AI 0x80
  28. #define PCA957X_IN 0
  29. #define PCA957X_INVRT 1
  30. #define PCA957X_BKEN 2
  31. #define PCA957X_PUPD 3
  32. #define PCA957X_CFG 4
  33. #define PCA957X_OUT 5
  34. #define PCA957X_MSK 6
  35. #define PCA957X_INTS 7
  36. #define PCA_GPIO_MASK 0x00FF
  37. #define PCA_INT 0x0100
  38. #define PCA953X_TYPE 0x1000
  39. #define PCA957X_TYPE 0x2000
  40. static const struct i2c_device_id pca953x_id[] = {
  41. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  42. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  43. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  44. { "pca9536", 4 | PCA953X_TYPE, },
  45. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  46. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  47. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  48. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9556", 8 | PCA953X_TYPE, },
  51. { "pca9557", 8 | PCA953X_TYPE, },
  52. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  53. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  54. { "pca9698", 40 | PCA953X_TYPE, },
  55. { "max7310", 8 | PCA953X_TYPE, },
  56. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  57. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  58. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  59. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  60. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  61. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  62. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  63. { "xra1202", 8 | PCA953X_TYPE },
  64. { }
  65. };
  66. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  67. #define MAX_BANK 5
  68. #define BANK_SZ 8
  69. #define NBANK(chip) (chip->gpio_chip.ngpio / BANK_SZ)
  70. struct pca953x_chip {
  71. unsigned gpio_start;
  72. u8 reg_output[MAX_BANK];
  73. u8 reg_direction[MAX_BANK];
  74. struct mutex i2c_lock;
  75. #ifdef CONFIG_GPIO_PCA953X_IRQ
  76. struct mutex irq_lock;
  77. u8 irq_mask[MAX_BANK];
  78. u8 irq_stat[MAX_BANK];
  79. u8 irq_trig_raise[MAX_BANK];
  80. u8 irq_trig_fall[MAX_BANK];
  81. #endif
  82. struct i2c_client *client;
  83. struct gpio_chip gpio_chip;
  84. const char *const *names;
  85. int chip_type;
  86. };
  87. static inline struct pca953x_chip *to_pca(struct gpio_chip *gc)
  88. {
  89. return container_of(gc, struct pca953x_chip, gpio_chip);
  90. }
  91. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  92. int off)
  93. {
  94. int ret;
  95. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  96. int offset = off / BANK_SZ;
  97. ret = i2c_smbus_read_byte_data(chip->client,
  98. (reg << bank_shift) + offset);
  99. *val = ret;
  100. if (ret < 0) {
  101. dev_err(&chip->client->dev, "failed reading register\n");
  102. return ret;
  103. }
  104. return 0;
  105. }
  106. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  107. int off)
  108. {
  109. int ret = 0;
  110. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  111. int offset = off / BANK_SZ;
  112. ret = i2c_smbus_write_byte_data(chip->client,
  113. (reg << bank_shift) + offset, val);
  114. if (ret < 0) {
  115. dev_err(&chip->client->dev, "failed writing register\n");
  116. return ret;
  117. }
  118. return 0;
  119. }
  120. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  121. {
  122. int ret = 0;
  123. if (chip->gpio_chip.ngpio <= 8)
  124. ret = i2c_smbus_write_byte_data(chip->client, reg, *val);
  125. else if (chip->gpio_chip.ngpio >= 24) {
  126. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  127. ret = i2c_smbus_write_i2c_block_data(chip->client,
  128. (reg << bank_shift) | REG_ADDR_AI,
  129. NBANK(chip), val);
  130. } else {
  131. switch (chip->chip_type) {
  132. case PCA953X_TYPE:
  133. ret = i2c_smbus_write_word_data(chip->client,
  134. reg << 1, (u16) *val);
  135. break;
  136. case PCA957X_TYPE:
  137. ret = i2c_smbus_write_byte_data(chip->client, reg << 1,
  138. val[0]);
  139. if (ret < 0)
  140. break;
  141. ret = i2c_smbus_write_byte_data(chip->client,
  142. (reg << 1) + 1,
  143. val[1]);
  144. break;
  145. }
  146. }
  147. if (ret < 0) {
  148. dev_err(&chip->client->dev, "failed writing register\n");
  149. return ret;
  150. }
  151. return 0;
  152. }
  153. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  154. {
  155. int ret;
  156. if (chip->gpio_chip.ngpio <= 8) {
  157. ret = i2c_smbus_read_byte_data(chip->client, reg);
  158. *val = ret;
  159. } else if (chip->gpio_chip.ngpio >= 24) {
  160. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  161. ret = i2c_smbus_read_i2c_block_data(chip->client,
  162. (reg << bank_shift) | REG_ADDR_AI,
  163. NBANK(chip), val);
  164. } else {
  165. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  166. val[0] = (u16)ret & 0xFF;
  167. val[1] = (u16)ret >> 8;
  168. }
  169. if (ret < 0) {
  170. dev_err(&chip->client->dev, "failed reading register\n");
  171. return ret;
  172. }
  173. return 0;
  174. }
  175. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  176. {
  177. struct pca953x_chip *chip = to_pca(gc);
  178. u8 reg_val;
  179. int ret, offset = 0;
  180. mutex_lock(&chip->i2c_lock);
  181. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  182. switch (chip->chip_type) {
  183. case PCA953X_TYPE:
  184. offset = PCA953X_DIRECTION;
  185. break;
  186. case PCA957X_TYPE:
  187. offset = PCA957X_CFG;
  188. break;
  189. }
  190. ret = pca953x_write_single(chip, offset, reg_val, off);
  191. if (ret)
  192. goto exit;
  193. chip->reg_direction[off / BANK_SZ] = reg_val;
  194. ret = 0;
  195. exit:
  196. mutex_unlock(&chip->i2c_lock);
  197. return ret;
  198. }
  199. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  200. unsigned off, int val)
  201. {
  202. struct pca953x_chip *chip = to_pca(gc);
  203. u8 reg_val;
  204. int ret, offset = 0;
  205. mutex_lock(&chip->i2c_lock);
  206. /* set output level */
  207. if (val)
  208. reg_val = chip->reg_output[off / BANK_SZ]
  209. | (1u << (off % BANK_SZ));
  210. else
  211. reg_val = chip->reg_output[off / BANK_SZ]
  212. & ~(1u << (off % BANK_SZ));
  213. switch (chip->chip_type) {
  214. case PCA953X_TYPE:
  215. offset = PCA953X_OUTPUT;
  216. break;
  217. case PCA957X_TYPE:
  218. offset = PCA957X_OUT;
  219. break;
  220. }
  221. ret = pca953x_write_single(chip, offset, reg_val, off);
  222. if (ret)
  223. goto exit;
  224. chip->reg_output[off / BANK_SZ] = reg_val;
  225. /* then direction */
  226. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  227. switch (chip->chip_type) {
  228. case PCA953X_TYPE:
  229. offset = PCA953X_DIRECTION;
  230. break;
  231. case PCA957X_TYPE:
  232. offset = PCA957X_CFG;
  233. break;
  234. }
  235. ret = pca953x_write_single(chip, offset, reg_val, off);
  236. if (ret)
  237. goto exit;
  238. chip->reg_direction[off / BANK_SZ] = reg_val;
  239. ret = 0;
  240. exit:
  241. mutex_unlock(&chip->i2c_lock);
  242. return ret;
  243. }
  244. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  245. {
  246. struct pca953x_chip *chip = to_pca(gc);
  247. u32 reg_val;
  248. int ret, offset = 0;
  249. mutex_lock(&chip->i2c_lock);
  250. switch (chip->chip_type) {
  251. case PCA953X_TYPE:
  252. offset = PCA953X_INPUT;
  253. break;
  254. case PCA957X_TYPE:
  255. offset = PCA957X_IN;
  256. break;
  257. }
  258. ret = pca953x_read_single(chip, offset, &reg_val, off);
  259. mutex_unlock(&chip->i2c_lock);
  260. if (ret < 0) {
  261. /* NOTE: diagnostic already emitted; that's all we should
  262. * do unless gpio_*_value_cansleep() calls become different
  263. * from their nonsleeping siblings (and report faults).
  264. */
  265. return 0;
  266. }
  267. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  268. }
  269. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  270. {
  271. struct pca953x_chip *chip = to_pca(gc);
  272. u8 reg_val;
  273. int ret, offset = 0;
  274. mutex_lock(&chip->i2c_lock);
  275. if (val)
  276. reg_val = chip->reg_output[off / BANK_SZ]
  277. | (1u << (off % BANK_SZ));
  278. else
  279. reg_val = chip->reg_output[off / BANK_SZ]
  280. & ~(1u << (off % BANK_SZ));
  281. switch (chip->chip_type) {
  282. case PCA953X_TYPE:
  283. offset = PCA953X_OUTPUT;
  284. break;
  285. case PCA957X_TYPE:
  286. offset = PCA957X_OUT;
  287. break;
  288. }
  289. ret = pca953x_write_single(chip, offset, reg_val, off);
  290. if (ret)
  291. goto exit;
  292. chip->reg_output[off / BANK_SZ] = reg_val;
  293. exit:
  294. mutex_unlock(&chip->i2c_lock);
  295. }
  296. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  297. {
  298. struct gpio_chip *gc;
  299. gc = &chip->gpio_chip;
  300. gc->direction_input = pca953x_gpio_direction_input;
  301. gc->direction_output = pca953x_gpio_direction_output;
  302. gc->get = pca953x_gpio_get_value;
  303. gc->set = pca953x_gpio_set_value;
  304. gc->can_sleep = true;
  305. gc->base = chip->gpio_start;
  306. gc->ngpio = gpios;
  307. gc->label = chip->client->name;
  308. gc->dev = &chip->client->dev;
  309. gc->owner = THIS_MODULE;
  310. gc->names = chip->names;
  311. }
  312. #ifdef CONFIG_GPIO_PCA953X_IRQ
  313. static void pca953x_irq_mask(struct irq_data *d)
  314. {
  315. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  316. struct pca953x_chip *chip = to_pca(gc);
  317. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  318. }
  319. static void pca953x_irq_unmask(struct irq_data *d)
  320. {
  321. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  322. struct pca953x_chip *chip = to_pca(gc);
  323. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  324. }
  325. static void pca953x_irq_bus_lock(struct irq_data *d)
  326. {
  327. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  328. struct pca953x_chip *chip = to_pca(gc);
  329. mutex_lock(&chip->irq_lock);
  330. }
  331. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  332. {
  333. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  334. struct pca953x_chip *chip = to_pca(gc);
  335. u8 new_irqs;
  336. int level, i;
  337. /* Look for any newly setup interrupt */
  338. for (i = 0; i < NBANK(chip); i++) {
  339. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  340. new_irqs &= ~chip->reg_direction[i];
  341. while (new_irqs) {
  342. level = __ffs(new_irqs);
  343. pca953x_gpio_direction_input(&chip->gpio_chip,
  344. level + (BANK_SZ * i));
  345. new_irqs &= ~(1 << level);
  346. }
  347. }
  348. mutex_unlock(&chip->irq_lock);
  349. }
  350. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  351. {
  352. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  353. struct pca953x_chip *chip = to_pca(gc);
  354. int bank_nb = d->hwirq / BANK_SZ;
  355. u8 mask = 1 << (d->hwirq % BANK_SZ);
  356. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  357. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  358. d->irq, type);
  359. return -EINVAL;
  360. }
  361. if (type & IRQ_TYPE_EDGE_FALLING)
  362. chip->irq_trig_fall[bank_nb] |= mask;
  363. else
  364. chip->irq_trig_fall[bank_nb] &= ~mask;
  365. if (type & IRQ_TYPE_EDGE_RISING)
  366. chip->irq_trig_raise[bank_nb] |= mask;
  367. else
  368. chip->irq_trig_raise[bank_nb] &= ~mask;
  369. return 0;
  370. }
  371. static struct irq_chip pca953x_irq_chip = {
  372. .name = "pca953x",
  373. .irq_mask = pca953x_irq_mask,
  374. .irq_unmask = pca953x_irq_unmask,
  375. .irq_bus_lock = pca953x_irq_bus_lock,
  376. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  377. .irq_set_type = pca953x_irq_set_type,
  378. };
  379. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  380. {
  381. u8 cur_stat[MAX_BANK];
  382. u8 old_stat[MAX_BANK];
  383. bool pending_seen = false;
  384. bool trigger_seen = false;
  385. u8 trigger[MAX_BANK];
  386. int ret, i, offset = 0;
  387. switch (chip->chip_type) {
  388. case PCA953X_TYPE:
  389. offset = PCA953X_INPUT;
  390. break;
  391. case PCA957X_TYPE:
  392. offset = PCA957X_IN;
  393. break;
  394. }
  395. ret = pca953x_read_regs(chip, offset, cur_stat);
  396. if (ret)
  397. return false;
  398. /* Remove output pins from the equation */
  399. for (i = 0; i < NBANK(chip); i++)
  400. cur_stat[i] &= chip->reg_direction[i];
  401. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  402. for (i = 0; i < NBANK(chip); i++) {
  403. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  404. if (trigger[i])
  405. trigger_seen = true;
  406. }
  407. if (!trigger_seen)
  408. return false;
  409. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  410. for (i = 0; i < NBANK(chip); i++) {
  411. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  412. (cur_stat[i] & chip->irq_trig_raise[i]);
  413. pending[i] &= trigger[i];
  414. if (pending[i])
  415. pending_seen = true;
  416. }
  417. return pending_seen;
  418. }
  419. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  420. {
  421. struct pca953x_chip *chip = devid;
  422. u8 pending[MAX_BANK];
  423. u8 level;
  424. unsigned nhandled = 0;
  425. int i;
  426. if (!pca953x_irq_pending(chip, pending))
  427. return IRQ_NONE;
  428. for (i = 0; i < NBANK(chip); i++) {
  429. while (pending[i]) {
  430. level = __ffs(pending[i]);
  431. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  432. level + (BANK_SZ * i)));
  433. pending[i] &= ~(1 << level);
  434. nhandled++;
  435. }
  436. }
  437. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  438. }
  439. static int pca953x_irq_setup(struct pca953x_chip *chip,
  440. const struct i2c_device_id *id,
  441. int irq_base)
  442. {
  443. struct i2c_client *client = chip->client;
  444. int ret, i, offset = 0;
  445. if (client->irq && irq_base != -1
  446. && (id->driver_data & PCA_INT)) {
  447. switch (chip->chip_type) {
  448. case PCA953X_TYPE:
  449. offset = PCA953X_INPUT;
  450. break;
  451. case PCA957X_TYPE:
  452. offset = PCA957X_IN;
  453. break;
  454. }
  455. ret = pca953x_read_regs(chip, offset, chip->irq_stat);
  456. if (ret)
  457. return ret;
  458. /*
  459. * There is no way to know which GPIO line generated the
  460. * interrupt. We have to rely on the previous read for
  461. * this purpose.
  462. */
  463. for (i = 0; i < NBANK(chip); i++)
  464. chip->irq_stat[i] &= chip->reg_direction[i];
  465. mutex_init(&chip->irq_lock);
  466. ret = devm_request_threaded_irq(&client->dev,
  467. client->irq,
  468. NULL,
  469. pca953x_irq_handler,
  470. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  471. IRQF_SHARED,
  472. dev_name(&client->dev), chip);
  473. if (ret) {
  474. dev_err(&client->dev, "failed to request irq %d\n",
  475. client->irq);
  476. return ret;
  477. }
  478. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  479. &pca953x_irq_chip,
  480. irq_base,
  481. handle_simple_irq,
  482. IRQ_TYPE_NONE);
  483. if (ret) {
  484. dev_err(&client->dev,
  485. "could not connect irqchip to gpiochip\n");
  486. return ret;
  487. }
  488. }
  489. return 0;
  490. }
  491. #else /* CONFIG_GPIO_PCA953X_IRQ */
  492. static int pca953x_irq_setup(struct pca953x_chip *chip,
  493. const struct i2c_device_id *id,
  494. int irq_base)
  495. {
  496. struct i2c_client *client = chip->client;
  497. if (irq_base != -1 && (id->driver_data & PCA_INT))
  498. dev_warn(&client->dev, "interrupt support not compiled in\n");
  499. return 0;
  500. }
  501. #endif
  502. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  503. {
  504. int ret;
  505. u8 val[MAX_BANK];
  506. ret = pca953x_read_regs(chip, PCA953X_OUTPUT, chip->reg_output);
  507. if (ret)
  508. goto out;
  509. ret = pca953x_read_regs(chip, PCA953X_DIRECTION,
  510. chip->reg_direction);
  511. if (ret)
  512. goto out;
  513. /* set platform specific polarity inversion */
  514. if (invert)
  515. memset(val, 0xFF, NBANK(chip));
  516. else
  517. memset(val, 0, NBANK(chip));
  518. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  519. out:
  520. return ret;
  521. }
  522. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  523. {
  524. int ret;
  525. u8 val[MAX_BANK];
  526. ret = pca953x_read_regs(chip, PCA957X_OUT, chip->reg_output);
  527. if (ret)
  528. goto out;
  529. ret = pca953x_read_regs(chip, PCA957X_CFG, chip->reg_direction);
  530. if (ret)
  531. goto out;
  532. /* set platform specific polarity inversion */
  533. if (invert)
  534. memset(val, 0xFF, NBANK(chip));
  535. else
  536. memset(val, 0, NBANK(chip));
  537. pca953x_write_regs(chip, PCA957X_INVRT, val);
  538. /* To enable register 6, 7 to control pull up and pull down */
  539. memset(val, 0x02, NBANK(chip));
  540. pca953x_write_regs(chip, PCA957X_BKEN, val);
  541. return 0;
  542. out:
  543. return ret;
  544. }
  545. static int pca953x_probe(struct i2c_client *client,
  546. const struct i2c_device_id *id)
  547. {
  548. struct pca953x_platform_data *pdata;
  549. struct pca953x_chip *chip;
  550. int irq_base = 0;
  551. int ret;
  552. u32 invert = 0;
  553. chip = devm_kzalloc(&client->dev,
  554. sizeof(struct pca953x_chip), GFP_KERNEL);
  555. if (chip == NULL)
  556. return -ENOMEM;
  557. pdata = dev_get_platdata(&client->dev);
  558. if (pdata) {
  559. irq_base = pdata->irq_base;
  560. chip->gpio_start = pdata->gpio_base;
  561. invert = pdata->invert;
  562. chip->names = pdata->names;
  563. } else {
  564. chip->gpio_start = -1;
  565. irq_base = 0;
  566. }
  567. chip->client = client;
  568. chip->chip_type = id->driver_data & (PCA953X_TYPE | PCA957X_TYPE);
  569. mutex_init(&chip->i2c_lock);
  570. /* initialize cached registers from their original values.
  571. * we can't share this chip with another i2c master.
  572. */
  573. pca953x_setup_gpio(chip, id->driver_data & PCA_GPIO_MASK);
  574. if (chip->chip_type == PCA953X_TYPE)
  575. ret = device_pca953x_init(chip, invert);
  576. else
  577. ret = device_pca957x_init(chip, invert);
  578. if (ret)
  579. return ret;
  580. ret = gpiochip_add(&chip->gpio_chip);
  581. if (ret)
  582. return ret;
  583. ret = pca953x_irq_setup(chip, id, irq_base);
  584. if (ret)
  585. return ret;
  586. if (pdata && pdata->setup) {
  587. ret = pdata->setup(client, chip->gpio_chip.base,
  588. chip->gpio_chip.ngpio, pdata->context);
  589. if (ret < 0)
  590. dev_warn(&client->dev, "setup failed, %d\n", ret);
  591. }
  592. i2c_set_clientdata(client, chip);
  593. return 0;
  594. }
  595. static int pca953x_remove(struct i2c_client *client)
  596. {
  597. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  598. struct pca953x_chip *chip = i2c_get_clientdata(client);
  599. int ret = 0;
  600. if (pdata && pdata->teardown) {
  601. ret = pdata->teardown(client, chip->gpio_chip.base,
  602. chip->gpio_chip.ngpio, pdata->context);
  603. if (ret < 0) {
  604. dev_err(&client->dev, "%s failed, %d\n",
  605. "teardown", ret);
  606. return ret;
  607. }
  608. }
  609. gpiochip_remove(&chip->gpio_chip);
  610. return 0;
  611. }
  612. static const struct of_device_id pca953x_dt_ids[] = {
  613. { .compatible = "nxp,pca9505", },
  614. { .compatible = "nxp,pca9534", },
  615. { .compatible = "nxp,pca9535", },
  616. { .compatible = "nxp,pca9536", },
  617. { .compatible = "nxp,pca9537", },
  618. { .compatible = "nxp,pca9538", },
  619. { .compatible = "nxp,pca9539", },
  620. { .compatible = "nxp,pca9554", },
  621. { .compatible = "nxp,pca9555", },
  622. { .compatible = "nxp,pca9556", },
  623. { .compatible = "nxp,pca9557", },
  624. { .compatible = "nxp,pca9574", },
  625. { .compatible = "nxp,pca9575", },
  626. { .compatible = "nxp,pca9698", },
  627. { .compatible = "maxim,max7310", },
  628. { .compatible = "maxim,max7312", },
  629. { .compatible = "maxim,max7313", },
  630. { .compatible = "maxim,max7315", },
  631. { .compatible = "ti,pca6107", },
  632. { .compatible = "ti,tca6408", },
  633. { .compatible = "ti,tca6416", },
  634. { .compatible = "ti,tca6424", },
  635. { .compatible = "exar,xra1202", },
  636. { }
  637. };
  638. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  639. static struct i2c_driver pca953x_driver = {
  640. .driver = {
  641. .name = "pca953x",
  642. .of_match_table = pca953x_dt_ids,
  643. },
  644. .probe = pca953x_probe,
  645. .remove = pca953x_remove,
  646. .id_table = pca953x_id,
  647. };
  648. static int __init pca953x_init(void)
  649. {
  650. return i2c_add_driver(&pca953x_driver);
  651. }
  652. /* register after i2c postcore initcall and before
  653. * subsys initcalls that may rely on these GPIOs
  654. */
  655. subsys_initcall(pca953x_init);
  656. static void __exit pca953x_exit(void)
  657. {
  658. i2c_del_driver(&pca953x_driver);
  659. }
  660. module_exit(pca953x_exit);
  661. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  662. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  663. MODULE_LICENSE("GPL");