nvme-core.c 81 KB

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  1. /*
  2. * NVM Express device driver
  3. * Copyright (c) 2011-2014, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. */
  14. #include <linux/nvme.h>
  15. #include <linux/bitops.h>
  16. #include <linux/blkdev.h>
  17. #include <linux/blk-mq.h>
  18. #include <linux/cpu.h>
  19. #include <linux/delay.h>
  20. #include <linux/errno.h>
  21. #include <linux/fs.h>
  22. #include <linux/genhd.h>
  23. #include <linux/hdreg.h>
  24. #include <linux/idr.h>
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/io.h>
  28. #include <linux/kdev_t.h>
  29. #include <linux/kthread.h>
  30. #include <linux/kernel.h>
  31. #include <linux/list_sort.h>
  32. #include <linux/mm.h>
  33. #include <linux/module.h>
  34. #include <linux/moduleparam.h>
  35. #include <linux/pci.h>
  36. #include <linux/poison.h>
  37. #include <linux/ptrace.h>
  38. #include <linux/sched.h>
  39. #include <linux/slab.h>
  40. #include <linux/t10-pi.h>
  41. #include <linux/types.h>
  42. #include <scsi/sg.h>
  43. #include <asm-generic/io-64-nonatomic-lo-hi.h>
  44. #define NVME_MINORS (1U << MINORBITS)
  45. #define NVME_Q_DEPTH 1024
  46. #define NVME_AQ_DEPTH 256
  47. #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
  48. #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
  49. #define ADMIN_TIMEOUT (admin_timeout * HZ)
  50. #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
  51. static unsigned char admin_timeout = 60;
  52. module_param(admin_timeout, byte, 0644);
  53. MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
  54. unsigned char nvme_io_timeout = 30;
  55. module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
  56. MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
  57. static unsigned char shutdown_timeout = 5;
  58. module_param(shutdown_timeout, byte, 0644);
  59. MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
  60. static int nvme_major;
  61. module_param(nvme_major, int, 0);
  62. static int nvme_char_major;
  63. module_param(nvme_char_major, int, 0);
  64. static int use_threaded_interrupts;
  65. module_param(use_threaded_interrupts, int, 0);
  66. static DEFINE_SPINLOCK(dev_list_lock);
  67. static LIST_HEAD(dev_list);
  68. static struct task_struct *nvme_thread;
  69. static struct workqueue_struct *nvme_workq;
  70. static wait_queue_head_t nvme_kthread_wait;
  71. static struct class *nvme_class;
  72. static void nvme_reset_failed_dev(struct work_struct *ws);
  73. static int nvme_reset(struct nvme_dev *dev);
  74. static int nvme_process_cq(struct nvme_queue *nvmeq);
  75. struct async_cmd_info {
  76. struct kthread_work work;
  77. struct kthread_worker *worker;
  78. struct request *req;
  79. u32 result;
  80. int status;
  81. void *ctx;
  82. };
  83. /*
  84. * An NVM Express queue. Each device has at least two (one for admin
  85. * commands and one for I/O commands).
  86. */
  87. struct nvme_queue {
  88. struct device *q_dmadev;
  89. struct nvme_dev *dev;
  90. char irqname[24]; /* nvme4294967295-65535\0 */
  91. spinlock_t q_lock;
  92. struct nvme_command *sq_cmds;
  93. volatile struct nvme_completion *cqes;
  94. struct blk_mq_tags **tags;
  95. dma_addr_t sq_dma_addr;
  96. dma_addr_t cq_dma_addr;
  97. u32 __iomem *q_db;
  98. u16 q_depth;
  99. s16 cq_vector;
  100. u16 sq_head;
  101. u16 sq_tail;
  102. u16 cq_head;
  103. u16 qid;
  104. u8 cq_phase;
  105. u8 cqe_seen;
  106. struct async_cmd_info cmdinfo;
  107. };
  108. /*
  109. * Check we didin't inadvertently grow the command struct
  110. */
  111. static inline void _nvme_check_size(void)
  112. {
  113. BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
  114. BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
  115. BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
  116. BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
  117. BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
  118. BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
  119. BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
  120. BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
  121. BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
  122. BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
  123. BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
  124. BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
  125. }
  126. typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
  127. struct nvme_completion *);
  128. struct nvme_cmd_info {
  129. nvme_completion_fn fn;
  130. void *ctx;
  131. int aborted;
  132. struct nvme_queue *nvmeq;
  133. struct nvme_iod iod[0];
  134. };
  135. /*
  136. * Max size of iod being embedded in the request payload
  137. */
  138. #define NVME_INT_PAGES 2
  139. #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
  140. #define NVME_INT_MASK 0x01
  141. /*
  142. * Will slightly overestimate the number of pages needed. This is OK
  143. * as it only leads to a small amount of wasted memory for the lifetime of
  144. * the I/O.
  145. */
  146. static int nvme_npages(unsigned size, struct nvme_dev *dev)
  147. {
  148. unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
  149. return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
  150. }
  151. static unsigned int nvme_cmd_size(struct nvme_dev *dev)
  152. {
  153. unsigned int ret = sizeof(struct nvme_cmd_info);
  154. ret += sizeof(struct nvme_iod);
  155. ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
  156. ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
  157. return ret;
  158. }
  159. static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  160. unsigned int hctx_idx)
  161. {
  162. struct nvme_dev *dev = data;
  163. struct nvme_queue *nvmeq = dev->queues[0];
  164. WARN_ON(hctx_idx != 0);
  165. WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
  166. WARN_ON(nvmeq->tags);
  167. hctx->driver_data = nvmeq;
  168. nvmeq->tags = &dev->admin_tagset.tags[0];
  169. return 0;
  170. }
  171. static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
  172. {
  173. struct nvme_queue *nvmeq = hctx->driver_data;
  174. nvmeq->tags = NULL;
  175. }
  176. static int nvme_admin_init_request(void *data, struct request *req,
  177. unsigned int hctx_idx, unsigned int rq_idx,
  178. unsigned int numa_node)
  179. {
  180. struct nvme_dev *dev = data;
  181. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  182. struct nvme_queue *nvmeq = dev->queues[0];
  183. BUG_ON(!nvmeq);
  184. cmd->nvmeq = nvmeq;
  185. return 0;
  186. }
  187. static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
  188. unsigned int hctx_idx)
  189. {
  190. struct nvme_dev *dev = data;
  191. struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
  192. if (!nvmeq->tags)
  193. nvmeq->tags = &dev->tagset.tags[hctx_idx];
  194. WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
  195. hctx->driver_data = nvmeq;
  196. return 0;
  197. }
  198. static int nvme_init_request(void *data, struct request *req,
  199. unsigned int hctx_idx, unsigned int rq_idx,
  200. unsigned int numa_node)
  201. {
  202. struct nvme_dev *dev = data;
  203. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  204. struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
  205. BUG_ON(!nvmeq);
  206. cmd->nvmeq = nvmeq;
  207. return 0;
  208. }
  209. static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
  210. nvme_completion_fn handler)
  211. {
  212. cmd->fn = handler;
  213. cmd->ctx = ctx;
  214. cmd->aborted = 0;
  215. blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
  216. }
  217. static void *iod_get_private(struct nvme_iod *iod)
  218. {
  219. return (void *) (iod->private & ~0x1UL);
  220. }
  221. /*
  222. * If bit 0 is set, the iod is embedded in the request payload.
  223. */
  224. static bool iod_should_kfree(struct nvme_iod *iod)
  225. {
  226. return (iod->private & NVME_INT_MASK) == 0;
  227. }
  228. /* Special values must be less than 0x1000 */
  229. #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
  230. #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
  231. #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
  232. #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
  233. static void special_completion(struct nvme_queue *nvmeq, void *ctx,
  234. struct nvme_completion *cqe)
  235. {
  236. if (ctx == CMD_CTX_CANCELLED)
  237. return;
  238. if (ctx == CMD_CTX_COMPLETED) {
  239. dev_warn(nvmeq->q_dmadev,
  240. "completed id %d twice on queue %d\n",
  241. cqe->command_id, le16_to_cpup(&cqe->sq_id));
  242. return;
  243. }
  244. if (ctx == CMD_CTX_INVALID) {
  245. dev_warn(nvmeq->q_dmadev,
  246. "invalid id %d completed on queue %d\n",
  247. cqe->command_id, le16_to_cpup(&cqe->sq_id));
  248. return;
  249. }
  250. dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
  251. }
  252. static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
  253. {
  254. void *ctx;
  255. if (fn)
  256. *fn = cmd->fn;
  257. ctx = cmd->ctx;
  258. cmd->fn = special_completion;
  259. cmd->ctx = CMD_CTX_CANCELLED;
  260. return ctx;
  261. }
  262. static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
  263. struct nvme_completion *cqe)
  264. {
  265. u32 result = le32_to_cpup(&cqe->result);
  266. u16 status = le16_to_cpup(&cqe->status) >> 1;
  267. if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
  268. ++nvmeq->dev->event_limit;
  269. if (status != NVME_SC_SUCCESS)
  270. return;
  271. switch (result & 0xff07) {
  272. case NVME_AER_NOTICE_NS_CHANGED:
  273. dev_info(nvmeq->q_dmadev, "rescanning\n");
  274. schedule_work(&nvmeq->dev->scan_work);
  275. default:
  276. dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
  277. }
  278. }
  279. static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
  280. struct nvme_completion *cqe)
  281. {
  282. struct request *req = ctx;
  283. u16 status = le16_to_cpup(&cqe->status) >> 1;
  284. u32 result = le32_to_cpup(&cqe->result);
  285. blk_mq_free_request(req);
  286. dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
  287. ++nvmeq->dev->abort_limit;
  288. }
  289. static void async_completion(struct nvme_queue *nvmeq, void *ctx,
  290. struct nvme_completion *cqe)
  291. {
  292. struct async_cmd_info *cmdinfo = ctx;
  293. cmdinfo->result = le32_to_cpup(&cqe->result);
  294. cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
  295. queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
  296. blk_mq_free_request(cmdinfo->req);
  297. }
  298. static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
  299. unsigned int tag)
  300. {
  301. struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
  302. return blk_mq_rq_to_pdu(req);
  303. }
  304. /*
  305. * Called with local interrupts disabled and the q_lock held. May not sleep.
  306. */
  307. static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
  308. nvme_completion_fn *fn)
  309. {
  310. struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
  311. void *ctx;
  312. if (tag >= nvmeq->q_depth) {
  313. *fn = special_completion;
  314. return CMD_CTX_INVALID;
  315. }
  316. if (fn)
  317. *fn = cmd->fn;
  318. ctx = cmd->ctx;
  319. cmd->fn = special_completion;
  320. cmd->ctx = CMD_CTX_COMPLETED;
  321. return ctx;
  322. }
  323. /**
  324. * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
  325. * @nvmeq: The queue to use
  326. * @cmd: The command to send
  327. *
  328. * Safe to use from interrupt context
  329. */
  330. static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
  331. {
  332. u16 tail = nvmeq->sq_tail;
  333. memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
  334. if (++tail == nvmeq->q_depth)
  335. tail = 0;
  336. writel(tail, nvmeq->q_db);
  337. nvmeq->sq_tail = tail;
  338. return 0;
  339. }
  340. static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
  341. {
  342. unsigned long flags;
  343. int ret;
  344. spin_lock_irqsave(&nvmeq->q_lock, flags);
  345. ret = __nvme_submit_cmd(nvmeq, cmd);
  346. spin_unlock_irqrestore(&nvmeq->q_lock, flags);
  347. return ret;
  348. }
  349. static __le64 **iod_list(struct nvme_iod *iod)
  350. {
  351. return ((void *)iod) + iod->offset;
  352. }
  353. static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
  354. unsigned nseg, unsigned long private)
  355. {
  356. iod->private = private;
  357. iod->offset = offsetof(struct nvme_iod, sg[nseg]);
  358. iod->npages = -1;
  359. iod->length = nbytes;
  360. iod->nents = 0;
  361. }
  362. static struct nvme_iod *
  363. __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
  364. unsigned long priv, gfp_t gfp)
  365. {
  366. struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
  367. sizeof(__le64 *) * nvme_npages(bytes, dev) +
  368. sizeof(struct scatterlist) * nseg, gfp);
  369. if (iod)
  370. iod_init(iod, bytes, nseg, priv);
  371. return iod;
  372. }
  373. static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
  374. gfp_t gfp)
  375. {
  376. unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
  377. sizeof(struct nvme_dsm_range);
  378. struct nvme_iod *iod;
  379. if (rq->nr_phys_segments <= NVME_INT_PAGES &&
  380. size <= NVME_INT_BYTES(dev)) {
  381. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
  382. iod = cmd->iod;
  383. iod_init(iod, size, rq->nr_phys_segments,
  384. (unsigned long) rq | NVME_INT_MASK);
  385. return iod;
  386. }
  387. return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
  388. (unsigned long) rq, gfp);
  389. }
  390. static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
  391. {
  392. const int last_prp = dev->page_size / 8 - 1;
  393. int i;
  394. __le64 **list = iod_list(iod);
  395. dma_addr_t prp_dma = iod->first_dma;
  396. if (iod->npages == 0)
  397. dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
  398. for (i = 0; i < iod->npages; i++) {
  399. __le64 *prp_list = list[i];
  400. dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
  401. dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
  402. prp_dma = next_prp_dma;
  403. }
  404. if (iod_should_kfree(iod))
  405. kfree(iod);
  406. }
  407. static int nvme_error_status(u16 status)
  408. {
  409. switch (status & 0x7ff) {
  410. case NVME_SC_SUCCESS:
  411. return 0;
  412. case NVME_SC_CAP_EXCEEDED:
  413. return -ENOSPC;
  414. default:
  415. return -EIO;
  416. }
  417. }
  418. #ifdef CONFIG_BLK_DEV_INTEGRITY
  419. static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
  420. {
  421. if (be32_to_cpu(pi->ref_tag) == v)
  422. pi->ref_tag = cpu_to_be32(p);
  423. }
  424. static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
  425. {
  426. if (be32_to_cpu(pi->ref_tag) == p)
  427. pi->ref_tag = cpu_to_be32(v);
  428. }
  429. /**
  430. * nvme_dif_remap - remaps ref tags to bip seed and physical lba
  431. *
  432. * The virtual start sector is the one that was originally submitted by the
  433. * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
  434. * start sector may be different. Remap protection information to match the
  435. * physical LBA on writes, and back to the original seed on reads.
  436. *
  437. * Type 0 and 3 do not have a ref tag, so no remapping required.
  438. */
  439. static void nvme_dif_remap(struct request *req,
  440. void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
  441. {
  442. struct nvme_ns *ns = req->rq_disk->private_data;
  443. struct bio_integrity_payload *bip;
  444. struct t10_pi_tuple *pi;
  445. void *p, *pmap;
  446. u32 i, nlb, ts, phys, virt;
  447. if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
  448. return;
  449. bip = bio_integrity(req->bio);
  450. if (!bip)
  451. return;
  452. pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
  453. p = pmap;
  454. virt = bip_get_seed(bip);
  455. phys = nvme_block_nr(ns, blk_rq_pos(req));
  456. nlb = (blk_rq_bytes(req) >> ns->lba_shift);
  457. ts = ns->disk->integrity->tuple_size;
  458. for (i = 0; i < nlb; i++, virt++, phys++) {
  459. pi = (struct t10_pi_tuple *)p;
  460. dif_swap(phys, virt, pi);
  461. p += ts;
  462. }
  463. kunmap_atomic(pmap);
  464. }
  465. static int nvme_noop_verify(struct blk_integrity_iter *iter)
  466. {
  467. return 0;
  468. }
  469. static int nvme_noop_generate(struct blk_integrity_iter *iter)
  470. {
  471. return 0;
  472. }
  473. struct blk_integrity nvme_meta_noop = {
  474. .name = "NVME_META_NOOP",
  475. .generate_fn = nvme_noop_generate,
  476. .verify_fn = nvme_noop_verify,
  477. };
  478. static void nvme_init_integrity(struct nvme_ns *ns)
  479. {
  480. struct blk_integrity integrity;
  481. switch (ns->pi_type) {
  482. case NVME_NS_DPS_PI_TYPE3:
  483. integrity = t10_pi_type3_crc;
  484. break;
  485. case NVME_NS_DPS_PI_TYPE1:
  486. case NVME_NS_DPS_PI_TYPE2:
  487. integrity = t10_pi_type1_crc;
  488. break;
  489. default:
  490. integrity = nvme_meta_noop;
  491. break;
  492. }
  493. integrity.tuple_size = ns->ms;
  494. blk_integrity_register(ns->disk, &integrity);
  495. blk_queue_max_integrity_segments(ns->queue, 1);
  496. }
  497. #else /* CONFIG_BLK_DEV_INTEGRITY */
  498. static void nvme_dif_remap(struct request *req,
  499. void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
  500. {
  501. }
  502. static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
  503. {
  504. }
  505. static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
  506. {
  507. }
  508. static void nvme_init_integrity(struct nvme_ns *ns)
  509. {
  510. }
  511. #endif
  512. static void req_completion(struct nvme_queue *nvmeq, void *ctx,
  513. struct nvme_completion *cqe)
  514. {
  515. struct nvme_iod *iod = ctx;
  516. struct request *req = iod_get_private(iod);
  517. struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
  518. u16 status = le16_to_cpup(&cqe->status) >> 1;
  519. if (unlikely(status)) {
  520. if (!(status & NVME_SC_DNR || blk_noretry_request(req))
  521. && (jiffies - req->start_time) < req->timeout) {
  522. unsigned long flags;
  523. blk_mq_requeue_request(req);
  524. spin_lock_irqsave(req->q->queue_lock, flags);
  525. if (!blk_queue_stopped(req->q))
  526. blk_mq_kick_requeue_list(req->q);
  527. spin_unlock_irqrestore(req->q->queue_lock, flags);
  528. return;
  529. }
  530. if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
  531. if (cmd_rq->ctx == CMD_CTX_CANCELLED)
  532. req->errors = -EINTR;
  533. else
  534. req->errors = status;
  535. } else {
  536. req->errors = nvme_error_status(status);
  537. }
  538. } else
  539. req->errors = 0;
  540. if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
  541. u32 result = le32_to_cpup(&cqe->result);
  542. req->special = (void *)(uintptr_t)result;
  543. }
  544. if (cmd_rq->aborted)
  545. dev_warn(nvmeq->dev->dev,
  546. "completing aborted command with status:%04x\n",
  547. status);
  548. if (iod->nents) {
  549. dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
  550. rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  551. if (blk_integrity_rq(req)) {
  552. if (!rq_data_dir(req))
  553. nvme_dif_remap(req, nvme_dif_complete);
  554. dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
  555. rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  556. }
  557. }
  558. nvme_free_iod(nvmeq->dev, iod);
  559. blk_mq_complete_request(req);
  560. }
  561. /* length is in bytes. gfp flags indicates whether we may sleep. */
  562. static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
  563. int total_len, gfp_t gfp)
  564. {
  565. struct dma_pool *pool;
  566. int length = total_len;
  567. struct scatterlist *sg = iod->sg;
  568. int dma_len = sg_dma_len(sg);
  569. u64 dma_addr = sg_dma_address(sg);
  570. u32 page_size = dev->page_size;
  571. int offset = dma_addr & (page_size - 1);
  572. __le64 *prp_list;
  573. __le64 **list = iod_list(iod);
  574. dma_addr_t prp_dma;
  575. int nprps, i;
  576. length -= (page_size - offset);
  577. if (length <= 0)
  578. return total_len;
  579. dma_len -= (page_size - offset);
  580. if (dma_len) {
  581. dma_addr += (page_size - offset);
  582. } else {
  583. sg = sg_next(sg);
  584. dma_addr = sg_dma_address(sg);
  585. dma_len = sg_dma_len(sg);
  586. }
  587. if (length <= page_size) {
  588. iod->first_dma = dma_addr;
  589. return total_len;
  590. }
  591. nprps = DIV_ROUND_UP(length, page_size);
  592. if (nprps <= (256 / 8)) {
  593. pool = dev->prp_small_pool;
  594. iod->npages = 0;
  595. } else {
  596. pool = dev->prp_page_pool;
  597. iod->npages = 1;
  598. }
  599. prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
  600. if (!prp_list) {
  601. iod->first_dma = dma_addr;
  602. iod->npages = -1;
  603. return (total_len - length) + page_size;
  604. }
  605. list[0] = prp_list;
  606. iod->first_dma = prp_dma;
  607. i = 0;
  608. for (;;) {
  609. if (i == page_size >> 3) {
  610. __le64 *old_prp_list = prp_list;
  611. prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
  612. if (!prp_list)
  613. return total_len - length;
  614. list[iod->npages++] = prp_list;
  615. prp_list[0] = old_prp_list[i - 1];
  616. old_prp_list[i - 1] = cpu_to_le64(prp_dma);
  617. i = 1;
  618. }
  619. prp_list[i++] = cpu_to_le64(dma_addr);
  620. dma_len -= page_size;
  621. dma_addr += page_size;
  622. length -= page_size;
  623. if (length <= 0)
  624. break;
  625. if (dma_len > 0)
  626. continue;
  627. BUG_ON(dma_len < 0);
  628. sg = sg_next(sg);
  629. dma_addr = sg_dma_address(sg);
  630. dma_len = sg_dma_len(sg);
  631. }
  632. return total_len;
  633. }
  634. static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
  635. struct nvme_iod *iod)
  636. {
  637. struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
  638. memcpy(cmnd, req->cmd, sizeof(struct nvme_command));
  639. cmnd->rw.command_id = req->tag;
  640. if (req->nr_phys_segments) {
  641. cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
  642. cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
  643. }
  644. if (++nvmeq->sq_tail == nvmeq->q_depth)
  645. nvmeq->sq_tail = 0;
  646. writel(nvmeq->sq_tail, nvmeq->q_db);
  647. }
  648. /*
  649. * We reuse the small pool to allocate the 16-byte range here as it is not
  650. * worth having a special pool for these or additional cases to handle freeing
  651. * the iod.
  652. */
  653. static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
  654. struct request *req, struct nvme_iod *iod)
  655. {
  656. struct nvme_dsm_range *range =
  657. (struct nvme_dsm_range *)iod_list(iod)[0];
  658. struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
  659. range->cattr = cpu_to_le32(0);
  660. range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
  661. range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
  662. memset(cmnd, 0, sizeof(*cmnd));
  663. cmnd->dsm.opcode = nvme_cmd_dsm;
  664. cmnd->dsm.command_id = req->tag;
  665. cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
  666. cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
  667. cmnd->dsm.nr = 0;
  668. cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
  669. if (++nvmeq->sq_tail == nvmeq->q_depth)
  670. nvmeq->sq_tail = 0;
  671. writel(nvmeq->sq_tail, nvmeq->q_db);
  672. }
  673. static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
  674. int cmdid)
  675. {
  676. struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
  677. memset(cmnd, 0, sizeof(*cmnd));
  678. cmnd->common.opcode = nvme_cmd_flush;
  679. cmnd->common.command_id = cmdid;
  680. cmnd->common.nsid = cpu_to_le32(ns->ns_id);
  681. if (++nvmeq->sq_tail == nvmeq->q_depth)
  682. nvmeq->sq_tail = 0;
  683. writel(nvmeq->sq_tail, nvmeq->q_db);
  684. }
  685. static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
  686. struct nvme_ns *ns)
  687. {
  688. struct request *req = iod_get_private(iod);
  689. struct nvme_command *cmnd;
  690. u16 control = 0;
  691. u32 dsmgmt = 0;
  692. if (req->cmd_flags & REQ_FUA)
  693. control |= NVME_RW_FUA;
  694. if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
  695. control |= NVME_RW_LR;
  696. if (req->cmd_flags & REQ_RAHEAD)
  697. dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
  698. cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
  699. memset(cmnd, 0, sizeof(*cmnd));
  700. cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
  701. cmnd->rw.command_id = req->tag;
  702. cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
  703. cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
  704. cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
  705. cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
  706. cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
  707. if (blk_integrity_rq(req)) {
  708. cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg));
  709. switch (ns->pi_type) {
  710. case NVME_NS_DPS_PI_TYPE3:
  711. control |= NVME_RW_PRINFO_PRCHK_GUARD;
  712. break;
  713. case NVME_NS_DPS_PI_TYPE1:
  714. case NVME_NS_DPS_PI_TYPE2:
  715. control |= NVME_RW_PRINFO_PRCHK_GUARD |
  716. NVME_RW_PRINFO_PRCHK_REF;
  717. cmnd->rw.reftag = cpu_to_le32(
  718. nvme_block_nr(ns, blk_rq_pos(req)));
  719. break;
  720. }
  721. } else if (ns->ms)
  722. control |= NVME_RW_PRINFO_PRACT;
  723. cmnd->rw.control = cpu_to_le16(control);
  724. cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
  725. if (++nvmeq->sq_tail == nvmeq->q_depth)
  726. nvmeq->sq_tail = 0;
  727. writel(nvmeq->sq_tail, nvmeq->q_db);
  728. return 0;
  729. }
  730. /*
  731. * NOTE: ns is NULL when called on the admin queue.
  732. */
  733. static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
  734. const struct blk_mq_queue_data *bd)
  735. {
  736. struct nvme_ns *ns = hctx->queue->queuedata;
  737. struct nvme_queue *nvmeq = hctx->driver_data;
  738. struct nvme_dev *dev = nvmeq->dev;
  739. struct request *req = bd->rq;
  740. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  741. struct nvme_iod *iod;
  742. enum dma_data_direction dma_dir;
  743. /*
  744. * If formated with metadata, require the block layer provide a buffer
  745. * unless this namespace is formated such that the metadata can be
  746. * stripped/generated by the controller with PRACT=1.
  747. */
  748. if (ns && ns->ms && !blk_integrity_rq(req)) {
  749. if (!(ns->pi_type && ns->ms == 8) &&
  750. req->cmd_type != REQ_TYPE_DRV_PRIV) {
  751. req->errors = -EFAULT;
  752. blk_mq_complete_request(req);
  753. return BLK_MQ_RQ_QUEUE_OK;
  754. }
  755. }
  756. iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
  757. if (!iod)
  758. return BLK_MQ_RQ_QUEUE_BUSY;
  759. if (req->cmd_flags & REQ_DISCARD) {
  760. void *range;
  761. /*
  762. * We reuse the small pool to allocate the 16-byte range here
  763. * as it is not worth having a special pool for these or
  764. * additional cases to handle freeing the iod.
  765. */
  766. range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
  767. &iod->first_dma);
  768. if (!range)
  769. goto retry_cmd;
  770. iod_list(iod)[0] = (__le64 *)range;
  771. iod->npages = 0;
  772. } else if (req->nr_phys_segments) {
  773. dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  774. sg_init_table(iod->sg, req->nr_phys_segments);
  775. iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
  776. if (!iod->nents)
  777. goto error_cmd;
  778. if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
  779. goto retry_cmd;
  780. if (blk_rq_bytes(req) !=
  781. nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
  782. dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
  783. goto retry_cmd;
  784. }
  785. if (blk_integrity_rq(req)) {
  786. if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
  787. goto error_cmd;
  788. sg_init_table(iod->meta_sg, 1);
  789. if (blk_rq_map_integrity_sg(
  790. req->q, req->bio, iod->meta_sg) != 1)
  791. goto error_cmd;
  792. if (rq_data_dir(req))
  793. nvme_dif_remap(req, nvme_dif_prep);
  794. if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
  795. goto error_cmd;
  796. }
  797. }
  798. nvme_set_info(cmd, iod, req_completion);
  799. spin_lock_irq(&nvmeq->q_lock);
  800. if (req->cmd_type == REQ_TYPE_DRV_PRIV)
  801. nvme_submit_priv(nvmeq, req, iod);
  802. else if (req->cmd_flags & REQ_DISCARD)
  803. nvme_submit_discard(nvmeq, ns, req, iod);
  804. else if (req->cmd_flags & REQ_FLUSH)
  805. nvme_submit_flush(nvmeq, ns, req->tag);
  806. else
  807. nvme_submit_iod(nvmeq, iod, ns);
  808. nvme_process_cq(nvmeq);
  809. spin_unlock_irq(&nvmeq->q_lock);
  810. return BLK_MQ_RQ_QUEUE_OK;
  811. error_cmd:
  812. nvme_free_iod(dev, iod);
  813. return BLK_MQ_RQ_QUEUE_ERROR;
  814. retry_cmd:
  815. nvme_free_iod(dev, iod);
  816. return BLK_MQ_RQ_QUEUE_BUSY;
  817. }
  818. static int nvme_process_cq(struct nvme_queue *nvmeq)
  819. {
  820. u16 head, phase;
  821. head = nvmeq->cq_head;
  822. phase = nvmeq->cq_phase;
  823. for (;;) {
  824. void *ctx;
  825. nvme_completion_fn fn;
  826. struct nvme_completion cqe = nvmeq->cqes[head];
  827. if ((le16_to_cpu(cqe.status) & 1) != phase)
  828. break;
  829. nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
  830. if (++head == nvmeq->q_depth) {
  831. head = 0;
  832. phase = !phase;
  833. }
  834. ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
  835. fn(nvmeq, ctx, &cqe);
  836. }
  837. /* If the controller ignores the cq head doorbell and continuously
  838. * writes to the queue, it is theoretically possible to wrap around
  839. * the queue twice and mistakenly return IRQ_NONE. Linux only
  840. * requires that 0.1% of your interrupts are handled, so this isn't
  841. * a big problem.
  842. */
  843. if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
  844. return 0;
  845. writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
  846. nvmeq->cq_head = head;
  847. nvmeq->cq_phase = phase;
  848. nvmeq->cqe_seen = 1;
  849. return 1;
  850. }
  851. static irqreturn_t nvme_irq(int irq, void *data)
  852. {
  853. irqreturn_t result;
  854. struct nvme_queue *nvmeq = data;
  855. spin_lock(&nvmeq->q_lock);
  856. nvme_process_cq(nvmeq);
  857. result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
  858. nvmeq->cqe_seen = 0;
  859. spin_unlock(&nvmeq->q_lock);
  860. return result;
  861. }
  862. static irqreturn_t nvme_irq_check(int irq, void *data)
  863. {
  864. struct nvme_queue *nvmeq = data;
  865. struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
  866. if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
  867. return IRQ_NONE;
  868. return IRQ_WAKE_THREAD;
  869. }
  870. /*
  871. * Returns 0 on success. If the result is negative, it's a Linux error code;
  872. * if the result is positive, it's an NVM Express status code
  873. */
  874. int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
  875. void *buffer, void __user *ubuffer, unsigned bufflen,
  876. u32 *result, unsigned timeout)
  877. {
  878. bool write = cmd->common.opcode & 1;
  879. struct bio *bio = NULL;
  880. struct request *req;
  881. int ret;
  882. req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
  883. if (IS_ERR(req))
  884. return PTR_ERR(req);
  885. req->cmd_type = REQ_TYPE_DRV_PRIV;
  886. req->cmd_flags |= REQ_FAILFAST_DRIVER;
  887. req->__data_len = 0;
  888. req->__sector = (sector_t) -1;
  889. req->bio = req->biotail = NULL;
  890. req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
  891. req->cmd = (unsigned char *)cmd;
  892. req->cmd_len = sizeof(struct nvme_command);
  893. req->special = (void *)0;
  894. if (buffer && bufflen) {
  895. ret = blk_rq_map_kern(q, req, buffer, bufflen, __GFP_WAIT);
  896. if (ret)
  897. goto out;
  898. } else if (ubuffer && bufflen) {
  899. ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen, __GFP_WAIT);
  900. if (ret)
  901. goto out;
  902. bio = req->bio;
  903. }
  904. blk_execute_rq(req->q, NULL, req, 0);
  905. if (bio)
  906. blk_rq_unmap_user(bio);
  907. if (result)
  908. *result = (u32)(uintptr_t)req->special;
  909. ret = req->errors;
  910. out:
  911. blk_mq_free_request(req);
  912. return ret;
  913. }
  914. int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
  915. void *buffer, unsigned bufflen)
  916. {
  917. return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
  918. }
  919. static int nvme_submit_async_admin_req(struct nvme_dev *dev)
  920. {
  921. struct nvme_queue *nvmeq = dev->queues[0];
  922. struct nvme_command c;
  923. struct nvme_cmd_info *cmd_info;
  924. struct request *req;
  925. req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
  926. if (IS_ERR(req))
  927. return PTR_ERR(req);
  928. req->cmd_flags |= REQ_NO_TIMEOUT;
  929. cmd_info = blk_mq_rq_to_pdu(req);
  930. nvme_set_info(cmd_info, NULL, async_req_completion);
  931. memset(&c, 0, sizeof(c));
  932. c.common.opcode = nvme_admin_async_event;
  933. c.common.command_id = req->tag;
  934. blk_mq_free_request(req);
  935. return __nvme_submit_cmd(nvmeq, &c);
  936. }
  937. static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
  938. struct nvme_command *cmd,
  939. struct async_cmd_info *cmdinfo, unsigned timeout)
  940. {
  941. struct nvme_queue *nvmeq = dev->queues[0];
  942. struct request *req;
  943. struct nvme_cmd_info *cmd_rq;
  944. req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
  945. if (IS_ERR(req))
  946. return PTR_ERR(req);
  947. req->timeout = timeout;
  948. cmd_rq = blk_mq_rq_to_pdu(req);
  949. cmdinfo->req = req;
  950. nvme_set_info(cmd_rq, cmdinfo, async_completion);
  951. cmdinfo->status = -EINTR;
  952. cmd->common.command_id = req->tag;
  953. return nvme_submit_cmd(nvmeq, cmd);
  954. }
  955. static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
  956. {
  957. struct nvme_command c;
  958. memset(&c, 0, sizeof(c));
  959. c.delete_queue.opcode = opcode;
  960. c.delete_queue.qid = cpu_to_le16(id);
  961. return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
  962. }
  963. static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
  964. struct nvme_queue *nvmeq)
  965. {
  966. struct nvme_command c;
  967. int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
  968. /*
  969. * Note: we (ab)use the fact the the prp fields survive if no data
  970. * is attached to the request.
  971. */
  972. memset(&c, 0, sizeof(c));
  973. c.create_cq.opcode = nvme_admin_create_cq;
  974. c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
  975. c.create_cq.cqid = cpu_to_le16(qid);
  976. c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  977. c.create_cq.cq_flags = cpu_to_le16(flags);
  978. c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
  979. return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
  980. }
  981. static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
  982. struct nvme_queue *nvmeq)
  983. {
  984. struct nvme_command c;
  985. int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
  986. /*
  987. * Note: we (ab)use the fact the the prp fields survive if no data
  988. * is attached to the request.
  989. */
  990. memset(&c, 0, sizeof(c));
  991. c.create_sq.opcode = nvme_admin_create_sq;
  992. c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
  993. c.create_sq.sqid = cpu_to_le16(qid);
  994. c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
  995. c.create_sq.sq_flags = cpu_to_le16(flags);
  996. c.create_sq.cqid = cpu_to_le16(qid);
  997. return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
  998. }
  999. static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
  1000. {
  1001. return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
  1002. }
  1003. static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
  1004. {
  1005. return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
  1006. }
  1007. int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
  1008. {
  1009. struct nvme_command c = { };
  1010. int error;
  1011. /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
  1012. c.identify.opcode = nvme_admin_identify;
  1013. c.identify.cns = cpu_to_le32(1);
  1014. *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
  1015. if (!*id)
  1016. return -ENOMEM;
  1017. error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
  1018. sizeof(struct nvme_id_ctrl));
  1019. if (error)
  1020. kfree(*id);
  1021. return error;
  1022. }
  1023. int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
  1024. struct nvme_id_ns **id)
  1025. {
  1026. struct nvme_command c = { };
  1027. int error;
  1028. /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
  1029. c.identify.opcode = nvme_admin_identify,
  1030. c.identify.nsid = cpu_to_le32(nsid),
  1031. *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
  1032. if (!*id)
  1033. return -ENOMEM;
  1034. error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
  1035. sizeof(struct nvme_id_ns));
  1036. if (error)
  1037. kfree(*id);
  1038. return error;
  1039. }
  1040. int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
  1041. dma_addr_t dma_addr, u32 *result)
  1042. {
  1043. struct nvme_command c;
  1044. memset(&c, 0, sizeof(c));
  1045. c.features.opcode = nvme_admin_get_features;
  1046. c.features.nsid = cpu_to_le32(nsid);
  1047. c.features.prp1 = cpu_to_le64(dma_addr);
  1048. c.features.fid = cpu_to_le32(fid);
  1049. return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
  1050. result, 0);
  1051. }
  1052. int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
  1053. dma_addr_t dma_addr, u32 *result)
  1054. {
  1055. struct nvme_command c;
  1056. memset(&c, 0, sizeof(c));
  1057. c.features.opcode = nvme_admin_set_features;
  1058. c.features.prp1 = cpu_to_le64(dma_addr);
  1059. c.features.fid = cpu_to_le32(fid);
  1060. c.features.dword11 = cpu_to_le32(dword11);
  1061. return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
  1062. result, 0);
  1063. }
  1064. int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
  1065. {
  1066. struct nvme_command c = { };
  1067. int error;
  1068. c.common.opcode = nvme_admin_get_log_page,
  1069. c.common.nsid = cpu_to_le32(0xFFFFFFFF),
  1070. c.common.cdw10[0] = cpu_to_le32(
  1071. (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
  1072. NVME_LOG_SMART),
  1073. *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
  1074. if (!*log)
  1075. return -ENOMEM;
  1076. error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
  1077. sizeof(struct nvme_smart_log));
  1078. if (error)
  1079. kfree(*log);
  1080. return error;
  1081. }
  1082. /**
  1083. * nvme_abort_req - Attempt aborting a request
  1084. *
  1085. * Schedule controller reset if the command was already aborted once before and
  1086. * still hasn't been returned to the driver, or if this is the admin queue.
  1087. */
  1088. static void nvme_abort_req(struct request *req)
  1089. {
  1090. struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
  1091. struct nvme_queue *nvmeq = cmd_rq->nvmeq;
  1092. struct nvme_dev *dev = nvmeq->dev;
  1093. struct request *abort_req;
  1094. struct nvme_cmd_info *abort_cmd;
  1095. struct nvme_command cmd;
  1096. if (!nvmeq->qid || cmd_rq->aborted) {
  1097. unsigned long flags;
  1098. spin_lock_irqsave(&dev_list_lock, flags);
  1099. if (work_busy(&dev->reset_work))
  1100. goto out;
  1101. list_del_init(&dev->node);
  1102. dev_warn(dev->dev, "I/O %d QID %d timeout, reset controller\n",
  1103. req->tag, nvmeq->qid);
  1104. dev->reset_workfn = nvme_reset_failed_dev;
  1105. queue_work(nvme_workq, &dev->reset_work);
  1106. out:
  1107. spin_unlock_irqrestore(&dev_list_lock, flags);
  1108. return;
  1109. }
  1110. if (!dev->abort_limit)
  1111. return;
  1112. abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
  1113. false);
  1114. if (IS_ERR(abort_req))
  1115. return;
  1116. abort_cmd = blk_mq_rq_to_pdu(abort_req);
  1117. nvme_set_info(abort_cmd, abort_req, abort_completion);
  1118. memset(&cmd, 0, sizeof(cmd));
  1119. cmd.abort.opcode = nvme_admin_abort_cmd;
  1120. cmd.abort.cid = req->tag;
  1121. cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
  1122. cmd.abort.command_id = abort_req->tag;
  1123. --dev->abort_limit;
  1124. cmd_rq->aborted = 1;
  1125. dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
  1126. nvmeq->qid);
  1127. if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
  1128. dev_warn(nvmeq->q_dmadev,
  1129. "Could not abort I/O %d QID %d",
  1130. req->tag, nvmeq->qid);
  1131. blk_mq_free_request(abort_req);
  1132. }
  1133. }
  1134. static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
  1135. {
  1136. struct nvme_queue *nvmeq = data;
  1137. void *ctx;
  1138. nvme_completion_fn fn;
  1139. struct nvme_cmd_info *cmd;
  1140. struct nvme_completion cqe;
  1141. if (!blk_mq_request_started(req))
  1142. return;
  1143. cmd = blk_mq_rq_to_pdu(req);
  1144. if (cmd->ctx == CMD_CTX_CANCELLED)
  1145. return;
  1146. if (blk_queue_dying(req->q))
  1147. cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
  1148. else
  1149. cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
  1150. dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
  1151. req->tag, nvmeq->qid);
  1152. ctx = cancel_cmd_info(cmd, &fn);
  1153. fn(nvmeq, ctx, &cqe);
  1154. }
  1155. static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
  1156. {
  1157. struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
  1158. struct nvme_queue *nvmeq = cmd->nvmeq;
  1159. dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
  1160. nvmeq->qid);
  1161. spin_lock_irq(&nvmeq->q_lock);
  1162. nvme_abort_req(req);
  1163. spin_unlock_irq(&nvmeq->q_lock);
  1164. /*
  1165. * The aborted req will be completed on receiving the abort req.
  1166. * We enable the timer again. If hit twice, it'll cause a device reset,
  1167. * as the device then is in a faulty state.
  1168. */
  1169. return BLK_EH_RESET_TIMER;
  1170. }
  1171. static void nvme_free_queue(struct nvme_queue *nvmeq)
  1172. {
  1173. dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
  1174. (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
  1175. dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
  1176. nvmeq->sq_cmds, nvmeq->sq_dma_addr);
  1177. kfree(nvmeq);
  1178. }
  1179. static void nvme_free_queues(struct nvme_dev *dev, int lowest)
  1180. {
  1181. int i;
  1182. for (i = dev->queue_count - 1; i >= lowest; i--) {
  1183. struct nvme_queue *nvmeq = dev->queues[i];
  1184. dev->queue_count--;
  1185. dev->queues[i] = NULL;
  1186. nvme_free_queue(nvmeq);
  1187. }
  1188. }
  1189. /**
  1190. * nvme_suspend_queue - put queue into suspended state
  1191. * @nvmeq - queue to suspend
  1192. */
  1193. static int nvme_suspend_queue(struct nvme_queue *nvmeq)
  1194. {
  1195. int vector;
  1196. spin_lock_irq(&nvmeq->q_lock);
  1197. if (nvmeq->cq_vector == -1) {
  1198. spin_unlock_irq(&nvmeq->q_lock);
  1199. return 1;
  1200. }
  1201. vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
  1202. nvmeq->dev->online_queues--;
  1203. nvmeq->cq_vector = -1;
  1204. spin_unlock_irq(&nvmeq->q_lock);
  1205. if (!nvmeq->qid && nvmeq->dev->admin_q)
  1206. blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
  1207. irq_set_affinity_hint(vector, NULL);
  1208. free_irq(vector, nvmeq);
  1209. return 0;
  1210. }
  1211. static void nvme_clear_queue(struct nvme_queue *nvmeq)
  1212. {
  1213. spin_lock_irq(&nvmeq->q_lock);
  1214. if (nvmeq->tags && *nvmeq->tags)
  1215. blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
  1216. spin_unlock_irq(&nvmeq->q_lock);
  1217. }
  1218. static void nvme_disable_queue(struct nvme_dev *dev, int qid)
  1219. {
  1220. struct nvme_queue *nvmeq = dev->queues[qid];
  1221. if (!nvmeq)
  1222. return;
  1223. if (nvme_suspend_queue(nvmeq))
  1224. return;
  1225. /* Don't tell the adapter to delete the admin queue.
  1226. * Don't tell a removed adapter to delete IO queues. */
  1227. if (qid && readl(&dev->bar->csts) != -1) {
  1228. adapter_delete_sq(dev, qid);
  1229. adapter_delete_cq(dev, qid);
  1230. }
  1231. spin_lock_irq(&nvmeq->q_lock);
  1232. nvme_process_cq(nvmeq);
  1233. spin_unlock_irq(&nvmeq->q_lock);
  1234. }
  1235. static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
  1236. int depth)
  1237. {
  1238. struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
  1239. if (!nvmeq)
  1240. return NULL;
  1241. nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
  1242. &nvmeq->cq_dma_addr, GFP_KERNEL);
  1243. if (!nvmeq->cqes)
  1244. goto free_nvmeq;
  1245. nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
  1246. &nvmeq->sq_dma_addr, GFP_KERNEL);
  1247. if (!nvmeq->sq_cmds)
  1248. goto free_cqdma;
  1249. nvmeq->q_dmadev = dev->dev;
  1250. nvmeq->dev = dev;
  1251. snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
  1252. dev->instance, qid);
  1253. spin_lock_init(&nvmeq->q_lock);
  1254. nvmeq->cq_head = 0;
  1255. nvmeq->cq_phase = 1;
  1256. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1257. nvmeq->q_depth = depth;
  1258. nvmeq->qid = qid;
  1259. nvmeq->cq_vector = -1;
  1260. dev->queues[qid] = nvmeq;
  1261. /* make sure queue descriptor is set before queue count, for kthread */
  1262. mb();
  1263. dev->queue_count++;
  1264. return nvmeq;
  1265. free_cqdma:
  1266. dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
  1267. nvmeq->cq_dma_addr);
  1268. free_nvmeq:
  1269. kfree(nvmeq);
  1270. return NULL;
  1271. }
  1272. static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
  1273. const char *name)
  1274. {
  1275. if (use_threaded_interrupts)
  1276. return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
  1277. nvme_irq_check, nvme_irq, IRQF_SHARED,
  1278. name, nvmeq);
  1279. return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
  1280. IRQF_SHARED, name, nvmeq);
  1281. }
  1282. static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
  1283. {
  1284. struct nvme_dev *dev = nvmeq->dev;
  1285. spin_lock_irq(&nvmeq->q_lock);
  1286. nvmeq->sq_tail = 0;
  1287. nvmeq->cq_head = 0;
  1288. nvmeq->cq_phase = 1;
  1289. nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
  1290. memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
  1291. dev->online_queues++;
  1292. spin_unlock_irq(&nvmeq->q_lock);
  1293. }
  1294. static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
  1295. {
  1296. struct nvme_dev *dev = nvmeq->dev;
  1297. int result;
  1298. nvmeq->cq_vector = qid - 1;
  1299. result = adapter_alloc_cq(dev, qid, nvmeq);
  1300. if (result < 0)
  1301. return result;
  1302. result = adapter_alloc_sq(dev, qid, nvmeq);
  1303. if (result < 0)
  1304. goto release_cq;
  1305. result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
  1306. if (result < 0)
  1307. goto release_sq;
  1308. nvme_init_queue(nvmeq, qid);
  1309. return result;
  1310. release_sq:
  1311. adapter_delete_sq(dev, qid);
  1312. release_cq:
  1313. adapter_delete_cq(dev, qid);
  1314. return result;
  1315. }
  1316. static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
  1317. {
  1318. unsigned long timeout;
  1319. u32 bit = enabled ? NVME_CSTS_RDY : 0;
  1320. timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
  1321. while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
  1322. msleep(100);
  1323. if (fatal_signal_pending(current))
  1324. return -EINTR;
  1325. if (time_after(jiffies, timeout)) {
  1326. dev_err(dev->dev,
  1327. "Device not ready; aborting %s\n", enabled ?
  1328. "initialisation" : "reset");
  1329. return -ENODEV;
  1330. }
  1331. }
  1332. return 0;
  1333. }
  1334. /*
  1335. * If the device has been passed off to us in an enabled state, just clear
  1336. * the enabled bit. The spec says we should set the 'shutdown notification
  1337. * bits', but doing so may cause the device to complete commands to the
  1338. * admin queue ... and we don't know what memory that might be pointing at!
  1339. */
  1340. static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
  1341. {
  1342. dev->ctrl_config &= ~NVME_CC_SHN_MASK;
  1343. dev->ctrl_config &= ~NVME_CC_ENABLE;
  1344. writel(dev->ctrl_config, &dev->bar->cc);
  1345. return nvme_wait_ready(dev, cap, false);
  1346. }
  1347. static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
  1348. {
  1349. dev->ctrl_config &= ~NVME_CC_SHN_MASK;
  1350. dev->ctrl_config |= NVME_CC_ENABLE;
  1351. writel(dev->ctrl_config, &dev->bar->cc);
  1352. return nvme_wait_ready(dev, cap, true);
  1353. }
  1354. static int nvme_shutdown_ctrl(struct nvme_dev *dev)
  1355. {
  1356. unsigned long timeout;
  1357. dev->ctrl_config &= ~NVME_CC_SHN_MASK;
  1358. dev->ctrl_config |= NVME_CC_SHN_NORMAL;
  1359. writel(dev->ctrl_config, &dev->bar->cc);
  1360. timeout = SHUTDOWN_TIMEOUT + jiffies;
  1361. while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
  1362. NVME_CSTS_SHST_CMPLT) {
  1363. msleep(100);
  1364. if (fatal_signal_pending(current))
  1365. return -EINTR;
  1366. if (time_after(jiffies, timeout)) {
  1367. dev_err(dev->dev,
  1368. "Device shutdown incomplete; abort shutdown\n");
  1369. return -ENODEV;
  1370. }
  1371. }
  1372. return 0;
  1373. }
  1374. static struct blk_mq_ops nvme_mq_admin_ops = {
  1375. .queue_rq = nvme_queue_rq,
  1376. .map_queue = blk_mq_map_queue,
  1377. .init_hctx = nvme_admin_init_hctx,
  1378. .exit_hctx = nvme_admin_exit_hctx,
  1379. .init_request = nvme_admin_init_request,
  1380. .timeout = nvme_timeout,
  1381. };
  1382. static struct blk_mq_ops nvme_mq_ops = {
  1383. .queue_rq = nvme_queue_rq,
  1384. .map_queue = blk_mq_map_queue,
  1385. .init_hctx = nvme_init_hctx,
  1386. .init_request = nvme_init_request,
  1387. .timeout = nvme_timeout,
  1388. };
  1389. static void nvme_dev_remove_admin(struct nvme_dev *dev)
  1390. {
  1391. if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
  1392. blk_cleanup_queue(dev->admin_q);
  1393. blk_mq_free_tag_set(&dev->admin_tagset);
  1394. }
  1395. }
  1396. static int nvme_alloc_admin_tags(struct nvme_dev *dev)
  1397. {
  1398. if (!dev->admin_q) {
  1399. dev->admin_tagset.ops = &nvme_mq_admin_ops;
  1400. dev->admin_tagset.nr_hw_queues = 1;
  1401. dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
  1402. dev->admin_tagset.reserved_tags = 1;
  1403. dev->admin_tagset.timeout = ADMIN_TIMEOUT;
  1404. dev->admin_tagset.numa_node = dev_to_node(dev->dev);
  1405. dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
  1406. dev->admin_tagset.driver_data = dev;
  1407. if (blk_mq_alloc_tag_set(&dev->admin_tagset))
  1408. return -ENOMEM;
  1409. dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
  1410. if (IS_ERR(dev->admin_q)) {
  1411. blk_mq_free_tag_set(&dev->admin_tagset);
  1412. return -ENOMEM;
  1413. }
  1414. if (!blk_get_queue(dev->admin_q)) {
  1415. nvme_dev_remove_admin(dev);
  1416. dev->admin_q = NULL;
  1417. return -ENODEV;
  1418. }
  1419. } else
  1420. blk_mq_unfreeze_queue(dev->admin_q);
  1421. return 0;
  1422. }
  1423. static int nvme_configure_admin_queue(struct nvme_dev *dev)
  1424. {
  1425. int result;
  1426. u32 aqa;
  1427. u64 cap = readq(&dev->bar->cap);
  1428. struct nvme_queue *nvmeq;
  1429. unsigned page_shift = PAGE_SHIFT;
  1430. unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
  1431. unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
  1432. if (page_shift < dev_page_min) {
  1433. dev_err(dev->dev,
  1434. "Minimum device page size (%u) too large for "
  1435. "host (%u)\n", 1 << dev_page_min,
  1436. 1 << page_shift);
  1437. return -ENODEV;
  1438. }
  1439. if (page_shift > dev_page_max) {
  1440. dev_info(dev->dev,
  1441. "Device maximum page size (%u) smaller than "
  1442. "host (%u); enabling work-around\n",
  1443. 1 << dev_page_max, 1 << page_shift);
  1444. page_shift = dev_page_max;
  1445. }
  1446. result = nvme_disable_ctrl(dev, cap);
  1447. if (result < 0)
  1448. return result;
  1449. nvmeq = dev->queues[0];
  1450. if (!nvmeq) {
  1451. nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
  1452. if (!nvmeq)
  1453. return -ENOMEM;
  1454. }
  1455. aqa = nvmeq->q_depth - 1;
  1456. aqa |= aqa << 16;
  1457. dev->page_size = 1 << page_shift;
  1458. dev->ctrl_config = NVME_CC_CSS_NVM;
  1459. dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
  1460. dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
  1461. dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
  1462. writel(aqa, &dev->bar->aqa);
  1463. writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
  1464. writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
  1465. result = nvme_enable_ctrl(dev, cap);
  1466. if (result)
  1467. goto free_nvmeq;
  1468. nvmeq->cq_vector = 0;
  1469. result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
  1470. if (result) {
  1471. nvmeq->cq_vector = -1;
  1472. goto free_nvmeq;
  1473. }
  1474. return result;
  1475. free_nvmeq:
  1476. nvme_free_queues(dev, 0);
  1477. return result;
  1478. }
  1479. static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
  1480. {
  1481. struct nvme_dev *dev = ns->dev;
  1482. struct nvme_user_io io;
  1483. struct nvme_command c;
  1484. unsigned length, meta_len;
  1485. int status, write;
  1486. dma_addr_t meta_dma = 0;
  1487. void *meta = NULL;
  1488. void __user *metadata;
  1489. if (copy_from_user(&io, uio, sizeof(io)))
  1490. return -EFAULT;
  1491. switch (io.opcode) {
  1492. case nvme_cmd_write:
  1493. case nvme_cmd_read:
  1494. case nvme_cmd_compare:
  1495. break;
  1496. default:
  1497. return -EINVAL;
  1498. }
  1499. length = (io.nblocks + 1) << ns->lba_shift;
  1500. meta_len = (io.nblocks + 1) * ns->ms;
  1501. metadata = (void __user *)(unsigned long)io.metadata;
  1502. write = io.opcode & 1;
  1503. if (ns->ext) {
  1504. length += meta_len;
  1505. meta_len = 0;
  1506. }
  1507. if (meta_len) {
  1508. if (((io.metadata & 3) || !io.metadata) && !ns->ext)
  1509. return -EINVAL;
  1510. meta = dma_alloc_coherent(dev->dev, meta_len,
  1511. &meta_dma, GFP_KERNEL);
  1512. if (!meta) {
  1513. status = -ENOMEM;
  1514. goto unmap;
  1515. }
  1516. if (write) {
  1517. if (copy_from_user(meta, metadata, meta_len)) {
  1518. status = -EFAULT;
  1519. goto unmap;
  1520. }
  1521. }
  1522. }
  1523. memset(&c, 0, sizeof(c));
  1524. c.rw.opcode = io.opcode;
  1525. c.rw.flags = io.flags;
  1526. c.rw.nsid = cpu_to_le32(ns->ns_id);
  1527. c.rw.slba = cpu_to_le64(io.slba);
  1528. c.rw.length = cpu_to_le16(io.nblocks);
  1529. c.rw.control = cpu_to_le16(io.control);
  1530. c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
  1531. c.rw.reftag = cpu_to_le32(io.reftag);
  1532. c.rw.apptag = cpu_to_le16(io.apptag);
  1533. c.rw.appmask = cpu_to_le16(io.appmask);
  1534. c.rw.metadata = cpu_to_le64(meta_dma);
  1535. status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
  1536. (void __user *)io.addr, length, NULL, 0);
  1537. unmap:
  1538. if (meta) {
  1539. if (status == NVME_SC_SUCCESS && !write) {
  1540. if (copy_to_user(metadata, meta, meta_len))
  1541. status = -EFAULT;
  1542. }
  1543. dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
  1544. }
  1545. return status;
  1546. }
  1547. static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
  1548. struct nvme_passthru_cmd __user *ucmd)
  1549. {
  1550. struct nvme_passthru_cmd cmd;
  1551. struct nvme_command c;
  1552. unsigned timeout = 0;
  1553. int status;
  1554. if (!capable(CAP_SYS_ADMIN))
  1555. return -EACCES;
  1556. if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
  1557. return -EFAULT;
  1558. memset(&c, 0, sizeof(c));
  1559. c.common.opcode = cmd.opcode;
  1560. c.common.flags = cmd.flags;
  1561. c.common.nsid = cpu_to_le32(cmd.nsid);
  1562. c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
  1563. c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
  1564. c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
  1565. c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
  1566. c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
  1567. c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
  1568. c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
  1569. c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
  1570. if (cmd.timeout_ms)
  1571. timeout = msecs_to_jiffies(cmd.timeout_ms);
  1572. status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
  1573. NULL, (void __user *)cmd.addr, cmd.data_len,
  1574. &cmd.result, timeout);
  1575. if (status >= 0) {
  1576. if (put_user(cmd.result, &ucmd->result))
  1577. return -EFAULT;
  1578. }
  1579. return status;
  1580. }
  1581. static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
  1582. unsigned long arg)
  1583. {
  1584. struct nvme_ns *ns = bdev->bd_disk->private_data;
  1585. switch (cmd) {
  1586. case NVME_IOCTL_ID:
  1587. force_successful_syscall_return();
  1588. return ns->ns_id;
  1589. case NVME_IOCTL_ADMIN_CMD:
  1590. return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
  1591. case NVME_IOCTL_IO_CMD:
  1592. return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
  1593. case NVME_IOCTL_SUBMIT_IO:
  1594. return nvme_submit_io(ns, (void __user *)arg);
  1595. case SG_GET_VERSION_NUM:
  1596. return nvme_sg_get_version_num((void __user *)arg);
  1597. case SG_IO:
  1598. return nvme_sg_io(ns, (void __user *)arg);
  1599. default:
  1600. return -ENOTTY;
  1601. }
  1602. }
  1603. #ifdef CONFIG_COMPAT
  1604. static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
  1605. unsigned int cmd, unsigned long arg)
  1606. {
  1607. switch (cmd) {
  1608. case SG_IO:
  1609. return -ENOIOCTLCMD;
  1610. }
  1611. return nvme_ioctl(bdev, mode, cmd, arg);
  1612. }
  1613. #else
  1614. #define nvme_compat_ioctl NULL
  1615. #endif
  1616. static int nvme_open(struct block_device *bdev, fmode_t mode)
  1617. {
  1618. int ret = 0;
  1619. struct nvme_ns *ns;
  1620. spin_lock(&dev_list_lock);
  1621. ns = bdev->bd_disk->private_data;
  1622. if (!ns)
  1623. ret = -ENXIO;
  1624. else if (!kref_get_unless_zero(&ns->dev->kref))
  1625. ret = -ENXIO;
  1626. spin_unlock(&dev_list_lock);
  1627. return ret;
  1628. }
  1629. static void nvme_free_dev(struct kref *kref);
  1630. static void nvme_release(struct gendisk *disk, fmode_t mode)
  1631. {
  1632. struct nvme_ns *ns = disk->private_data;
  1633. struct nvme_dev *dev = ns->dev;
  1634. kref_put(&dev->kref, nvme_free_dev);
  1635. }
  1636. static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
  1637. {
  1638. /* some standard values */
  1639. geo->heads = 1 << 6;
  1640. geo->sectors = 1 << 5;
  1641. geo->cylinders = get_capacity(bd->bd_disk) >> 11;
  1642. return 0;
  1643. }
  1644. static void nvme_config_discard(struct nvme_ns *ns)
  1645. {
  1646. u32 logical_block_size = queue_logical_block_size(ns->queue);
  1647. ns->queue->limits.discard_zeroes_data = 0;
  1648. ns->queue->limits.discard_alignment = logical_block_size;
  1649. ns->queue->limits.discard_granularity = logical_block_size;
  1650. ns->queue->limits.max_discard_sectors = 0xffffffff;
  1651. queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
  1652. }
  1653. static int nvme_revalidate_disk(struct gendisk *disk)
  1654. {
  1655. struct nvme_ns *ns = disk->private_data;
  1656. struct nvme_dev *dev = ns->dev;
  1657. struct nvme_id_ns *id;
  1658. u8 lbaf, pi_type;
  1659. u16 old_ms;
  1660. unsigned short bs;
  1661. if (nvme_identify_ns(dev, ns->ns_id, &id)) {
  1662. dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
  1663. dev->instance, ns->ns_id);
  1664. return -ENODEV;
  1665. }
  1666. if (id->ncap == 0) {
  1667. kfree(id);
  1668. return -ENODEV;
  1669. }
  1670. old_ms = ns->ms;
  1671. lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
  1672. ns->lba_shift = id->lbaf[lbaf].ds;
  1673. ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
  1674. ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
  1675. /*
  1676. * If identify namespace failed, use default 512 byte block size so
  1677. * block layer can use before failing read/write for 0 capacity.
  1678. */
  1679. if (ns->lba_shift == 0)
  1680. ns->lba_shift = 9;
  1681. bs = 1 << ns->lba_shift;
  1682. /* XXX: PI implementation requires metadata equal t10 pi tuple size */
  1683. pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
  1684. id->dps & NVME_NS_DPS_PI_MASK : 0;
  1685. if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
  1686. ns->ms != old_ms ||
  1687. bs != queue_logical_block_size(disk->queue) ||
  1688. (ns->ms && ns->ext)))
  1689. blk_integrity_unregister(disk);
  1690. ns->pi_type = pi_type;
  1691. blk_queue_logical_block_size(ns->queue, bs);
  1692. if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
  1693. !ns->ext)
  1694. nvme_init_integrity(ns);
  1695. if (ns->ms && !blk_get_integrity(disk))
  1696. set_capacity(disk, 0);
  1697. else
  1698. set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
  1699. if (dev->oncs & NVME_CTRL_ONCS_DSM)
  1700. nvme_config_discard(ns);
  1701. kfree(id);
  1702. return 0;
  1703. }
  1704. static const struct block_device_operations nvme_fops = {
  1705. .owner = THIS_MODULE,
  1706. .ioctl = nvme_ioctl,
  1707. .compat_ioctl = nvme_compat_ioctl,
  1708. .open = nvme_open,
  1709. .release = nvme_release,
  1710. .getgeo = nvme_getgeo,
  1711. .revalidate_disk= nvme_revalidate_disk,
  1712. };
  1713. static int nvme_kthread(void *data)
  1714. {
  1715. struct nvme_dev *dev, *next;
  1716. while (!kthread_should_stop()) {
  1717. set_current_state(TASK_INTERRUPTIBLE);
  1718. spin_lock(&dev_list_lock);
  1719. list_for_each_entry_safe(dev, next, &dev_list, node) {
  1720. int i;
  1721. if (readl(&dev->bar->csts) & NVME_CSTS_CFS) {
  1722. if (work_busy(&dev->reset_work))
  1723. continue;
  1724. list_del_init(&dev->node);
  1725. dev_warn(dev->dev,
  1726. "Failed status: %x, reset controller\n",
  1727. readl(&dev->bar->csts));
  1728. dev->reset_workfn = nvme_reset_failed_dev;
  1729. queue_work(nvme_workq, &dev->reset_work);
  1730. continue;
  1731. }
  1732. for (i = 0; i < dev->queue_count; i++) {
  1733. struct nvme_queue *nvmeq = dev->queues[i];
  1734. if (!nvmeq)
  1735. continue;
  1736. spin_lock_irq(&nvmeq->q_lock);
  1737. nvme_process_cq(nvmeq);
  1738. while ((i == 0) && (dev->event_limit > 0)) {
  1739. if (nvme_submit_async_admin_req(dev))
  1740. break;
  1741. dev->event_limit--;
  1742. }
  1743. spin_unlock_irq(&nvmeq->q_lock);
  1744. }
  1745. }
  1746. spin_unlock(&dev_list_lock);
  1747. schedule_timeout(round_jiffies_relative(HZ));
  1748. }
  1749. return 0;
  1750. }
  1751. static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
  1752. {
  1753. struct nvme_ns *ns;
  1754. struct gendisk *disk;
  1755. int node = dev_to_node(dev->dev);
  1756. ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
  1757. if (!ns)
  1758. return;
  1759. ns->queue = blk_mq_init_queue(&dev->tagset);
  1760. if (IS_ERR(ns->queue))
  1761. goto out_free_ns;
  1762. queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
  1763. queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
  1764. queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
  1765. ns->dev = dev;
  1766. ns->queue->queuedata = ns;
  1767. disk = alloc_disk_node(0, node);
  1768. if (!disk)
  1769. goto out_free_queue;
  1770. ns->ns_id = nsid;
  1771. ns->disk = disk;
  1772. ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
  1773. list_add_tail(&ns->list, &dev->namespaces);
  1774. blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
  1775. if (dev->max_hw_sectors)
  1776. blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
  1777. if (dev->stripe_size)
  1778. blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
  1779. if (dev->vwc & NVME_CTRL_VWC_PRESENT)
  1780. blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
  1781. disk->major = nvme_major;
  1782. disk->first_minor = 0;
  1783. disk->fops = &nvme_fops;
  1784. disk->private_data = ns;
  1785. disk->queue = ns->queue;
  1786. disk->driverfs_dev = dev->device;
  1787. disk->flags = GENHD_FL_EXT_DEVT;
  1788. sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
  1789. /*
  1790. * Initialize capacity to 0 until we establish the namespace format and
  1791. * setup integrity extentions if necessary. The revalidate_disk after
  1792. * add_disk allows the driver to register with integrity if the format
  1793. * requires it.
  1794. */
  1795. set_capacity(disk, 0);
  1796. if (nvme_revalidate_disk(ns->disk))
  1797. goto out_free_disk;
  1798. add_disk(ns->disk);
  1799. if (ns->ms)
  1800. revalidate_disk(ns->disk);
  1801. return;
  1802. out_free_disk:
  1803. kfree(disk);
  1804. list_del(&ns->list);
  1805. out_free_queue:
  1806. blk_cleanup_queue(ns->queue);
  1807. out_free_ns:
  1808. kfree(ns);
  1809. }
  1810. static void nvme_create_io_queues(struct nvme_dev *dev)
  1811. {
  1812. unsigned i;
  1813. for (i = dev->queue_count; i <= dev->max_qid; i++)
  1814. if (!nvme_alloc_queue(dev, i, dev->q_depth))
  1815. break;
  1816. for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
  1817. if (nvme_create_queue(dev->queues[i], i))
  1818. break;
  1819. }
  1820. static int set_queue_count(struct nvme_dev *dev, int count)
  1821. {
  1822. int status;
  1823. u32 result;
  1824. u32 q_count = (count - 1) | ((count - 1) << 16);
  1825. status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
  1826. &result);
  1827. if (status < 0)
  1828. return status;
  1829. if (status > 0) {
  1830. dev_err(dev->dev, "Could not set queue count (%d)\n", status);
  1831. return 0;
  1832. }
  1833. return min(result & 0xffff, result >> 16) + 1;
  1834. }
  1835. static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
  1836. {
  1837. return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
  1838. }
  1839. static int nvme_setup_io_queues(struct nvme_dev *dev)
  1840. {
  1841. struct nvme_queue *adminq = dev->queues[0];
  1842. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1843. int result, i, vecs, nr_io_queues, size;
  1844. nr_io_queues = num_possible_cpus();
  1845. result = set_queue_count(dev, nr_io_queues);
  1846. if (result <= 0)
  1847. return result;
  1848. if (result < nr_io_queues)
  1849. nr_io_queues = result;
  1850. size = db_bar_size(dev, nr_io_queues);
  1851. if (size > 8192) {
  1852. iounmap(dev->bar);
  1853. do {
  1854. dev->bar = ioremap(pci_resource_start(pdev, 0), size);
  1855. if (dev->bar)
  1856. break;
  1857. if (!--nr_io_queues)
  1858. return -ENOMEM;
  1859. size = db_bar_size(dev, nr_io_queues);
  1860. } while (1);
  1861. dev->dbs = ((void __iomem *)dev->bar) + 4096;
  1862. adminq->q_db = dev->dbs;
  1863. }
  1864. /* Deregister the admin queue's interrupt */
  1865. free_irq(dev->entry[0].vector, adminq);
  1866. /*
  1867. * If we enable msix early due to not intx, disable it again before
  1868. * setting up the full range we need.
  1869. */
  1870. if (!pdev->irq)
  1871. pci_disable_msix(pdev);
  1872. for (i = 0; i < nr_io_queues; i++)
  1873. dev->entry[i].entry = i;
  1874. vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
  1875. if (vecs < 0) {
  1876. vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
  1877. if (vecs < 0) {
  1878. vecs = 1;
  1879. } else {
  1880. for (i = 0; i < vecs; i++)
  1881. dev->entry[i].vector = i + pdev->irq;
  1882. }
  1883. }
  1884. /*
  1885. * Should investigate if there's a performance win from allocating
  1886. * more queues than interrupt vectors; it might allow the submission
  1887. * path to scale better, even if the receive path is limited by the
  1888. * number of interrupts.
  1889. */
  1890. nr_io_queues = vecs;
  1891. dev->max_qid = nr_io_queues;
  1892. result = queue_request_irq(dev, adminq, adminq->irqname);
  1893. if (result) {
  1894. adminq->cq_vector = -1;
  1895. goto free_queues;
  1896. }
  1897. /* Free previously allocated queues that are no longer usable */
  1898. nvme_free_queues(dev, nr_io_queues + 1);
  1899. nvme_create_io_queues(dev);
  1900. return 0;
  1901. free_queues:
  1902. nvme_free_queues(dev, 1);
  1903. return result;
  1904. }
  1905. static void nvme_free_namespace(struct nvme_ns *ns)
  1906. {
  1907. list_del(&ns->list);
  1908. spin_lock(&dev_list_lock);
  1909. ns->disk->private_data = NULL;
  1910. spin_unlock(&dev_list_lock);
  1911. put_disk(ns->disk);
  1912. kfree(ns);
  1913. }
  1914. static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
  1915. {
  1916. struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
  1917. struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
  1918. return nsa->ns_id - nsb->ns_id;
  1919. }
  1920. static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
  1921. {
  1922. struct nvme_ns *ns;
  1923. list_for_each_entry(ns, &dev->namespaces, list) {
  1924. if (ns->ns_id == nsid)
  1925. return ns;
  1926. if (ns->ns_id > nsid)
  1927. break;
  1928. }
  1929. return NULL;
  1930. }
  1931. static inline bool nvme_io_incapable(struct nvme_dev *dev)
  1932. {
  1933. return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
  1934. dev->online_queues < 2);
  1935. }
  1936. static void nvme_ns_remove(struct nvme_ns *ns)
  1937. {
  1938. bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
  1939. if (kill)
  1940. blk_set_queue_dying(ns->queue);
  1941. if (ns->disk->flags & GENHD_FL_UP) {
  1942. if (blk_get_integrity(ns->disk))
  1943. blk_integrity_unregister(ns->disk);
  1944. del_gendisk(ns->disk);
  1945. }
  1946. if (kill || !blk_queue_dying(ns->queue)) {
  1947. blk_mq_abort_requeue_list(ns->queue);
  1948. blk_cleanup_queue(ns->queue);
  1949. }
  1950. }
  1951. static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
  1952. {
  1953. struct nvme_ns *ns, *next;
  1954. unsigned i;
  1955. for (i = 1; i <= nn; i++) {
  1956. ns = nvme_find_ns(dev, i);
  1957. if (ns) {
  1958. if (revalidate_disk(ns->disk)) {
  1959. nvme_ns_remove(ns);
  1960. nvme_free_namespace(ns);
  1961. }
  1962. } else
  1963. nvme_alloc_ns(dev, i);
  1964. }
  1965. list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
  1966. if (ns->ns_id > nn) {
  1967. nvme_ns_remove(ns);
  1968. nvme_free_namespace(ns);
  1969. }
  1970. }
  1971. list_sort(NULL, &dev->namespaces, ns_cmp);
  1972. }
  1973. static void nvme_dev_scan(struct work_struct *work)
  1974. {
  1975. struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
  1976. struct nvme_id_ctrl *ctrl;
  1977. if (!dev->tagset.tags)
  1978. return;
  1979. if (nvme_identify_ctrl(dev, &ctrl))
  1980. return;
  1981. nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
  1982. kfree(ctrl);
  1983. }
  1984. /*
  1985. * Return: error value if an error occurred setting up the queues or calling
  1986. * Identify Device. 0 if these succeeded, even if adding some of the
  1987. * namespaces failed. At the moment, these failures are silent. TBD which
  1988. * failures should be reported.
  1989. */
  1990. static int nvme_dev_add(struct nvme_dev *dev)
  1991. {
  1992. struct pci_dev *pdev = to_pci_dev(dev->dev);
  1993. int res;
  1994. unsigned nn;
  1995. struct nvme_id_ctrl *ctrl;
  1996. int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
  1997. res = nvme_identify_ctrl(dev, &ctrl);
  1998. if (res) {
  1999. dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
  2000. return -EIO;
  2001. }
  2002. nn = le32_to_cpup(&ctrl->nn);
  2003. dev->oncs = le16_to_cpup(&ctrl->oncs);
  2004. dev->abort_limit = ctrl->acl + 1;
  2005. dev->vwc = ctrl->vwc;
  2006. memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
  2007. memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
  2008. memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
  2009. if (ctrl->mdts)
  2010. dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
  2011. if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
  2012. (pdev->device == 0x0953) && ctrl->vs[3]) {
  2013. unsigned int max_hw_sectors;
  2014. dev->stripe_size = 1 << (ctrl->vs[3] + shift);
  2015. max_hw_sectors = dev->stripe_size >> (shift - 9);
  2016. if (dev->max_hw_sectors) {
  2017. dev->max_hw_sectors = min(max_hw_sectors,
  2018. dev->max_hw_sectors);
  2019. } else
  2020. dev->max_hw_sectors = max_hw_sectors;
  2021. }
  2022. kfree(ctrl);
  2023. if (!dev->tagset.tags) {
  2024. dev->tagset.ops = &nvme_mq_ops;
  2025. dev->tagset.nr_hw_queues = dev->online_queues - 1;
  2026. dev->tagset.timeout = NVME_IO_TIMEOUT;
  2027. dev->tagset.numa_node = dev_to_node(dev->dev);
  2028. dev->tagset.queue_depth =
  2029. min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
  2030. dev->tagset.cmd_size = nvme_cmd_size(dev);
  2031. dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
  2032. dev->tagset.driver_data = dev;
  2033. if (blk_mq_alloc_tag_set(&dev->tagset))
  2034. return 0;
  2035. }
  2036. schedule_work(&dev->scan_work);
  2037. return 0;
  2038. }
  2039. static int nvme_dev_map(struct nvme_dev *dev)
  2040. {
  2041. u64 cap;
  2042. int bars, result = -ENOMEM;
  2043. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2044. if (pci_enable_device_mem(pdev))
  2045. return result;
  2046. dev->entry[0].vector = pdev->irq;
  2047. pci_set_master(pdev);
  2048. bars = pci_select_bars(pdev, IORESOURCE_MEM);
  2049. if (!bars)
  2050. goto disable_pci;
  2051. if (pci_request_selected_regions(pdev, bars, "nvme"))
  2052. goto disable_pci;
  2053. if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
  2054. dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
  2055. goto disable;
  2056. dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
  2057. if (!dev->bar)
  2058. goto disable;
  2059. if (readl(&dev->bar->csts) == -1) {
  2060. result = -ENODEV;
  2061. goto unmap;
  2062. }
  2063. /*
  2064. * Some devices don't advertse INTx interrupts, pre-enable a single
  2065. * MSIX vec for setup. We'll adjust this later.
  2066. */
  2067. if (!pdev->irq) {
  2068. result = pci_enable_msix(pdev, dev->entry, 1);
  2069. if (result < 0)
  2070. goto unmap;
  2071. }
  2072. cap = readq(&dev->bar->cap);
  2073. dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
  2074. dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
  2075. dev->dbs = ((void __iomem *)dev->bar) + 4096;
  2076. return 0;
  2077. unmap:
  2078. iounmap(dev->bar);
  2079. dev->bar = NULL;
  2080. disable:
  2081. pci_release_regions(pdev);
  2082. disable_pci:
  2083. pci_disable_device(pdev);
  2084. return result;
  2085. }
  2086. static void nvme_dev_unmap(struct nvme_dev *dev)
  2087. {
  2088. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2089. if (pdev->msi_enabled)
  2090. pci_disable_msi(pdev);
  2091. else if (pdev->msix_enabled)
  2092. pci_disable_msix(pdev);
  2093. if (dev->bar) {
  2094. iounmap(dev->bar);
  2095. dev->bar = NULL;
  2096. pci_release_regions(pdev);
  2097. }
  2098. if (pci_is_enabled(pdev))
  2099. pci_disable_device(pdev);
  2100. }
  2101. struct nvme_delq_ctx {
  2102. struct task_struct *waiter;
  2103. struct kthread_worker *worker;
  2104. atomic_t refcount;
  2105. };
  2106. static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
  2107. {
  2108. dq->waiter = current;
  2109. mb();
  2110. for (;;) {
  2111. set_current_state(TASK_KILLABLE);
  2112. if (!atomic_read(&dq->refcount))
  2113. break;
  2114. if (!schedule_timeout(ADMIN_TIMEOUT) ||
  2115. fatal_signal_pending(current)) {
  2116. /*
  2117. * Disable the controller first since we can't trust it
  2118. * at this point, but leave the admin queue enabled
  2119. * until all queue deletion requests are flushed.
  2120. * FIXME: This may take a while if there are more h/w
  2121. * queues than admin tags.
  2122. */
  2123. set_current_state(TASK_RUNNING);
  2124. nvme_disable_ctrl(dev, readq(&dev->bar->cap));
  2125. nvme_clear_queue(dev->queues[0]);
  2126. flush_kthread_worker(dq->worker);
  2127. nvme_disable_queue(dev, 0);
  2128. return;
  2129. }
  2130. }
  2131. set_current_state(TASK_RUNNING);
  2132. }
  2133. static void nvme_put_dq(struct nvme_delq_ctx *dq)
  2134. {
  2135. atomic_dec(&dq->refcount);
  2136. if (dq->waiter)
  2137. wake_up_process(dq->waiter);
  2138. }
  2139. static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
  2140. {
  2141. atomic_inc(&dq->refcount);
  2142. return dq;
  2143. }
  2144. static void nvme_del_queue_end(struct nvme_queue *nvmeq)
  2145. {
  2146. struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
  2147. nvme_put_dq(dq);
  2148. }
  2149. static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
  2150. kthread_work_func_t fn)
  2151. {
  2152. struct nvme_command c;
  2153. memset(&c, 0, sizeof(c));
  2154. c.delete_queue.opcode = opcode;
  2155. c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
  2156. init_kthread_work(&nvmeq->cmdinfo.work, fn);
  2157. return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
  2158. ADMIN_TIMEOUT);
  2159. }
  2160. static void nvme_del_cq_work_handler(struct kthread_work *work)
  2161. {
  2162. struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
  2163. cmdinfo.work);
  2164. nvme_del_queue_end(nvmeq);
  2165. }
  2166. static int nvme_delete_cq(struct nvme_queue *nvmeq)
  2167. {
  2168. return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
  2169. nvme_del_cq_work_handler);
  2170. }
  2171. static void nvme_del_sq_work_handler(struct kthread_work *work)
  2172. {
  2173. struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
  2174. cmdinfo.work);
  2175. int status = nvmeq->cmdinfo.status;
  2176. if (!status)
  2177. status = nvme_delete_cq(nvmeq);
  2178. if (status)
  2179. nvme_del_queue_end(nvmeq);
  2180. }
  2181. static int nvme_delete_sq(struct nvme_queue *nvmeq)
  2182. {
  2183. return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
  2184. nvme_del_sq_work_handler);
  2185. }
  2186. static void nvme_del_queue_start(struct kthread_work *work)
  2187. {
  2188. struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
  2189. cmdinfo.work);
  2190. if (nvme_delete_sq(nvmeq))
  2191. nvme_del_queue_end(nvmeq);
  2192. }
  2193. static void nvme_disable_io_queues(struct nvme_dev *dev)
  2194. {
  2195. int i;
  2196. DEFINE_KTHREAD_WORKER_ONSTACK(worker);
  2197. struct nvme_delq_ctx dq;
  2198. struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
  2199. &worker, "nvme%d", dev->instance);
  2200. if (IS_ERR(kworker_task)) {
  2201. dev_err(dev->dev,
  2202. "Failed to create queue del task\n");
  2203. for (i = dev->queue_count - 1; i > 0; i--)
  2204. nvme_disable_queue(dev, i);
  2205. return;
  2206. }
  2207. dq.waiter = NULL;
  2208. atomic_set(&dq.refcount, 0);
  2209. dq.worker = &worker;
  2210. for (i = dev->queue_count - 1; i > 0; i--) {
  2211. struct nvme_queue *nvmeq = dev->queues[i];
  2212. if (nvme_suspend_queue(nvmeq))
  2213. continue;
  2214. nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
  2215. nvmeq->cmdinfo.worker = dq.worker;
  2216. init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
  2217. queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
  2218. }
  2219. nvme_wait_dq(&dq, dev);
  2220. kthread_stop(kworker_task);
  2221. }
  2222. /*
  2223. * Remove the node from the device list and check
  2224. * for whether or not we need to stop the nvme_thread.
  2225. */
  2226. static void nvme_dev_list_remove(struct nvme_dev *dev)
  2227. {
  2228. struct task_struct *tmp = NULL;
  2229. spin_lock(&dev_list_lock);
  2230. list_del_init(&dev->node);
  2231. if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
  2232. tmp = nvme_thread;
  2233. nvme_thread = NULL;
  2234. }
  2235. spin_unlock(&dev_list_lock);
  2236. if (tmp)
  2237. kthread_stop(tmp);
  2238. }
  2239. static void nvme_freeze_queues(struct nvme_dev *dev)
  2240. {
  2241. struct nvme_ns *ns;
  2242. list_for_each_entry(ns, &dev->namespaces, list) {
  2243. blk_mq_freeze_queue_start(ns->queue);
  2244. spin_lock_irq(ns->queue->queue_lock);
  2245. queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
  2246. spin_unlock_irq(ns->queue->queue_lock);
  2247. blk_mq_cancel_requeue_work(ns->queue);
  2248. blk_mq_stop_hw_queues(ns->queue);
  2249. }
  2250. }
  2251. static void nvme_unfreeze_queues(struct nvme_dev *dev)
  2252. {
  2253. struct nvme_ns *ns;
  2254. list_for_each_entry(ns, &dev->namespaces, list) {
  2255. queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
  2256. blk_mq_unfreeze_queue(ns->queue);
  2257. blk_mq_start_stopped_hw_queues(ns->queue, true);
  2258. blk_mq_kick_requeue_list(ns->queue);
  2259. }
  2260. }
  2261. static void nvme_dev_shutdown(struct nvme_dev *dev)
  2262. {
  2263. int i;
  2264. u32 csts = -1;
  2265. nvme_dev_list_remove(dev);
  2266. if (dev->bar) {
  2267. nvme_freeze_queues(dev);
  2268. csts = readl(&dev->bar->csts);
  2269. }
  2270. if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
  2271. for (i = dev->queue_count - 1; i >= 0; i--) {
  2272. struct nvme_queue *nvmeq = dev->queues[i];
  2273. nvme_suspend_queue(nvmeq);
  2274. }
  2275. } else {
  2276. nvme_disable_io_queues(dev);
  2277. nvme_shutdown_ctrl(dev);
  2278. nvme_disable_queue(dev, 0);
  2279. }
  2280. nvme_dev_unmap(dev);
  2281. for (i = dev->queue_count - 1; i >= 0; i--)
  2282. nvme_clear_queue(dev->queues[i]);
  2283. }
  2284. static void nvme_dev_remove(struct nvme_dev *dev)
  2285. {
  2286. struct nvme_ns *ns;
  2287. list_for_each_entry(ns, &dev->namespaces, list)
  2288. nvme_ns_remove(ns);
  2289. }
  2290. static int nvme_setup_prp_pools(struct nvme_dev *dev)
  2291. {
  2292. dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
  2293. PAGE_SIZE, PAGE_SIZE, 0);
  2294. if (!dev->prp_page_pool)
  2295. return -ENOMEM;
  2296. /* Optimisation for I/Os between 4k and 128k */
  2297. dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
  2298. 256, 256, 0);
  2299. if (!dev->prp_small_pool) {
  2300. dma_pool_destroy(dev->prp_page_pool);
  2301. return -ENOMEM;
  2302. }
  2303. return 0;
  2304. }
  2305. static void nvme_release_prp_pools(struct nvme_dev *dev)
  2306. {
  2307. dma_pool_destroy(dev->prp_page_pool);
  2308. dma_pool_destroy(dev->prp_small_pool);
  2309. }
  2310. static DEFINE_IDA(nvme_instance_ida);
  2311. static int nvme_set_instance(struct nvme_dev *dev)
  2312. {
  2313. int instance, error;
  2314. do {
  2315. if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
  2316. return -ENODEV;
  2317. spin_lock(&dev_list_lock);
  2318. error = ida_get_new(&nvme_instance_ida, &instance);
  2319. spin_unlock(&dev_list_lock);
  2320. } while (error == -EAGAIN);
  2321. if (error)
  2322. return -ENODEV;
  2323. dev->instance = instance;
  2324. return 0;
  2325. }
  2326. static void nvme_release_instance(struct nvme_dev *dev)
  2327. {
  2328. spin_lock(&dev_list_lock);
  2329. ida_remove(&nvme_instance_ida, dev->instance);
  2330. spin_unlock(&dev_list_lock);
  2331. }
  2332. static void nvme_free_namespaces(struct nvme_dev *dev)
  2333. {
  2334. struct nvme_ns *ns, *next;
  2335. list_for_each_entry_safe(ns, next, &dev->namespaces, list)
  2336. nvme_free_namespace(ns);
  2337. }
  2338. static void nvme_free_dev(struct kref *kref)
  2339. {
  2340. struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
  2341. put_device(dev->dev);
  2342. put_device(dev->device);
  2343. nvme_free_namespaces(dev);
  2344. nvme_release_instance(dev);
  2345. if (dev->tagset.tags)
  2346. blk_mq_free_tag_set(&dev->tagset);
  2347. if (dev->admin_q)
  2348. blk_put_queue(dev->admin_q);
  2349. kfree(dev->queues);
  2350. kfree(dev->entry);
  2351. kfree(dev);
  2352. }
  2353. static int nvme_dev_open(struct inode *inode, struct file *f)
  2354. {
  2355. struct nvme_dev *dev;
  2356. int instance = iminor(inode);
  2357. int ret = -ENODEV;
  2358. spin_lock(&dev_list_lock);
  2359. list_for_each_entry(dev, &dev_list, node) {
  2360. if (dev->instance == instance) {
  2361. if (!dev->admin_q) {
  2362. ret = -EWOULDBLOCK;
  2363. break;
  2364. }
  2365. if (!kref_get_unless_zero(&dev->kref))
  2366. break;
  2367. f->private_data = dev;
  2368. ret = 0;
  2369. break;
  2370. }
  2371. }
  2372. spin_unlock(&dev_list_lock);
  2373. return ret;
  2374. }
  2375. static int nvme_dev_release(struct inode *inode, struct file *f)
  2376. {
  2377. struct nvme_dev *dev = f->private_data;
  2378. kref_put(&dev->kref, nvme_free_dev);
  2379. return 0;
  2380. }
  2381. static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
  2382. {
  2383. struct nvme_dev *dev = f->private_data;
  2384. struct nvme_ns *ns;
  2385. switch (cmd) {
  2386. case NVME_IOCTL_ADMIN_CMD:
  2387. return nvme_user_cmd(dev, NULL, (void __user *)arg);
  2388. case NVME_IOCTL_IO_CMD:
  2389. if (list_empty(&dev->namespaces))
  2390. return -ENOTTY;
  2391. ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
  2392. return nvme_user_cmd(dev, ns, (void __user *)arg);
  2393. case NVME_IOCTL_RESET:
  2394. dev_warn(dev->dev, "resetting controller\n");
  2395. return nvme_reset(dev);
  2396. default:
  2397. return -ENOTTY;
  2398. }
  2399. }
  2400. static const struct file_operations nvme_dev_fops = {
  2401. .owner = THIS_MODULE,
  2402. .open = nvme_dev_open,
  2403. .release = nvme_dev_release,
  2404. .unlocked_ioctl = nvme_dev_ioctl,
  2405. .compat_ioctl = nvme_dev_ioctl,
  2406. };
  2407. static void nvme_set_irq_hints(struct nvme_dev *dev)
  2408. {
  2409. struct nvme_queue *nvmeq;
  2410. int i;
  2411. for (i = 0; i < dev->online_queues; i++) {
  2412. nvmeq = dev->queues[i];
  2413. if (!nvmeq->tags || !(*nvmeq->tags))
  2414. continue;
  2415. irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
  2416. blk_mq_tags_cpumask(*nvmeq->tags));
  2417. }
  2418. }
  2419. static int nvme_dev_start(struct nvme_dev *dev)
  2420. {
  2421. int result;
  2422. bool start_thread = false;
  2423. result = nvme_dev_map(dev);
  2424. if (result)
  2425. return result;
  2426. result = nvme_configure_admin_queue(dev);
  2427. if (result)
  2428. goto unmap;
  2429. spin_lock(&dev_list_lock);
  2430. if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
  2431. start_thread = true;
  2432. nvme_thread = NULL;
  2433. }
  2434. list_add(&dev->node, &dev_list);
  2435. spin_unlock(&dev_list_lock);
  2436. if (start_thread) {
  2437. nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
  2438. wake_up_all(&nvme_kthread_wait);
  2439. } else
  2440. wait_event_killable(nvme_kthread_wait, nvme_thread);
  2441. if (IS_ERR_OR_NULL(nvme_thread)) {
  2442. result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
  2443. goto disable;
  2444. }
  2445. nvme_init_queue(dev->queues[0], 0);
  2446. result = nvme_alloc_admin_tags(dev);
  2447. if (result)
  2448. goto disable;
  2449. result = nvme_setup_io_queues(dev);
  2450. if (result)
  2451. goto free_tags;
  2452. nvme_set_irq_hints(dev);
  2453. dev->event_limit = 1;
  2454. return result;
  2455. free_tags:
  2456. nvme_dev_remove_admin(dev);
  2457. blk_put_queue(dev->admin_q);
  2458. dev->admin_q = NULL;
  2459. dev->queues[0]->tags = NULL;
  2460. disable:
  2461. nvme_disable_queue(dev, 0);
  2462. nvme_dev_list_remove(dev);
  2463. unmap:
  2464. nvme_dev_unmap(dev);
  2465. return result;
  2466. }
  2467. static int nvme_remove_dead_ctrl(void *arg)
  2468. {
  2469. struct nvme_dev *dev = (struct nvme_dev *)arg;
  2470. struct pci_dev *pdev = to_pci_dev(dev->dev);
  2471. if (pci_get_drvdata(pdev))
  2472. pci_stop_and_remove_bus_device_locked(pdev);
  2473. kref_put(&dev->kref, nvme_free_dev);
  2474. return 0;
  2475. }
  2476. static void nvme_remove_disks(struct work_struct *ws)
  2477. {
  2478. struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
  2479. nvme_free_queues(dev, 1);
  2480. nvme_dev_remove(dev);
  2481. }
  2482. static int nvme_dev_resume(struct nvme_dev *dev)
  2483. {
  2484. int ret;
  2485. ret = nvme_dev_start(dev);
  2486. if (ret)
  2487. return ret;
  2488. if (dev->online_queues < 2) {
  2489. spin_lock(&dev_list_lock);
  2490. dev->reset_workfn = nvme_remove_disks;
  2491. queue_work(nvme_workq, &dev->reset_work);
  2492. spin_unlock(&dev_list_lock);
  2493. } else {
  2494. nvme_unfreeze_queues(dev);
  2495. nvme_dev_add(dev);
  2496. nvme_set_irq_hints(dev);
  2497. }
  2498. return 0;
  2499. }
  2500. static void nvme_dead_ctrl(struct nvme_dev *dev)
  2501. {
  2502. dev_warn(dev->dev, "Device failed to resume\n");
  2503. kref_get(&dev->kref);
  2504. if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
  2505. dev->instance))) {
  2506. dev_err(dev->dev,
  2507. "Failed to start controller remove task\n");
  2508. kref_put(&dev->kref, nvme_free_dev);
  2509. }
  2510. }
  2511. static void nvme_dev_reset(struct nvme_dev *dev)
  2512. {
  2513. bool in_probe = work_busy(&dev->probe_work);
  2514. nvme_dev_shutdown(dev);
  2515. /* Synchronize with device probe so that work will see failure status
  2516. * and exit gracefully without trying to schedule another reset */
  2517. flush_work(&dev->probe_work);
  2518. /* Fail this device if reset occured during probe to avoid
  2519. * infinite initialization loops. */
  2520. if (in_probe) {
  2521. nvme_dead_ctrl(dev);
  2522. return;
  2523. }
  2524. /* Schedule device resume asynchronously so the reset work is available
  2525. * to cleanup errors that may occur during reinitialization */
  2526. schedule_work(&dev->probe_work);
  2527. }
  2528. static void nvme_reset_failed_dev(struct work_struct *ws)
  2529. {
  2530. struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
  2531. nvme_dev_reset(dev);
  2532. }
  2533. static void nvme_reset_workfn(struct work_struct *work)
  2534. {
  2535. struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
  2536. dev->reset_workfn(work);
  2537. }
  2538. static int nvme_reset(struct nvme_dev *dev)
  2539. {
  2540. int ret = -EBUSY;
  2541. if (!dev->admin_q || blk_queue_dying(dev->admin_q))
  2542. return -ENODEV;
  2543. spin_lock(&dev_list_lock);
  2544. if (!work_pending(&dev->reset_work)) {
  2545. dev->reset_workfn = nvme_reset_failed_dev;
  2546. queue_work(nvme_workq, &dev->reset_work);
  2547. ret = 0;
  2548. }
  2549. spin_unlock(&dev_list_lock);
  2550. if (!ret) {
  2551. flush_work(&dev->reset_work);
  2552. flush_work(&dev->probe_work);
  2553. return 0;
  2554. }
  2555. return ret;
  2556. }
  2557. static ssize_t nvme_sysfs_reset(struct device *dev,
  2558. struct device_attribute *attr, const char *buf,
  2559. size_t count)
  2560. {
  2561. struct nvme_dev *ndev = dev_get_drvdata(dev);
  2562. int ret;
  2563. ret = nvme_reset(ndev);
  2564. if (ret < 0)
  2565. return ret;
  2566. return count;
  2567. }
  2568. static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
  2569. static void nvme_async_probe(struct work_struct *work);
  2570. static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  2571. {
  2572. int node, result = -ENOMEM;
  2573. struct nvme_dev *dev;
  2574. node = dev_to_node(&pdev->dev);
  2575. if (node == NUMA_NO_NODE)
  2576. set_dev_node(&pdev->dev, 0);
  2577. dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
  2578. if (!dev)
  2579. return -ENOMEM;
  2580. dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
  2581. GFP_KERNEL, node);
  2582. if (!dev->entry)
  2583. goto free;
  2584. dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
  2585. GFP_KERNEL, node);
  2586. if (!dev->queues)
  2587. goto free;
  2588. INIT_LIST_HEAD(&dev->namespaces);
  2589. dev->reset_workfn = nvme_reset_failed_dev;
  2590. INIT_WORK(&dev->reset_work, nvme_reset_workfn);
  2591. dev->dev = get_device(&pdev->dev);
  2592. pci_set_drvdata(pdev, dev);
  2593. result = nvme_set_instance(dev);
  2594. if (result)
  2595. goto put_pci;
  2596. result = nvme_setup_prp_pools(dev);
  2597. if (result)
  2598. goto release;
  2599. kref_init(&dev->kref);
  2600. dev->device = device_create(nvme_class, &pdev->dev,
  2601. MKDEV(nvme_char_major, dev->instance),
  2602. dev, "nvme%d", dev->instance);
  2603. if (IS_ERR(dev->device)) {
  2604. result = PTR_ERR(dev->device);
  2605. goto release_pools;
  2606. }
  2607. get_device(dev->device);
  2608. dev_set_drvdata(dev->device, dev);
  2609. result = device_create_file(dev->device, &dev_attr_reset_controller);
  2610. if (result)
  2611. goto put_dev;
  2612. INIT_LIST_HEAD(&dev->node);
  2613. INIT_WORK(&dev->scan_work, nvme_dev_scan);
  2614. INIT_WORK(&dev->probe_work, nvme_async_probe);
  2615. schedule_work(&dev->probe_work);
  2616. return 0;
  2617. put_dev:
  2618. device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
  2619. put_device(dev->device);
  2620. release_pools:
  2621. nvme_release_prp_pools(dev);
  2622. release:
  2623. nvme_release_instance(dev);
  2624. put_pci:
  2625. put_device(dev->dev);
  2626. free:
  2627. kfree(dev->queues);
  2628. kfree(dev->entry);
  2629. kfree(dev);
  2630. return result;
  2631. }
  2632. static void nvme_async_probe(struct work_struct *work)
  2633. {
  2634. struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
  2635. if (nvme_dev_resume(dev) && !work_busy(&dev->reset_work))
  2636. nvme_dead_ctrl(dev);
  2637. }
  2638. static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
  2639. {
  2640. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2641. if (prepare)
  2642. nvme_dev_shutdown(dev);
  2643. else
  2644. nvme_dev_resume(dev);
  2645. }
  2646. static void nvme_shutdown(struct pci_dev *pdev)
  2647. {
  2648. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2649. nvme_dev_shutdown(dev);
  2650. }
  2651. static void nvme_remove(struct pci_dev *pdev)
  2652. {
  2653. struct nvme_dev *dev = pci_get_drvdata(pdev);
  2654. spin_lock(&dev_list_lock);
  2655. list_del_init(&dev->node);
  2656. spin_unlock(&dev_list_lock);
  2657. pci_set_drvdata(pdev, NULL);
  2658. flush_work(&dev->probe_work);
  2659. flush_work(&dev->reset_work);
  2660. flush_work(&dev->scan_work);
  2661. device_remove_file(dev->device, &dev_attr_reset_controller);
  2662. nvme_dev_remove(dev);
  2663. nvme_dev_shutdown(dev);
  2664. nvme_dev_remove_admin(dev);
  2665. device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
  2666. nvme_free_queues(dev, 0);
  2667. nvme_release_prp_pools(dev);
  2668. kref_put(&dev->kref, nvme_free_dev);
  2669. }
  2670. /* These functions are yet to be implemented */
  2671. #define nvme_error_detected NULL
  2672. #define nvme_dump_registers NULL
  2673. #define nvme_link_reset NULL
  2674. #define nvme_slot_reset NULL
  2675. #define nvme_error_resume NULL
  2676. #ifdef CONFIG_PM_SLEEP
  2677. static int nvme_suspend(struct device *dev)
  2678. {
  2679. struct pci_dev *pdev = to_pci_dev(dev);
  2680. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2681. nvme_dev_shutdown(ndev);
  2682. return 0;
  2683. }
  2684. static int nvme_resume(struct device *dev)
  2685. {
  2686. struct pci_dev *pdev = to_pci_dev(dev);
  2687. struct nvme_dev *ndev = pci_get_drvdata(pdev);
  2688. if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
  2689. ndev->reset_workfn = nvme_reset_failed_dev;
  2690. queue_work(nvme_workq, &ndev->reset_work);
  2691. }
  2692. return 0;
  2693. }
  2694. #endif
  2695. static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
  2696. static const struct pci_error_handlers nvme_err_handler = {
  2697. .error_detected = nvme_error_detected,
  2698. .mmio_enabled = nvme_dump_registers,
  2699. .link_reset = nvme_link_reset,
  2700. .slot_reset = nvme_slot_reset,
  2701. .resume = nvme_error_resume,
  2702. .reset_notify = nvme_reset_notify,
  2703. };
  2704. /* Move to pci_ids.h later */
  2705. #define PCI_CLASS_STORAGE_EXPRESS 0x010802
  2706. static const struct pci_device_id nvme_id_table[] = {
  2707. { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
  2708. { 0, }
  2709. };
  2710. MODULE_DEVICE_TABLE(pci, nvme_id_table);
  2711. static struct pci_driver nvme_driver = {
  2712. .name = "nvme",
  2713. .id_table = nvme_id_table,
  2714. .probe = nvme_probe,
  2715. .remove = nvme_remove,
  2716. .shutdown = nvme_shutdown,
  2717. .driver = {
  2718. .pm = &nvme_dev_pm_ops,
  2719. },
  2720. .err_handler = &nvme_err_handler,
  2721. };
  2722. static int __init nvme_init(void)
  2723. {
  2724. int result;
  2725. init_waitqueue_head(&nvme_kthread_wait);
  2726. nvme_workq = create_singlethread_workqueue("nvme");
  2727. if (!nvme_workq)
  2728. return -ENOMEM;
  2729. result = register_blkdev(nvme_major, "nvme");
  2730. if (result < 0)
  2731. goto kill_workq;
  2732. else if (result > 0)
  2733. nvme_major = result;
  2734. result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
  2735. &nvme_dev_fops);
  2736. if (result < 0)
  2737. goto unregister_blkdev;
  2738. else if (result > 0)
  2739. nvme_char_major = result;
  2740. nvme_class = class_create(THIS_MODULE, "nvme");
  2741. if (IS_ERR(nvme_class)) {
  2742. result = PTR_ERR(nvme_class);
  2743. goto unregister_chrdev;
  2744. }
  2745. result = pci_register_driver(&nvme_driver);
  2746. if (result)
  2747. goto destroy_class;
  2748. return 0;
  2749. destroy_class:
  2750. class_destroy(nvme_class);
  2751. unregister_chrdev:
  2752. __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
  2753. unregister_blkdev:
  2754. unregister_blkdev(nvme_major, "nvme");
  2755. kill_workq:
  2756. destroy_workqueue(nvme_workq);
  2757. return result;
  2758. }
  2759. static void __exit nvme_exit(void)
  2760. {
  2761. pci_unregister_driver(&nvme_driver);
  2762. unregister_blkdev(nvme_major, "nvme");
  2763. destroy_workqueue(nvme_workq);
  2764. class_destroy(nvme_class);
  2765. __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
  2766. BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
  2767. _nvme_check_size();
  2768. }
  2769. MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
  2770. MODULE_LICENSE("GPL");
  2771. MODULE_VERSION("1.0");
  2772. module_init(nvme_init);
  2773. module_exit(nvme_exit);