clock-sh7201.c 2.0 KB

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  1. /*
  2. * arch/sh/kernel/cpu/sh2a/clock-sh7201.c
  3. *
  4. * SH7201 support for the clock framework
  5. *
  6. * Copyright (C) 2008 Peter Griffin <pgriffin@mpc-data.co.uk>
  7. *
  8. * Based on clock-sh4.c
  9. * Copyright (C) 2005 Paul Mundt
  10. *
  11. * This file is subject to the terms and conditions of the GNU General Public
  12. * License. See the file "COPYING" in the main directory of this archive
  13. * for more details.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/kernel.h>
  17. #include <asm/clock.h>
  18. #include <asm/freq.h>
  19. #include <asm/io.h>
  20. static const int pll1rate[]={1,2,3,4,6,8};
  21. static const int pfc_divisors[]={1,2,3,4,6,8,12};
  22. #define ifc_divisors pfc_divisors
  23. static unsigned int pll2_mult;
  24. static void master_clk_init(struct clk *clk)
  25. {
  26. clk->rate = 10000000 * pll2_mult *
  27. pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
  28. }
  29. static struct sh_clk_ops sh7201_master_clk_ops = {
  30. .init = master_clk_init,
  31. };
  32. static unsigned long module_clk_recalc(struct clk *clk)
  33. {
  34. int idx = (__raw_readw(FREQCR) & 0x0007);
  35. return clk->parent->rate / pfc_divisors[idx];
  36. }
  37. static struct sh_clk_ops sh7201_module_clk_ops = {
  38. .recalc = module_clk_recalc,
  39. };
  40. static unsigned long bus_clk_recalc(struct clk *clk)
  41. {
  42. int idx = (__raw_readw(FREQCR) & 0x0007);
  43. return clk->parent->rate / pfc_divisors[idx];
  44. }
  45. static struct sh_clk_ops sh7201_bus_clk_ops = {
  46. .recalc = bus_clk_recalc,
  47. };
  48. static unsigned long cpu_clk_recalc(struct clk *clk)
  49. {
  50. int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
  51. return clk->parent->rate / ifc_divisors[idx];
  52. }
  53. static struct sh_clk_ops sh7201_cpu_clk_ops = {
  54. .recalc = cpu_clk_recalc,
  55. };
  56. static struct sh_clk_ops *sh7201_clk_ops[] = {
  57. &sh7201_master_clk_ops,
  58. &sh7201_module_clk_ops,
  59. &sh7201_bus_clk_ops,
  60. &sh7201_cpu_clk_ops,
  61. };
  62. void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
  63. {
  64. if (test_mode_pin(MODE_PIN1 | MODE_PIN0))
  65. pll2_mult = 1;
  66. else if (test_mode_pin(MODE_PIN1))
  67. pll2_mult = 2;
  68. else
  69. pll2_mult = 4;
  70. if (idx < ARRAY_SIZE(sh7201_clk_ops))
  71. *ops = sh7201_clk_ops[idx];
  72. }