cvmx-interrupt-decodes.c 14 KB

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  1. /***********************license start***************
  2. * Author: Cavium Networks
  3. *
  4. * Contact: support@caviumnetworks.com
  5. * This file is part of the OCTEON SDK
  6. *
  7. * Copyright (c) 2003-2009 Cavium Networks
  8. *
  9. * This file is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License, Version 2, as
  11. * published by the Free Software Foundation.
  12. *
  13. * This file is distributed in the hope that it will be useful, but
  14. * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16. * NONINFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this file; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22. * or visit http://www.gnu.org/licenses/.
  23. *
  24. * This file may also be available under a different license from Cavium.
  25. * Contact Cavium Networks for more information
  26. ***********************license end**************************************/
  27. /*
  28. *
  29. * Automatically generated functions useful for enabling
  30. * and decoding RSL_INT_BLOCKS interrupts.
  31. *
  32. */
  33. #include <asm/octeon/octeon.h>
  34. #include <asm/octeon/cvmx-gmxx-defs.h>
  35. #include <asm/octeon/cvmx-pcsx-defs.h>
  36. #include <asm/octeon/cvmx-pcsxx-defs.h>
  37. #include <asm/octeon/cvmx-spxx-defs.h>
  38. #include <asm/octeon/cvmx-stxx-defs.h>
  39. #ifndef PRINT_ERROR
  40. #define PRINT_ERROR(format, ...)
  41. #endif
  42. /**
  43. * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t
  44. */
  45. void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
  46. {
  47. union cvmx_gmxx_rxx_int_en gmx_rx_int_en;
  48. cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block),
  49. cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block)));
  50. gmx_rx_int_en.u64 = 0;
  51. if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
  52. /* Skipping gmx_rx_int_en.s.reserved_29_63 */
  53. gmx_rx_int_en.s.hg2cc = 1;
  54. gmx_rx_int_en.s.hg2fld = 1;
  55. gmx_rx_int_en.s.undat = 1;
  56. gmx_rx_int_en.s.uneop = 1;
  57. gmx_rx_int_en.s.unsop = 1;
  58. gmx_rx_int_en.s.bad_term = 1;
  59. gmx_rx_int_en.s.bad_seq = 1;
  60. gmx_rx_int_en.s.rem_fault = 1;
  61. gmx_rx_int_en.s.loc_fault = 1;
  62. gmx_rx_int_en.s.pause_drp = 1;
  63. /* Skipping gmx_rx_int_en.s.reserved_16_18 */
  64. /*gmx_rx_int_en.s.ifgerr = 1; */
  65. /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
  66. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  67. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  68. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  69. gmx_rx_int_en.s.ovrerr = 1;
  70. /* Skipping gmx_rx_int_en.s.reserved_9_9 */
  71. gmx_rx_int_en.s.skperr = 1;
  72. gmx_rx_int_en.s.rcverr = 1;
  73. /* Skipping gmx_rx_int_en.s.reserved_5_6 */
  74. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  75. gmx_rx_int_en.s.jabber = 1;
  76. /* Skipping gmx_rx_int_en.s.reserved_2_2 */
  77. gmx_rx_int_en.s.carext = 1;
  78. /* Skipping gmx_rx_int_en.s.reserved_0_0 */
  79. }
  80. if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
  81. /* Skipping gmx_rx_int_en.s.reserved_19_63 */
  82. /*gmx_rx_int_en.s.phy_dupx = 1; */
  83. /*gmx_rx_int_en.s.phy_spd = 1; */
  84. /*gmx_rx_int_en.s.phy_link = 1; */
  85. /*gmx_rx_int_en.s.ifgerr = 1; */
  86. /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
  87. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  88. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  89. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  90. gmx_rx_int_en.s.ovrerr = 1;
  91. gmx_rx_int_en.s.niberr = 1;
  92. gmx_rx_int_en.s.skperr = 1;
  93. gmx_rx_int_en.s.rcverr = 1;
  94. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  95. gmx_rx_int_en.s.alnerr = 1;
  96. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  97. gmx_rx_int_en.s.jabber = 1;
  98. gmx_rx_int_en.s.maxerr = 1;
  99. gmx_rx_int_en.s.carext = 1;
  100. gmx_rx_int_en.s.minerr = 1;
  101. }
  102. if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
  103. /* Skipping gmx_rx_int_en.s.reserved_20_63 */
  104. gmx_rx_int_en.s.pause_drp = 1;
  105. /*gmx_rx_int_en.s.phy_dupx = 1; */
  106. /*gmx_rx_int_en.s.phy_spd = 1; */
  107. /*gmx_rx_int_en.s.phy_link = 1; */
  108. /*gmx_rx_int_en.s.ifgerr = 1; */
  109. /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
  110. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  111. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  112. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  113. gmx_rx_int_en.s.ovrerr = 1;
  114. gmx_rx_int_en.s.niberr = 1;
  115. gmx_rx_int_en.s.skperr = 1;
  116. gmx_rx_int_en.s.rcverr = 1;
  117. /* Skipping gmx_rx_int_en.s.reserved_6_6 */
  118. gmx_rx_int_en.s.alnerr = 1;
  119. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  120. gmx_rx_int_en.s.jabber = 1;
  121. /* Skipping gmx_rx_int_en.s.reserved_2_2 */
  122. gmx_rx_int_en.s.carext = 1;
  123. /* Skipping gmx_rx_int_en.s.reserved_0_0 */
  124. }
  125. if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
  126. /* Skipping gmx_rx_int_en.s.reserved_19_63 */
  127. /*gmx_rx_int_en.s.phy_dupx = 1; */
  128. /*gmx_rx_int_en.s.phy_spd = 1; */
  129. /*gmx_rx_int_en.s.phy_link = 1; */
  130. /*gmx_rx_int_en.s.ifgerr = 1; */
  131. /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
  132. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  133. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  134. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  135. gmx_rx_int_en.s.ovrerr = 1;
  136. gmx_rx_int_en.s.niberr = 1;
  137. gmx_rx_int_en.s.skperr = 1;
  138. gmx_rx_int_en.s.rcverr = 1;
  139. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  140. gmx_rx_int_en.s.alnerr = 1;
  141. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  142. gmx_rx_int_en.s.jabber = 1;
  143. gmx_rx_int_en.s.maxerr = 1;
  144. gmx_rx_int_en.s.carext = 1;
  145. gmx_rx_int_en.s.minerr = 1;
  146. }
  147. if (OCTEON_IS_MODEL(OCTEON_CN31XX)) {
  148. /* Skipping gmx_rx_int_en.s.reserved_19_63 */
  149. /*gmx_rx_int_en.s.phy_dupx = 1; */
  150. /*gmx_rx_int_en.s.phy_spd = 1; */
  151. /*gmx_rx_int_en.s.phy_link = 1; */
  152. /*gmx_rx_int_en.s.ifgerr = 1; */
  153. /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
  154. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  155. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  156. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  157. gmx_rx_int_en.s.ovrerr = 1;
  158. gmx_rx_int_en.s.niberr = 1;
  159. gmx_rx_int_en.s.skperr = 1;
  160. gmx_rx_int_en.s.rcverr = 1;
  161. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  162. gmx_rx_int_en.s.alnerr = 1;
  163. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  164. gmx_rx_int_en.s.jabber = 1;
  165. gmx_rx_int_en.s.maxerr = 1;
  166. gmx_rx_int_en.s.carext = 1;
  167. gmx_rx_int_en.s.minerr = 1;
  168. }
  169. if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  170. /* Skipping gmx_rx_int_en.s.reserved_20_63 */
  171. gmx_rx_int_en.s.pause_drp = 1;
  172. /*gmx_rx_int_en.s.phy_dupx = 1; */
  173. /*gmx_rx_int_en.s.phy_spd = 1; */
  174. /*gmx_rx_int_en.s.phy_link = 1; */
  175. /*gmx_rx_int_en.s.ifgerr = 1; */
  176. /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
  177. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  178. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  179. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  180. gmx_rx_int_en.s.ovrerr = 1;
  181. gmx_rx_int_en.s.niberr = 1;
  182. gmx_rx_int_en.s.skperr = 1;
  183. gmx_rx_int_en.s.rcverr = 1;
  184. /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */
  185. gmx_rx_int_en.s.alnerr = 1;
  186. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  187. gmx_rx_int_en.s.jabber = 1;
  188. gmx_rx_int_en.s.maxerr = 1;
  189. gmx_rx_int_en.s.carext = 1;
  190. gmx_rx_int_en.s.minerr = 1;
  191. }
  192. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  193. /* Skipping gmx_rx_int_en.s.reserved_29_63 */
  194. gmx_rx_int_en.s.hg2cc = 1;
  195. gmx_rx_int_en.s.hg2fld = 1;
  196. gmx_rx_int_en.s.undat = 1;
  197. gmx_rx_int_en.s.uneop = 1;
  198. gmx_rx_int_en.s.unsop = 1;
  199. gmx_rx_int_en.s.bad_term = 1;
  200. gmx_rx_int_en.s.bad_seq = 0;
  201. gmx_rx_int_en.s.rem_fault = 1;
  202. gmx_rx_int_en.s.loc_fault = 0;
  203. gmx_rx_int_en.s.pause_drp = 1;
  204. /* Skipping gmx_rx_int_en.s.reserved_16_18 */
  205. /*gmx_rx_int_en.s.ifgerr = 1; */
  206. /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */
  207. /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
  208. /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
  209. /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
  210. gmx_rx_int_en.s.ovrerr = 1;
  211. /* Skipping gmx_rx_int_en.s.reserved_9_9 */
  212. gmx_rx_int_en.s.skperr = 1;
  213. gmx_rx_int_en.s.rcverr = 1;
  214. /* Skipping gmx_rx_int_en.s.reserved_5_6 */
  215. /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */
  216. gmx_rx_int_en.s.jabber = 1;
  217. /* Skipping gmx_rx_int_en.s.reserved_2_2 */
  218. gmx_rx_int_en.s.carext = 1;
  219. /* Skipping gmx_rx_int_en.s.reserved_0_0 */
  220. }
  221. cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64);
  222. }
  223. /**
  224. * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t
  225. */
  226. void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block)
  227. {
  228. union cvmx_pcsx_intx_en_reg pcs_int_en_reg;
  229. cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block),
  230. cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block)));
  231. pcs_int_en_reg.u64 = 0;
  232. if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
  233. /* Skipping pcs_int_en_reg.s.reserved_12_63 */
  234. /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
  235. pcs_int_en_reg.s.sync_bad_en = 1;
  236. pcs_int_en_reg.s.an_bad_en = 1;
  237. pcs_int_en_reg.s.rxlock_en = 1;
  238. pcs_int_en_reg.s.rxbad_en = 1;
  239. /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
  240. pcs_int_en_reg.s.txbad_en = 1;
  241. pcs_int_en_reg.s.txfifo_en = 1;
  242. pcs_int_en_reg.s.txfifu_en = 1;
  243. pcs_int_en_reg.s.an_err_en = 1;
  244. /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
  245. /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
  246. }
  247. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  248. /* Skipping pcs_int_en_reg.s.reserved_12_63 */
  249. /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */
  250. pcs_int_en_reg.s.sync_bad_en = 1;
  251. pcs_int_en_reg.s.an_bad_en = 1;
  252. pcs_int_en_reg.s.rxlock_en = 1;
  253. pcs_int_en_reg.s.rxbad_en = 1;
  254. /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */
  255. pcs_int_en_reg.s.txbad_en = 1;
  256. pcs_int_en_reg.s.txfifo_en = 1;
  257. pcs_int_en_reg.s.txfifu_en = 1;
  258. pcs_int_en_reg.s.an_err_en = 1;
  259. /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */
  260. /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */
  261. }
  262. cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64);
  263. }
  264. /**
  265. * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t
  266. */
  267. void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index)
  268. {
  269. union cvmx_pcsxx_int_en_reg pcsx_int_en_reg;
  270. cvmx_write_csr(CVMX_PCSXX_INT_REG(index),
  271. cvmx_read_csr(CVMX_PCSXX_INT_REG(index)));
  272. pcsx_int_en_reg.u64 = 0;
  273. if (OCTEON_IS_MODEL(OCTEON_CN56XX)) {
  274. /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
  275. pcsx_int_en_reg.s.algnlos_en = 1;
  276. pcsx_int_en_reg.s.synlos_en = 1;
  277. pcsx_int_en_reg.s.bitlckls_en = 1;
  278. pcsx_int_en_reg.s.rxsynbad_en = 1;
  279. pcsx_int_en_reg.s.rxbad_en = 1;
  280. pcsx_int_en_reg.s.txflt_en = 1;
  281. }
  282. if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
  283. /* Skipping pcsx_int_en_reg.s.reserved_6_63 */
  284. pcsx_int_en_reg.s.algnlos_en = 1;
  285. pcsx_int_en_reg.s.synlos_en = 1;
  286. pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */
  287. pcsx_int_en_reg.s.rxsynbad_en = 1;
  288. pcsx_int_en_reg.s.rxbad_en = 1;
  289. pcsx_int_en_reg.s.txflt_en = 1;
  290. }
  291. cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64);
  292. }
  293. /**
  294. * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t
  295. */
  296. void __cvmx_interrupt_spxx_int_msk_enable(int index)
  297. {
  298. union cvmx_spxx_int_msk spx_int_msk;
  299. cvmx_write_csr(CVMX_SPXX_INT_REG(index),
  300. cvmx_read_csr(CVMX_SPXX_INT_REG(index)));
  301. spx_int_msk.u64 = 0;
  302. if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
  303. /* Skipping spx_int_msk.s.reserved_12_63 */
  304. spx_int_msk.s.calerr = 1;
  305. spx_int_msk.s.syncerr = 1;
  306. spx_int_msk.s.diperr = 1;
  307. spx_int_msk.s.tpaovr = 1;
  308. spx_int_msk.s.rsverr = 1;
  309. spx_int_msk.s.drwnng = 1;
  310. spx_int_msk.s.clserr = 1;
  311. spx_int_msk.s.spiovr = 1;
  312. /* Skipping spx_int_msk.s.reserved_2_3 */
  313. spx_int_msk.s.abnorm = 1;
  314. spx_int_msk.s.prtnxa = 1;
  315. }
  316. if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  317. /* Skipping spx_int_msk.s.reserved_12_63 */
  318. spx_int_msk.s.calerr = 1;
  319. spx_int_msk.s.syncerr = 1;
  320. spx_int_msk.s.diperr = 1;
  321. spx_int_msk.s.tpaovr = 1;
  322. spx_int_msk.s.rsverr = 1;
  323. spx_int_msk.s.drwnng = 1;
  324. spx_int_msk.s.clserr = 1;
  325. spx_int_msk.s.spiovr = 1;
  326. /* Skipping spx_int_msk.s.reserved_2_3 */
  327. spx_int_msk.s.abnorm = 1;
  328. spx_int_msk.s.prtnxa = 1;
  329. }
  330. cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64);
  331. }
  332. /**
  333. * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t
  334. */
  335. void __cvmx_interrupt_stxx_int_msk_enable(int index)
  336. {
  337. union cvmx_stxx_int_msk stx_int_msk;
  338. cvmx_write_csr(CVMX_STXX_INT_REG(index),
  339. cvmx_read_csr(CVMX_STXX_INT_REG(index)));
  340. stx_int_msk.u64 = 0;
  341. if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
  342. /* Skipping stx_int_msk.s.reserved_8_63 */
  343. stx_int_msk.s.frmerr = 1;
  344. stx_int_msk.s.unxfrm = 1;
  345. stx_int_msk.s.nosync = 1;
  346. stx_int_msk.s.diperr = 1;
  347. stx_int_msk.s.datovr = 1;
  348. stx_int_msk.s.ovrbst = 1;
  349. stx_int_msk.s.calpar1 = 1;
  350. stx_int_msk.s.calpar0 = 1;
  351. }
  352. if (OCTEON_IS_MODEL(OCTEON_CN58XX)) {
  353. /* Skipping stx_int_msk.s.reserved_8_63 */
  354. stx_int_msk.s.frmerr = 1;
  355. stx_int_msk.s.unxfrm = 1;
  356. stx_int_msk.s.nosync = 1;
  357. stx_int_msk.s.diperr = 1;
  358. stx_int_msk.s.datovr = 1;
  359. stx_int_msk.s.ovrbst = 1;
  360. stx_int_msk.s.calpar1 = 1;
  361. stx_int_msk.s.calpar0 = 1;
  362. }
  363. cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64);
  364. }