misc.S 2.1 KB

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  1. /*
  2. * Miscellaneous low-level MMU functions.
  3. *
  4. * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
  5. * Copyright (C) 2008-2009 PetaLogix
  6. * Copyright (C) 2007 Xilinx, Inc. All rights reserved.
  7. *
  8. * Derived from arch/ppc/kernel/misc.S
  9. *
  10. * This file is subject to the terms and conditions of the GNU General
  11. * Public License. See the file COPYING in the main directory of this
  12. * archive for more details.
  13. */
  14. #include <linux/linkage.h>
  15. #include <linux/sys.h>
  16. #include <asm/unistd.h>
  17. #include <linux/errno.h>
  18. #include <asm/mmu.h>
  19. #include <asm/page.h>
  20. .text
  21. /*
  22. * Flush MMU TLB
  23. *
  24. * We avoid flushing the pinned 0, 1 and possibly 2 entries.
  25. */
  26. .globl _tlbia;
  27. .type _tlbia, @function
  28. .align 4;
  29. _tlbia:
  30. lwi r12, r0, tlb_skip;
  31. /* isync */
  32. _tlbia_1:
  33. mts rtlbx, r12
  34. nop
  35. mts rtlbhi, r0 /* flush: ensure V is clear */
  36. nop
  37. rsubi r11, r12, MICROBLAZE_TLB_SIZE - 1
  38. bneid r11, _tlbia_1 /* loop for all entries */
  39. addik r12, r12, 1
  40. /* sync */
  41. rtsd r15, 8
  42. nop
  43. .size _tlbia, . - _tlbia
  44. /*
  45. * Flush MMU TLB for a particular address (in r5)
  46. */
  47. .globl _tlbie;
  48. .type _tlbie, @function
  49. .align 4;
  50. _tlbie:
  51. mts rtlbsx, r5 /* look up the address in TLB */
  52. nop
  53. mfs r12, rtlbx /* Retrieve index */
  54. nop
  55. blti r12, _tlbie_1 /* Check if found */
  56. mts rtlbhi, r0 /* flush: ensure V is clear */
  57. nop
  58. _tlbie_1:
  59. rtsd r15, 8
  60. nop
  61. .size _tlbie, . - _tlbie
  62. /*
  63. * Allocate TLB entry for early console
  64. */
  65. .globl early_console_reg_tlb_alloc;
  66. .type early_console_reg_tlb_alloc, @function
  67. .align 4;
  68. early_console_reg_tlb_alloc:
  69. /*
  70. * Load a TLB entry for the UART, so that microblaze_progress() can use
  71. * the UARTs nice and early. We use a 4k real==virtual mapping.
  72. */
  73. lwi r4, r0, tlb_skip
  74. mts rtlbx, r4 /* TLB slot 63 */
  75. or r4,r5,r0
  76. andi r4,r4,0xfffff000
  77. ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
  78. andi r5,r5,0xfffff000
  79. ori r5,r5,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
  80. mts rtlblo,r4 /* Load the data portion of the entry */
  81. nop
  82. mts rtlbhi,r5 /* Load the tag portion of the entry */
  83. nop
  84. lwi r5, r0, tlb_skip
  85. addik r5, r5, 1
  86. swi r5, r0, tlb_skip
  87. rtsd r15, 8
  88. nop
  89. .size early_console_reg_tlb_alloc, . - early_console_reg_tlb_alloc