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m5407sim.h

m5407sim.h 5.9 KB
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  1. /****************************************************************************/
    2. 

  2. 

  3. /*
    4. 

  4.  *	m5407sim.h -- ColdFire 5407 System Integration Module support.
    5. 

  5.  *
    6. 

  6.  *	(C) Copyright 2000,  Lineo (www.lineo.com)
    7. 

  7.  *	(C) Copyright 1999,  Moreton Bay Ventures Pty Ltd.
    8. 

  8.  *
    9. 

  9.  *      Modified by David W. Miller for the MCF5307 Eval Board.
    10. 

  10.  */
    11. 

  11. 

  12. /****************************************************************************/
    13. 

  13. #ifndef	m5407sim_h
    14. 

  14. #define	m5407sim_h
    15. 

  15. /****************************************************************************/
    16. 

  16. 

  17. #define	CPU_NAME		"COLDFIRE(m5407)"
    18. 

  18. #define	CPU_INSTR_PER_JIFFY	3
    19. 

  19. #define	MCF_BUSCLK		(MCF_CLK / 2)
    20. 

  20. 

  21. #include <asm/m54xxacr.h>
    22. 

  22. 

  23. /*
    24. 

  24.  *	Define the 5407 SIM register set addresses.
    25. 

  25.  */
    26. 

  26. #define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */
    27. 

  27. #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
    28. 

  28. #define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */
    29. 

  29. #define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog service*/
    30. 

  30. #define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */
    31. 

  31. #define	MCFSIM_IRQPAR		(MCF_MBAR + 0x06)	/* Intr Assignment */
    32. 

  32. #define	MCFSIM_PLLCR		(MCF_MBAR + 0x08)	/* PLL Ctrl */
    33. 

  33. #define	MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */
    34. 

  34. #define	MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */
    35. 

  35. #define	MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */
    36. 

  36. #define	MCFSIM_AVR		(MCF_MBAR + 0x4b)	/* Autovector Ctrl */
    37. 

  37. #define	MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */
    38. 

  38. #define	MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */
    39. 

  39. #define	MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */
    40. 

  40. #define	MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */
    41. 

  41. #define	MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */
    42. 

  42. #define	MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */
    43. 

  43. #define	MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */
    44. 

  44. #define	MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */
    45. 

  45. #define	MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */
    46. 

  46. #define	MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */
    47. 

  47. #define	MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */
    48. 

  48. #define	MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */
    49. 

  49. 

  50. #define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */
    51. 

  51. #define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */
    52. 

  52. #define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
    53. 

  53. #define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */
    54. 

  54. #define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */
    55. 

  55. #define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */
    56. 

  56. 

  57. #define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */
    58. 

  58. #define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */
    59. 

  59. #define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
    60. 

  60. #define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */
    61. 

  61. #define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */
    62. 

  62. #define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
    63. 

  63. #define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */
    64. 

  64. #define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */
    65. 

  65. #define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
    66. 

  66. #define MCFSIM_CSAR5		(MCF_MBAR + 0xbc)	/* CS 5 Address reg */
    67. 

  67. #define MCFSIM_CSMR5		(MCF_MBAR + 0xc0)	/* CS 5 Mask reg */
    68. 

  68. #define MCFSIM_CSCR5		(MCF_MBAR + 0xc6)	/* CS 5 Control reg */
    69. 

  69. #define MCFSIM_CSAR6		(MCF_MBAR + 0xc8)	/* CS 6 Address reg */
    70. 

  70. #define MCFSIM_CSMR6		(MCF_MBAR + 0xcc)	/* CS 6 Mask reg */
    71. 

  71. #define MCFSIM_CSCR6		(MCF_MBAR + 0xd2)	/* CS 6 Control reg */
    72. 

  72. #define MCFSIM_CSAR7		(MCF_MBAR + 0xd4)	/* CS 7 Address reg */
    73. 

  73. #define MCFSIM_CSMR7		(MCF_MBAR + 0xd8)	/* CS 7 Mask reg */
    74. 

  74. #define MCFSIM_CSCR7		(MCF_MBAR + 0xde)	/* CS 7 Control reg */
    75. 

  75. 

  76. #define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
    77. 

  77. #define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
    78. 

  78. #define MCFSIM_DMR0		(MCF_MBAR + 0x10c)	/* DRAM 0 Mask */
    79. 

  79. #define MCFSIM_DACR1		(MCF_MBAR + 0x110)	/* DRAM 1 Addr/Ctrl */
    80. 

  80. #define MCFSIM_DMR1		(MCF_MBAR + 0x114)	/* DRAM 1 Mask */
    81. 

  81. 

  82. /*
    83. 

  83.  *	Timer module.
    84. 

  84.  */
    85. 

  85. #define MCFTIMER_BASE1		(MCF_MBAR + 0x140)	/* Base of TIMER1 */
    86. 

  86. #define MCFTIMER_BASE2		(MCF_MBAR + 0x180)	/* Base of TIMER2 */
    87. 

  87. 

  88. #define MCFUART_BASE0		(MCF_MBAR + 0x1c0)	/* Base address UART0 */
    89. 

  89. #define MCFUART_BASE1		(MCF_MBAR + 0x200)	/* Base address UART1 */
    90. 

  90. 

  91. #define	MCFSIM_PADDR		(MCF_MBAR + 0x244)
    92. 

  92. #define	MCFSIM_PADAT		(MCF_MBAR + 0x248)
    93. 

  93. 

  94. /*
    95. 

  95.  *	DMA unit base addresses.
    96. 

  96.  */
    97. 

  97. #define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
    98. 

  98. #define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
    99. 

  99. #define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
    100. 

  100. #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
    101. 

  101. 

  102. /*
    103. 

  103.  * Generic GPIO support
    104. 

  104.  */
    105. 

  105. #define MCFGPIO_PIN_MAX		16
    106. 

  106. #define MCFGPIO_IRQ_MAX		-1
    107. 

  107. #define MCFGPIO_IRQ_VECBASE	-1
    108. 

  108. 

  109. /*
    110. 

  110.  *	Some symbol defines for the above...
    111. 

  111.  */
    112. 

  112. #define	MCFSIM_SWDICR		MCFSIM_ICR0	/* Watchdog timer ICR */
    113. 

  113. #define	MCFSIM_TIMER1ICR	MCFSIM_ICR1	/* Timer 1 ICR */
    114. 

  114. #define	MCFSIM_TIMER2ICR	MCFSIM_ICR2	/* Timer 2 ICR */
    115. 

  115. #define	MCFSIM_UART1ICR		MCFSIM_ICR4	/* UART 1 ICR */
    116. 

  116. #define	MCFSIM_UART2ICR		MCFSIM_ICR5	/* UART 2 ICR */
    117. 

  117. #define	MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
    118. 

  118. #define	MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
    119. 

  119. #define	MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
    120. 

  120. #define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */
    121. 

  121. 

  122. /*
    123. 

  123.  *	Some symbol defines for the Parallel Port Pin Assignment Register
    124. 

  124.  */
    125. 

  125. #define MCFSIM_PAR_DREQ0        0x40            /* Set to select DREQ0 input */
    126. 

  126.                                                 /* Clear to select par I/O */
    127. 

  127. #define MCFSIM_PAR_DREQ1        0x20            /* Select DREQ1 input */
    128. 

  128.                                                 /* Clear to select par I/O */
    129. 

  129. 

  130. /*
    131. 

  131.  *       Defines for the IRQPAR Register
    132. 

  132.  */
    133. 

  133. #define IRQ5_LEVEL4		0x80
    134. 

  134. #define IRQ3_LEVEL6		0x40
    135. 

  135. #define IRQ1_LEVEL2		0x20
    136. 

  136. 

  137. /*
    138. 

  138.  *	Define system peripheral IRQ usage.
    139. 

  139.  */
    140. 

  140. #define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */
    141. 

  141. #define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */
    142. 

  142. #define	MCF_IRQ_UART0		73		/* UART0 */
    143. 

  143. #define	MCF_IRQ_UART1		74		/* UART1 */
    144. 

  144. 

  145. /****************************************************************************/
    146. 

  146. #endif	/* m5407sim_h */
    147. 

  147.