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m5206sim.h

m5206sim.h 6.2 KB
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  1. /****************************************************************************/
    2. 

  2. 

  3. /*
    4. 

  4.  *	m5206sim.h -- ColdFire 5206 System Integration Module support.
    5. 

  5.  *
    6. 

  6.  *	(C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
    7. 

  7.  * 	(C) Copyright 2000, Lineo Inc. (www.lineo.com) 
    8. 

  8.  */
    9. 

  9. 

  10. /****************************************************************************/
    11. 

  11. #ifndef	m5206sim_h
    12. 

  12. #define	m5206sim_h
    13. 

  13. /****************************************************************************/
    14. 

  14. 

  15. #define	CPU_NAME		"COLDFIRE(m5206)"
    16. 

  16. #define	CPU_INSTR_PER_JIFFY	3
    17. 

  17. #define	MCF_BUSCLK		MCF_CLK
    18. 

  18. 

  19. #include <asm/m52xxacr.h>
    20. 

  20. 

  21. /*
    22. 

  22.  *	Define the 5206 SIM register set addresses.
    23. 

  23.  */
    24. 

  24. #define	MCFSIM_SIMR		(MCF_MBAR + 0x03)	/* SIM Config reg */
    25. 

  25. #define	MCFSIM_ICR1		(MCF_MBAR + 0x14)	/* Intr Ctrl reg 1 */
    26. 

  26. #define	MCFSIM_ICR2		(MCF_MBAR + 0x15)	/* Intr Ctrl reg 2 */
    27. 

  27. #define	MCFSIM_ICR3		(MCF_MBAR + 0x16)	/* Intr Ctrl reg 3 */
    28. 

  28. #define	MCFSIM_ICR4		(MCF_MBAR + 0x17)	/* Intr Ctrl reg 4 */
    29. 

  29. #define	MCFSIM_ICR5		(MCF_MBAR + 0x18)	/* Intr Ctrl reg 5 */
    30. 

  30. #define	MCFSIM_ICR6		(MCF_MBAR + 0x19)	/* Intr Ctrl reg 6 */
    31. 

  31. #define	MCFSIM_ICR7		(MCF_MBAR + 0x1a)	/* Intr Ctrl reg 7 */
    32. 

  32. #define	MCFSIM_ICR8		(MCF_MBAR + 0x1b)	/* Intr Ctrl reg 8 */
    33. 

  33. #define	MCFSIM_ICR9		(MCF_MBAR + 0x1c)	/* Intr Ctrl reg 9 */
    34. 

  34. #define	MCFSIM_ICR10		(MCF_MBAR + 0x1d)	/* Intr Ctrl reg 10 */
    35. 

  35. #define	MCFSIM_ICR11		(MCF_MBAR + 0x1e)	/* Intr Ctrl reg 11 */
    36. 

  36. #define	MCFSIM_ICR12		(MCF_MBAR + 0x1f)	/* Intr Ctrl reg 12 */
    37. 

  37. #define	MCFSIM_ICR13		(MCF_MBAR + 0x20)	/* Intr Ctrl reg 13 */
    38. 

  38. #ifdef CONFIG_M5206e
    39. 

  39. #define	MCFSIM_ICR14		(MCF_MBAR + 0x21)	/* Intr Ctrl reg 14 */
    40. 

  40. #define	MCFSIM_ICR15		(MCF_MBAR + 0x22)	/* Intr Ctrl reg 15 */
    41. 

  41. #endif
    42. 

  42. 

  43. #define	MCFSIM_IMR		(MCF_MBAR + 0x36)	/* Interrupt Mask */
    44. 

  44. #define	MCFSIM_IPR		(MCF_MBAR + 0x3a)	/* Interrupt Pending */
    45. 

  45. 

  46. #define	MCFSIM_RSR		(MCF_MBAR + 0x40)	/* Reset Status */
    47. 

  47. #define	MCFSIM_SYPCR		(MCF_MBAR + 0x41)	/* System Protection */
    48. 

  48. 

  49. #define	MCFSIM_SWIVR		(MCF_MBAR + 0x42)	/* SW Watchdog intr */
    50. 

  50. #define	MCFSIM_SWSR		(MCF_MBAR + 0x43)	/* SW Watchdog srv */
    51. 

  51. 

  52. #define	MCFSIM_DCRR		(MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
    53. 

  53. #define	MCFSIM_DCTR		(MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
    54. 

  54. #define	MCFSIM_DAR0		(MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
    55. 

  55. #define	MCFSIM_DMR0		(MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
    56. 

  56. #define	MCFSIM_DCR0		(MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
    57. 

  57. #define	MCFSIM_DAR1		(MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
    58. 

  58. #define	MCFSIM_DMR1		(MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
    59. 

  59. #define	MCFSIM_DCR1		(MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
    60. 

  60. 

  61. #define	MCFSIM_CSAR0		(MCF_MBAR + 0x64)	/* CS 0 Address reg */
    62. 

  62. #define	MCFSIM_CSMR0		(MCF_MBAR + 0x68)	/* CS 0 Mask reg */
    63. 

  63. #define	MCFSIM_CSCR0		(MCF_MBAR + 0x6e)	/* CS 0 Control reg */
    64. 

  64. #define	MCFSIM_CSAR1		(MCF_MBAR + 0x70)	/* CS 1 Address reg */
    65. 

  65. #define	MCFSIM_CSMR1		(MCF_MBAR + 0x74)	/* CS 1 Mask reg */
    66. 

  66. #define	MCFSIM_CSCR1		(MCF_MBAR + 0x7a)	/* CS 1 Control reg */
    67. 

  67. #define	MCFSIM_CSAR2		(MCF_MBAR + 0x7c)	/* CS 2 Address reg */
    68. 

  68. #define	MCFSIM_CSMR2		(MCF_MBAR + 0x80)	/* CS 2 Mask reg */
    69. 

  69. #define	MCFSIM_CSCR2		(MCF_MBAR + 0x86)	/* CS 2 Control reg */
    70. 

  70. #define	MCFSIM_CSAR3		(MCF_MBAR + 0x88)	/* CS 3 Address reg */
    71. 

  71. #define	MCFSIM_CSMR3		(MCF_MBAR + 0x8c)	/* CS 3 Mask reg */
    72. 

  72. #define	MCFSIM_CSCR3		(MCF_MBAR + 0x92)	/* CS 3 Control reg */
    73. 

  73. #define	MCFSIM_CSAR4		(MCF_MBAR + 0x94)	/* CS 4 Address reg */
    74. 

  74. #define	MCFSIM_CSMR4		(MCF_MBAR + 0x98)	/* CS 4 Mask reg */
    75. 

  75. #define	MCFSIM_CSCR4		(MCF_MBAR + 0x9e)	/* CS 4 Control reg */
    76. 

  76. #define	MCFSIM_CSAR5		(MCF_MBAR + 0xa0)	/* CS 5 Address reg */
    77. 

  77. #define	MCFSIM_CSMR5		(MCF_MBAR + 0xa4)	/* CS 5 Mask reg */
    78. 

  78. #define	MCFSIM_CSCR5		(MCF_MBAR + 0xaa)	/* CS 5 Control reg */
    79. 

  79. #define	MCFSIM_CSAR6		(MCF_MBAR + 0xac)	/* CS 6 Address reg */
    80. 

  80. #define	MCFSIM_CSMR6		(MCF_MBAR + 0xb0)	/* CS 6 Mask reg */
    81. 

  81. #define	MCFSIM_CSCR6		(MCF_MBAR + 0xb6)	/* CS 6 Control reg */
    82. 

  82. #define	MCFSIM_CSAR7		(MCF_MBAR + 0xb8)	/* CS 7 Address reg */
    83. 

  83. #define	MCFSIM_CSMR7		(MCF_MBAR + 0xbc)	/* CS 7 Mask reg */
    84. 

  84. #define	MCFSIM_CSCR7		(MCF_MBAR + 0xc2)	/* CS 7 Control reg */
    85. 

  85. #define	MCFSIM_DMCR		(MCF_MBAR + 0xc6)	/* Default control */
    86. 

  86. 

  87. #ifdef CONFIG_M5206e
    88. 

  88. #define	MCFSIM_PAR		(MCF_MBAR + 0xca)	/* Pin Assignment */
    89. 

  89. #else
    90. 

  90. #define	MCFSIM_PAR		(MCF_MBAR + 0xcb)	/* Pin Assignment */
    91. 

  91. #endif
    92. 

  92. 

  93. #define	MCFTIMER_BASE1		(MCF_MBAR + 0x100)	/* Base of TIMER1 */
    94. 

  94. #define	MCFTIMER_BASE2		(MCF_MBAR + 0x120)	/* Base of TIMER2 */
    95. 

  95. 

  96. #define	MCFSIM_PADDR		(MCF_MBAR + 0x1c5)	/* Parallel Direction (r/w) */
    97. 

  97. #define	MCFSIM_PADAT		(MCF_MBAR + 0x1c9)	/* Parallel Port Value (r/w) */
    98. 

  98. 

  99. #define	MCFDMA_BASE0		(MCF_MBAR + 0x200)	/* Base address DMA 0 */
    100. 

  100. #define	MCFDMA_BASE1		(MCF_MBAR + 0x240)	/* Base address DMA 1 */
    101. 

  101. 

  102. #if defined(CONFIG_NETtel)
    103. 

  103. #define	MCFUART_BASE0		(MCF_MBAR + 0x180)	/* Base address UART0 */
    104. 

  104. #define	MCFUART_BASE1		(MCF_MBAR + 0x140)	/* Base address UART1 */
    105. 

  105. #else
    106. 

  106. #define	MCFUART_BASE0		(MCF_MBAR + 0x140)	/* Base address UART0 */
    107. 

  107. #define	MCFUART_BASE1		(MCF_MBAR + 0x180)	/* Base address UART1 */
    108. 

  108. #endif
    109. 

  109. 

  110. /*
    111. 

  111.  *	Define system peripheral IRQ usage.
    112. 

  112.  */
    113. 

  113. #define	MCF_IRQ_TIMER		30		/* Timer0, Level 6 */
    114. 

  114. #define	MCF_IRQ_PROFILER	31		/* Timer1, Level 7 */
    115. 

  115. #define	MCF_IRQ_UART0		73		/* UART0 */
    116. 

  116. #define	MCF_IRQ_UART1		74		/* UART1 */
    117. 

  117. 

  118. /*
    119. 

  119.  *	Generic GPIO
    120. 

  120.  */
    121. 

  121. #define MCFGPIO_PIN_MAX		8
    122. 

  122. #define MCFGPIO_IRQ_VECBASE	-1
    123. 

  123. #define MCFGPIO_IRQ_MAX		-1
    124. 

  124. 

  125. /*
    126. 

  126.  *	Some symbol defines for the Parallel Port Pin Assignment Register
    127. 

  127.  */
    128. 

  128. #ifdef CONFIG_M5206e
    129. 

  129. #define MCFSIM_PAR_DREQ0        0x100           /* Set to select DREQ0 input */
    130. 

  130.                                                 /* Clear to select T0 input */
    131. 

  131. #define MCFSIM_PAR_DREQ1        0x200           /* Select DREQ1 input */
    132. 

  132.                                                 /* Clear to select T0 output */
    133. 

  133. #endif
    134. 

  134. 

  135. /*
    136. 

  136.  *	Some symbol defines for the Interrupt Control Register
    137. 

  137.  */
    138. 

  138. #define	MCFSIM_SWDICR		MCFSIM_ICR8	/* Watchdog timer ICR */
    139. 

  139. #define	MCFSIM_TIMER1ICR	MCFSIM_ICR9	/* Timer 1 ICR */
    140. 

  140. #define	MCFSIM_TIMER2ICR	MCFSIM_ICR10	/* Timer 2 ICR */
    141. 

  141. #define	MCFSIM_UART1ICR		MCFSIM_ICR12	/* UART 1 ICR */
    142. 

  142. #define	MCFSIM_UART2ICR		MCFSIM_ICR13	/* UART 2 ICR */
    143. 

  143. #ifdef CONFIG_M5206e
    144. 

  144. #define	MCFSIM_DMA1ICR		MCFSIM_ICR14	/* DMA 1 ICR */
    145. 

  145. #define	MCFSIM_DMA2ICR		MCFSIM_ICR15	/* DMA 2 ICR */
    146. 

  146. #endif
    147. 

  147. 

  148. /****************************************************************************/
    149. 

  149. #endif	/* m5206sim_h */
    150. 

  150.