exynos_dp.txt 3.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121
  1. The Exynos display port interface should be configured based on
  2. the type of panel connected to it.
  3. We use two nodes:
  4. -dp-controller node
  5. -dptx-phy node(defined inside dp-controller node)
  6. For the DP-PHY initialization, we use the dptx-phy node.
  7. Required properties for dptx-phy: deprecated, use phys and phy-names
  8. -reg: deprecated
  9. Base address of DP PHY register.
  10. -samsung,enable-mask: deprecated
  11. The bit-mask used to enable/disable DP PHY.
  12. For the Panel initialization, we read data from dp-controller node.
  13. Required properties for dp-controller:
  14. -compatible:
  15. should be "samsung,exynos5-dp".
  16. -reg:
  17. physical base address of the controller and length
  18. of memory mapped region.
  19. -interrupts:
  20. interrupt combiner values.
  21. -clocks:
  22. from common clock binding: handle to dp clock.
  23. -clock-names:
  24. from common clock binding: Shall be "dp".
  25. -interrupt-parent:
  26. phandle to Interrupt combiner node.
  27. -phys:
  28. from general PHY binding: the phandle for the PHY device.
  29. -phy-names:
  30. from general PHY binding: Should be "dp".
  31. -samsung,color-space:
  32. input video data format.
  33. COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
  34. -samsung,dynamic-range:
  35. dynamic range for input video data.
  36. VESA = 0, CEA = 1
  37. -samsung,ycbcr-coeff:
  38. YCbCr co-efficients for input video.
  39. COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
  40. -samsung,color-depth:
  41. number of bits per colour component.
  42. COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
  43. -samsung,link-rate:
  44. link rate supported by the panel.
  45. LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
  46. -samsung,lane-count:
  47. number of lanes supported by the panel.
  48. LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
  49. - display-timings: timings for the connected panel as described by
  50. Documentation/devicetree/bindings/video/display-timing.txt
  51. Optional properties for dp-controller:
  52. -interlaced:
  53. interlace scan mode.
  54. Progressive if defined, Interlaced if not defined
  55. -vsync-active-high:
  56. VSYNC polarity configuration.
  57. High if defined, Low if not defined
  58. -hsync-active-high:
  59. HSYNC polarity configuration.
  60. High if defined, Low if not defined
  61. -samsung,hpd-gpio:
  62. Hotplug detect GPIO.
  63. Indicates which GPIO should be used for hotplug
  64. detection
  65. -video interfaces: Device node can contain video interface port
  66. nodes according to [1].
  67. [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
  68. Example:
  69. SOC specific portion:
  70. dp-controller {
  71. compatible = "samsung,exynos5-dp";
  72. reg = <0x145b0000 0x10000>;
  73. interrupts = <10 3>;
  74. interrupt-parent = <&combiner>;
  75. clocks = <&clock 342>;
  76. clock-names = "dp";
  77. phys = <&dp_phy>;
  78. phy-names = "dp";
  79. };
  80. Board Specific portion:
  81. dp-controller {
  82. samsung,color-space = <0>;
  83. samsung,dynamic-range = <0>;
  84. samsung,ycbcr-coeff = <0>;
  85. samsung,color-depth = <1>;
  86. samsung,link-rate = <0x0a>;
  87. samsung,lane-count = <4>;
  88. display-timings {
  89. native-mode = <&lcd_timing>;
  90. lcd_timing: 1366x768 {
  91. clock-frequency = <70589280>;
  92. hactive = <1366>;
  93. vactive = <768>;
  94. hfront-porch = <40>;
  95. hback-porch = <40>;
  96. hsync-len = <32>;
  97. vback-porch = <10>;
  98. vfront-porch = <12>;
  99. vsync-len = <6>;
  100. };
  101. };
  102. ports {
  103. port@0 {
  104. dp_out: endpoint {
  105. remote-endpoint = <&bridge_in>;
  106. };
  107. };
  108. };
  109. };