awlsim/tests/100-instructions/insn_SV.awl

ORGANIZATION_BLOCK OB 1
BEGIN

	// Start timer and let it expire
	__STWRST
	L		0
	SV		T 10
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	SET
	L		W#16#0010
	SV		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT>=	__ACCU 1,	5
	__SLEEP		101
	U		T 10
	__ASSERT==	__STW VKE,	0
	L		T 10
	__ASSERT==	__ACCU 1,	0


	// Start timer and reset VKE before it expires
	__STWRST
	L		0
	SV		T 10
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	SET
	L		W#16#0010
	SV		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT>=	__ACCU 1,	5
	CLR
	L		W#16#0010
	SV		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT>=	__ACCU 1,	5
	__SLEEP		101
	U		T 10
	__ASSERT==	__STW VKE,	0
	L		T 10
	__ASSERT==	__ACCU 1,	0


	// Reset signal
	__STWRST
	L		0
	SV		T 10
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	SET
	L		W#16#0010
	SV		T 10
	U		T 10
	__ASSERT==	__STW VKE,	1
	L		T 10
	__ASSERT>=	__ACCU 1,	5
	SET
	R		T 10
	U		T 10
	__ASSERT==	__STW VKE,	0
	L		T 10
	__ASSERT==	__ACCU 1,	0
	__SLEEP		101
	U		T 10
	__ASSERT==	__STW VKE,	0
	L		T 10
	__ASSERT==	__ACCU 1,	0


	// Test FR.
	// Always run SV with VKE=1. The preceding FR shall trigger an edge detect in SV.
	// Thus a re-trigger in SV shall happen -> timer shall not expire.
	__STWRST
	SET
	L		W#16#0010
	SV		T 11
	__SLEEP		50
	L		T 11
	__ASSERT>=	__ACCU 1,	1
	SET
	FR		T 11
	CLR
	FR		T 11
	SET
	L		W#16#0010
	SV		T 11
	__SLEEP		50
	L		T 11
	__ASSERT>=	__ACCU 1,	1
	SET
	FR		T 11
	CLR
	FR		T 11
	SET
	L		W#16#0010
	SV		T 11
	__SLEEP		50
	L		T 11
	__ASSERT>=	__ACCU 1,	1
	SET
	FR		T 11
	CLR
	FR		T 11
	SET
	L		W#16#0010
	SV		T 11
	__SLEEP		50
	L		T 11
	__ASSERT>=	__ACCU 1,	1


	// Test FR without FR edge (VKE at FR is always 1).
	// Always run SV with VKE=1. The timer shall not be retriggerd.
	__STWRST
	SET
	L		W#16#0010
	SV		T 12
	__SLEEP		50
	L		T 12
	__ASSERT>=	__ACCU 1,	1
	SET
	FR		T 12
	SET
	L		W#16#0010
	SV		T 12
	__SLEEP		50
	SET
	FR		T 12
	SET
	L		W#16#0010
	SV		T 12
	__SLEEP		50
	SET
	FR		T 12
	SET
	L		W#16#0010
	SV		T 12
	__SLEEP		50
	L		T 12
	__ASSERT==	__ACCU 1,	0


	// Test timer parameter
	AUF		DB 1
	L		DBW 0
	__ASSERT==	__ACCU 1,	24
	CALL FB 1, DB 1 (
		TIMER_VAR	:= T 42
	)


	CALL SFC 46 // STOP CPU
END_ORGANIZATION_BLOCK


FUNCTION_BLOCK FB 1
	VAR_INPUT
		TIMER_VAR	: TIMER;
	END_VAR
BEGIN
	L		DIW 0
	__ASSERT==	__ACCU 1,	42
	L		#TIMER_VAR
	__ASSERT==	__ACCU 1,	0
	U		#TIMER_VAR
	__ASSERT==	__STW VKE,	0

	SV		#TIMER_VAR
END_FUNCTION_BLOCK


DATA_BLOCK DB 1
	FB 1
BEGIN
	TIMER_VAR	:= T 24;
END_DATA_BLOCK