anypointer.awl 9.5 KB

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  1. ORGANIZATION_BLOCK OB 1
  2. BEGIN
  3. // Check ANY pointer parameters
  4. CALL FC 1 (
  5. FCANY1 := P#M 10.0 BYTE 7,
  6. FCANY2 := P#M 11.1 BOOL 13,
  7. FCANY3 := M 12.2,
  8. FCANY4 := P#DB50.DBX 10.0 DWORD 8,
  9. FCANY5 := DB50.DBD 10,
  10. FCANY6 := P#DBX 20.2 WORD 7,
  11. FCANY7 := DB100.DBVAR2[2].V2,
  12. FCANY8 := P#DB100.DBVAR2[2].V2, // awlsim extension
  13. FCANY9 := P#DB100.DBVAR3, // awlsim extension
  14. FCANY10 := P#DB100.DBVAR4, // awlsim extension
  15. FCOUTANY1 := M 98.1,
  16. RET_VAL := A 97.6,
  17. )
  18. CALL FB 1, DB 1 (
  19. FBANY1 := P#M 10.0 BYTE 7,
  20. FBANY2 := P#M 11.1 BOOL 13,
  21. FBANY3 := M 12.2,
  22. FBANY4 := P#DB50.DBX 10.0 DWORD 8,
  23. FBANY5 := DB50.DBD 10,
  24. FBANY6 := P#DBX 20.2 WORD 7,
  25. FBANY7 := DB100.DBVAR2[2].V2,
  26. FBANY8 := P#DB100.DBVAR2[2].V2, // awlsim extension
  27. FBANY9 := P#DB100.DBVAR3, // awlsim extension
  28. FBANY10 := P#DB100.DBVAR4, // awlsim extension
  29. )
  30. CALL SFC 46 // STOP CPU
  31. END_ORGANIZATION_BLOCK
  32. DATA_BLOCK DB 100
  33. STRUCT
  34. DBVAR1 : INT;
  35. DBVAR2 : ARRAY[1 .. 6] of STRUCT
  36. V1 : INT;
  37. V2 : INT;
  38. END_STRUCT;
  39. DBVAR3 : ARRAY[1 .. 4] of STRUCT
  40. A1 : INT;
  41. END_STRUCT
  42. DBVAR4 : ARRAY[1 .. 8] of BYTE;
  43. END_STRUCT;
  44. BEGIN
  45. END_DATA_BLOCK
  46. FUNCTION FC 1 : ANY
  47. VAR_INPUT
  48. FCANY1 : ANY;
  49. FCANY2 : ANY;
  50. FCANY3 : ANY;
  51. FCANY4 : ANY;
  52. FCANY5 : ANY;
  53. FCANY6 : ANY;
  54. FCANY7 : ANY;
  55. FCANY8 : ANY;
  56. FCANY9 : ANY;
  57. FCANY10 : ANY;
  58. END_VAR
  59. VAR_OUTPUT
  60. FCOUTANY1 : ANY;
  61. END_VAR
  62. BEGIN
  63. L P##FCANY1
  64. LAR1
  65. UD DW#16#FF000000
  66. __ASSERT== __ACCU 1, DW#16#87000000
  67. L B [AR1, P#0.0]
  68. __ASSERT== __ACCU 1, B#16#10 // S7
  69. L B [AR1, P#1.0]
  70. __ASSERT== __ACCU 1, B#16#02 // BYTE
  71. L W [AR1, P#2.0]
  72. __ASSERT== __ACCU 1, 7 // count
  73. L W [AR1, P#4.0]
  74. __ASSERT== __ACCU 1, 0 // DB
  75. L D [AR1, P#6.0]
  76. __ASSERT== __ACCU 1, P#M 10.0
  77. L P##FCANY2
  78. LAR1
  79. UD DW#16#FF000000
  80. __ASSERT== __ACCU 1, DW#16#87000000
  81. L B [AR1, P#0.0]
  82. __ASSERT== __ACCU 1, B#16#10 // S7
  83. L B [AR1, P#1.0]
  84. __ASSERT== __ACCU 1, B#16#01 // BOOL
  85. L W [AR1, P#2.0]
  86. __ASSERT== __ACCU 1, 13 // count
  87. L W [AR1, P#4.0]
  88. __ASSERT== __ACCU 1, 0 // DB
  89. L D [AR1, P#6.0]
  90. __ASSERT== __ACCU 1, P#M 11.1
  91. L P##FCANY3
  92. LAR1
  93. UD DW#16#FF000000
  94. __ASSERT== __ACCU 1, DW#16#87000000
  95. L B [AR1, P#0.0]
  96. __ASSERT== __ACCU 1, B#16#10 // S7
  97. L B [AR1, P#1.0]
  98. __ASSERT== __ACCU 1, B#16#01 // BOOL
  99. L W [AR1, P#2.0]
  100. __ASSERT== __ACCU 1, 1 // count
  101. L W [AR1, P#4.0]
  102. __ASSERT== __ACCU 1, 0 // DB
  103. L D [AR1, P#6.0]
  104. __ASSERT== __ACCU 1, P#M 12.2
  105. L P##FCANY4
  106. LAR1
  107. UD DW#16#FF000000
  108. __ASSERT== __ACCU 1, DW#16#87000000
  109. L B [AR1, P#0.0]
  110. __ASSERT== __ACCU 1, B#16#10 // S7
  111. L B [AR1, P#1.0]
  112. __ASSERT== __ACCU 1, B#16#06 // DWORD
  113. L W [AR1, P#2.0]
  114. __ASSERT== __ACCU 1, 8 // count
  115. L W [AR1, P#4.0]
  116. __ASSERT== __ACCU 1, 50 // DB
  117. L D [AR1, P#6.0]
  118. __ASSERT== __ACCU 1, P#DBX 10.0
  119. L P##FCANY5
  120. LAR1
  121. UD DW#16#FF000000
  122. __ASSERT== __ACCU 1, DW#16#87000000
  123. L B [AR1, P#0.0]
  124. __ASSERT== __ACCU 1, B#16#10 // S7
  125. L B [AR1, P#1.0]
  126. __ASSERT== __ACCU 1, B#16#06 // DWORD
  127. L W [AR1, P#2.0]
  128. __ASSERT== __ACCU 1, 1 // count
  129. L W [AR1, P#4.0]
  130. __ASSERT== __ACCU 1, 50 // DB
  131. L D [AR1, P#6.0]
  132. __ASSERT== __ACCU 1, P#DBX 10.0
  133. L P##FCANY6
  134. LAR1
  135. UD DW#16#FF000000
  136. __ASSERT== __ACCU 1, DW#16#87000000
  137. L B [AR1, P#0.0]
  138. __ASSERT== __ACCU 1, B#16#10 // S7
  139. L B [AR1, P#1.0]
  140. __ASSERT== __ACCU 1, B#16#04 // WORD
  141. L W [AR1, P#2.0]
  142. __ASSERT== __ACCU 1, 7 // count
  143. L W [AR1, P#4.0]
  144. __ASSERT== __ACCU 1, 0 // DB
  145. L D [AR1, P#6.0]
  146. __ASSERT== __ACCU 1, P#DBX 20.2
  147. L P##FCANY7
  148. LAR1
  149. UD DW#16#FF000000
  150. __ASSERT== __ACCU 1, DW#16#87000000
  151. L B [AR1, P#0.0]
  152. __ASSERT== __ACCU 1, B#16#10 // S7
  153. L B [AR1, P#1.0]
  154. __ASSERT== __ACCU 1, B#16#05 // INT
  155. L W [AR1, P#2.0]
  156. __ASSERT== __ACCU 1, 1 // count
  157. L W [AR1, P#4.0]
  158. __ASSERT== __ACCU 1, 100 // DB
  159. L D [AR1, P#6.0]
  160. __ASSERT== __ACCU 1, P#DBX 8.0
  161. L P##FCANY8
  162. LAR1
  163. UD DW#16#FF000000
  164. __ASSERT== __ACCU 1, DW#16#87000000
  165. L B [AR1, P#0.0]
  166. __ASSERT== __ACCU 1, B#16#10 // S7
  167. L B [AR1, P#1.0]
  168. __ASSERT== __ACCU 1, B#16#05 // INT
  169. L W [AR1, P#2.0]
  170. __ASSERT== __ACCU 1, 1 // count
  171. L W [AR1, P#4.0]
  172. __ASSERT== __ACCU 1, 100 // DB
  173. L D [AR1, P#6.0]
  174. __ASSERT== __ACCU 1, P#DBX 8.0
  175. L P##FCANY9
  176. LAR1
  177. UD DW#16#FF000000
  178. __ASSERT== __ACCU 1, DW#16#87000000
  179. L B [AR1, P#0.0]
  180. __ASSERT== __ACCU 1, B#16#10 // S7
  181. L B [AR1, P#1.0]
  182. __ASSERT== __ACCU 1, B#16#06 // DWORD
  183. L W [AR1, P#2.0]
  184. __ASSERT== __ACCU 1, 2 // count
  185. L W [AR1, P#4.0]
  186. __ASSERT== __ACCU 1, 100 // DB
  187. L D [AR1, P#6.0]
  188. __ASSERT== __ACCU 1, P#DBX 26.0
  189. L P##FCANY10
  190. LAR1
  191. UD DW#16#FF000000
  192. __ASSERT== __ACCU 1, DW#16#87000000
  193. L B [AR1, P#0.0]
  194. __ASSERT== __ACCU 1, B#16#10 // S7
  195. L B [AR1, P#1.0]
  196. __ASSERT== __ACCU 1, B#16#02 // BYTE
  197. L W [AR1, P#2.0]
  198. __ASSERT== __ACCU 1, 8 // count
  199. L W [AR1, P#4.0]
  200. __ASSERT== __ACCU 1, 100 // DB
  201. L D [AR1, P#6.0]
  202. __ASSERT== __ACCU 1, P#DBX 34.0
  203. L P##FCOUTANY1
  204. LAR1
  205. UD DW#16#FF000000
  206. __ASSERT== __ACCU 1, DW#16#87000000
  207. L B [AR1, P#0.0]
  208. __ASSERT== __ACCU 1, B#16#10 // S7
  209. L B [AR1, P#1.0]
  210. __ASSERT== __ACCU 1, B#16#01 // BOOL
  211. L W [AR1, P#2.0]
  212. __ASSERT== __ACCU 1, 1 // count
  213. L W [AR1, P#4.0]
  214. __ASSERT== __ACCU 1, 0 // DB
  215. L D [AR1, P#6.0]
  216. __ASSERT== __ACCU 1, P#M 98.1
  217. L P##RET_VAL
  218. LAR1
  219. UD DW#16#FF000000
  220. __ASSERT== __ACCU 1, DW#16#87000000
  221. L B [AR1, P#0.0]
  222. __ASSERT== __ACCU 1, B#16#10 // S7
  223. L B [AR1, P#1.0]
  224. __ASSERT== __ACCU 1, B#16#01 // BOOL
  225. L W [AR1, P#2.0]
  226. __ASSERT== __ACCU 1, 1 // count
  227. L W [AR1, P#4.0]
  228. __ASSERT== __ACCU 1, 0 // DB
  229. L D [AR1, P#6.0]
  230. __ASSERT== __ACCU 1, P#A 97.6
  231. END_FUNCTION
  232. FUNCTION_BLOCK FB 1
  233. VAR_INPUT
  234. FBANY1 : ANY;
  235. FBANY2 : ANY;
  236. FBANY3 : ANY;
  237. FBANY4 : ANY;
  238. FBANY5 : ANY;
  239. FBANY6 : ANY;
  240. FBANY7 : ANY;
  241. FBANY8 : ANY;
  242. FBANY9 : ANY;
  243. FBANY10 : ANY;
  244. END_VAR
  245. BEGIN
  246. L P##FBANY1
  247. LAR1
  248. UD DW#16#FF000000
  249. __ASSERT== __ACCU 1, DW#16#85000000
  250. L B [AR1, P#0.0]
  251. __ASSERT== __ACCU 1, B#16#10 // S7
  252. L B [AR1, P#1.0]
  253. __ASSERT== __ACCU 1, B#16#02 // BYTE
  254. L W [AR1, P#2.0]
  255. __ASSERT== __ACCU 1, 7 // count
  256. L W [AR1, P#4.0]
  257. __ASSERT== __ACCU 1, 0 // DB
  258. L D [AR1, P#6.0]
  259. __ASSERT== __ACCU 1, P#M 10.0
  260. L P##FBANY2
  261. LAR1
  262. UD DW#16#FF000000
  263. __ASSERT== __ACCU 1, DW#16#85000000
  264. L B [AR1, P#0.0]
  265. __ASSERT== __ACCU 1, B#16#10 // S7
  266. L B [AR1, P#1.0]
  267. __ASSERT== __ACCU 1, B#16#01 // BOOL
  268. L W [AR1, P#2.0]
  269. __ASSERT== __ACCU 1, 13 // count
  270. L W [AR1, P#4.0]
  271. __ASSERT== __ACCU 1, 0 // DB
  272. L D [AR1, P#6.0]
  273. __ASSERT== __ACCU 1, P#M 11.1
  274. L P##FBANY3
  275. LAR1
  276. UD DW#16#FF000000
  277. __ASSERT== __ACCU 1, DW#16#85000000
  278. L B [AR1, P#0.0]
  279. __ASSERT== __ACCU 1, B#16#10 // S7
  280. L B [AR1, P#1.0]
  281. __ASSERT== __ACCU 1, B#16#01 // BOOL
  282. L W [AR1, P#2.0]
  283. __ASSERT== __ACCU 1, 1 // count
  284. L W [AR1, P#4.0]
  285. __ASSERT== __ACCU 1, 0 // DB
  286. L D [AR1, P#6.0]
  287. __ASSERT== __ACCU 1, P#M 12.2
  288. L P##FBANY4
  289. LAR1
  290. UD DW#16#FF000000
  291. __ASSERT== __ACCU 1, DW#16#85000000
  292. L B [AR1, P#0.0]
  293. __ASSERT== __ACCU 1, B#16#10 // S7
  294. L B [AR1, P#1.0]
  295. __ASSERT== __ACCU 1, B#16#06 // DWORD
  296. L W [AR1, P#2.0]
  297. __ASSERT== __ACCU 1, 8 // count
  298. L W [AR1, P#4.0]
  299. __ASSERT== __ACCU 1, 50 // DB
  300. L D [AR1, P#6.0]
  301. __ASSERT== __ACCU 1, P#DBX 10.0
  302. L P##FBANY5
  303. LAR1
  304. UD DW#16#FF000000
  305. __ASSERT== __ACCU 1, DW#16#85000000
  306. L B [AR1, P#0.0]
  307. __ASSERT== __ACCU 1, B#16#10 // S7
  308. L B [AR1, P#1.0]
  309. __ASSERT== __ACCU 1, B#16#06 // DWORD
  310. L W [AR1, P#2.0]
  311. __ASSERT== __ACCU 1, 1 // count
  312. L W [AR1, P#4.0]
  313. __ASSERT== __ACCU 1, 50 // DB
  314. L D [AR1, P#6.0]
  315. __ASSERT== __ACCU 1, P#DBX 10.0
  316. L P##FBANY6
  317. LAR1
  318. UD DW#16#FF000000
  319. __ASSERT== __ACCU 1, DW#16#85000000
  320. L B [AR1, P#0.0]
  321. __ASSERT== __ACCU 1, B#16#10 // S7
  322. L B [AR1, P#1.0]
  323. __ASSERT== __ACCU 1, B#16#04 // WORD
  324. L W [AR1, P#2.0]
  325. __ASSERT== __ACCU 1, 7 // count
  326. L W [AR1, P#4.0]
  327. __ASSERT== __ACCU 1, 0 // DB
  328. L D [AR1, P#6.0]
  329. __ASSERT== __ACCU 1, P#DBX 20.2
  330. L P##FBANY7
  331. LAR1
  332. UD DW#16#FF000000
  333. __ASSERT== __ACCU 1, DW#16#85000000
  334. L B [AR1, P#0.0]
  335. __ASSERT== __ACCU 1, B#16#10 // S7
  336. L B [AR1, P#1.0]
  337. __ASSERT== __ACCU 1, B#16#05 // INT
  338. L W [AR1, P#2.0]
  339. __ASSERT== __ACCU 1, 1 // count
  340. L W [AR1, P#4.0]
  341. __ASSERT== __ACCU 1, 100 // DB
  342. L D [AR1, P#6.0]
  343. __ASSERT== __ACCU 1, P#DBX 8.0
  344. L P##FBANY8
  345. LAR1
  346. UD DW#16#FF000000
  347. __ASSERT== __ACCU 1, DW#16#85000000
  348. L B [AR1, P#0.0]
  349. __ASSERT== __ACCU 1, B#16#10 // S7
  350. L B [AR1, P#1.0]
  351. __ASSERT== __ACCU 1, B#16#05 // INT
  352. L W [AR1, P#2.0]
  353. __ASSERT== __ACCU 1, 1 // count
  354. L W [AR1, P#4.0]
  355. __ASSERT== __ACCU 1, 100 // DB
  356. L D [AR1, P#6.0]
  357. __ASSERT== __ACCU 1, P#DBX 8.0
  358. L P##FBANY9
  359. LAR1
  360. UD DW#16#FF000000
  361. __ASSERT== __ACCU 1, DW#16#85000000
  362. L B [AR1, P#0.0]
  363. __ASSERT== __ACCU 1, B#16#10 // S7
  364. L B [AR1, P#1.0]
  365. __ASSERT== __ACCU 1, B#16#06 // DWORD
  366. L W [AR1, P#2.0]
  367. __ASSERT== __ACCU 1, 2 // count
  368. L W [AR1, P#4.0]
  369. __ASSERT== __ACCU 1, 100 // DB
  370. L D [AR1, P#6.0]
  371. __ASSERT== __ACCU 1, P#DBX 26.0
  372. L P##FBANY10
  373. LAR1
  374. UD DW#16#FF000000
  375. __ASSERT== __ACCU 1, DW#16#85000000
  376. L B [AR1, P#0.0]
  377. __ASSERT== __ACCU 1, B#16#10 // S7
  378. L B [AR1, P#1.0]
  379. __ASSERT== __ACCU 1, B#16#02 // BYTE
  380. L W [AR1, P#2.0]
  381. __ASSERT== __ACCU 1, 8 // count
  382. L W [AR1, P#4.0]
  383. __ASSERT== __ACCU 1, 100 // DB
  384. L D [AR1, P#6.0]
  385. __ASSERT== __ACCU 1, P#DBX 34.0
  386. END_FUNCTION_BLOCK
  387. DATA_BLOCK DB 1
  388. FB 1
  389. BEGIN
  390. END_DATA_BLOCK