sp805_wdt.c 8.7 KB

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  1. /*
  2. * drivers/char/watchdog/sp805-wdt.c
  3. *
  4. * Watchdog driver for ARM SP805 watchdog module
  5. *
  6. * Copyright (C) 2010 ST Microelectronics
  7. * Viresh Kumar <vireshk@kernel.org>
  8. *
  9. * This file is licensed under the terms of the GNU General Public
  10. * License version 2 or later. This program is licensed "as is" without any
  11. * warranty of any kind, whether express or implied.
  12. */
  13. #include <linux/acpi.h>
  14. #include <linux/device.h>
  15. #include <linux/resource.h>
  16. #include <linux/amba/bus.h>
  17. #include <linux/bitops.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/ioport.h>
  21. #include <linux/kernel.h>
  22. #include <linux/math64.h>
  23. #include <linux/module.h>
  24. #include <linux/moduleparam.h>
  25. #include <linux/of.h>
  26. #include <linux/pm.h>
  27. #include <linux/slab.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/types.h>
  30. #include <linux/watchdog.h>
  31. /* default timeout in seconds */
  32. #define DEFAULT_TIMEOUT 60
  33. #define MODULE_NAME "sp805-wdt"
  34. /* watchdog register offsets and masks */
  35. #define WDTLOAD 0x000
  36. #define LOAD_MIN 0x00000001
  37. #define LOAD_MAX 0xFFFFFFFF
  38. #define WDTVALUE 0x004
  39. #define WDTCONTROL 0x008
  40. /* control register masks */
  41. #define INT_ENABLE (1 << 0)
  42. #define RESET_ENABLE (1 << 1)
  43. #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
  44. #define WDTINTCLR 0x00C
  45. #define WDTRIS 0x010
  46. #define WDTMIS 0x014
  47. #define INT_MASK (1 << 0)
  48. #define WDTLOCK 0xC00
  49. #define UNLOCK 0x1ACCE551
  50. #define LOCK 0x00000001
  51. /**
  52. * struct sp805_wdt: sp805 wdt device structure
  53. * @wdd: instance of struct watchdog_device
  54. * @lock: spin lock protecting dev structure and io access
  55. * @base: base address of wdt
  56. * @clk: clock structure of wdt
  57. * @adev: amba device structure of wdt
  58. * @status: current status of wdt
  59. * @load_val: load value to be set for current timeout
  60. */
  61. struct sp805_wdt {
  62. struct watchdog_device wdd;
  63. spinlock_t lock;
  64. void __iomem *base;
  65. struct clk *clk;
  66. u64 rate;
  67. struct amba_device *adev;
  68. unsigned int load_val;
  69. };
  70. static bool nowayout = WATCHDOG_NOWAYOUT;
  71. module_param(nowayout, bool, 0);
  72. MODULE_PARM_DESC(nowayout,
  73. "Set to 1 to keep watchdog running after device release");
  74. /* returns true if wdt is running; otherwise returns false */
  75. static bool wdt_is_running(struct watchdog_device *wdd)
  76. {
  77. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  78. u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
  79. return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
  80. }
  81. /* This routine finds load value that will reset system in required timout */
  82. static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
  83. {
  84. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  85. u64 load, rate;
  86. rate = wdt->rate;
  87. /*
  88. * sp805 runs counter with given value twice, after the end of first
  89. * counter it gives an interrupt and then starts counter again. If
  90. * interrupt already occurred then it resets the system. This is why
  91. * load is half of what should be required.
  92. */
  93. load = div_u64(rate, 2) * timeout - 1;
  94. load = (load > LOAD_MAX) ? LOAD_MAX : load;
  95. load = (load < LOAD_MIN) ? LOAD_MIN : load;
  96. spin_lock(&wdt->lock);
  97. wdt->load_val = load;
  98. /* roundup timeout to closest positive integer value */
  99. wdd->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
  100. spin_unlock(&wdt->lock);
  101. return 0;
  102. }
  103. /* returns number of seconds left for reset to occur */
  104. static unsigned int wdt_timeleft(struct watchdog_device *wdd)
  105. {
  106. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  107. u64 load;
  108. spin_lock(&wdt->lock);
  109. load = readl_relaxed(wdt->base + WDTVALUE);
  110. /*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
  111. if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
  112. load += wdt->load_val + 1;
  113. spin_unlock(&wdt->lock);
  114. return div_u64(load, wdt->rate);
  115. }
  116. static int
  117. wdt_restart(struct watchdog_device *wdd, unsigned long mode, void *cmd)
  118. {
  119. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  120. writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
  121. writel_relaxed(0, wdt->base + WDTCONTROL);
  122. writel_relaxed(0, wdt->base + WDTLOAD);
  123. writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
  124. /* Flush posted writes. */
  125. readl_relaxed(wdt->base + WDTLOCK);
  126. return 0;
  127. }
  128. static int wdt_config(struct watchdog_device *wdd, bool ping)
  129. {
  130. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  131. int ret;
  132. if (!ping) {
  133. ret = clk_prepare_enable(wdt->clk);
  134. if (ret) {
  135. dev_err(&wdt->adev->dev, "clock enable fail");
  136. return ret;
  137. }
  138. }
  139. spin_lock(&wdt->lock);
  140. writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
  141. writel_relaxed(wdt->load_val, wdt->base + WDTLOAD);
  142. writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
  143. if (!ping)
  144. writel_relaxed(INT_ENABLE | RESET_ENABLE, wdt->base +
  145. WDTCONTROL);
  146. writel_relaxed(LOCK, wdt->base + WDTLOCK);
  147. /* Flush posted writes. */
  148. readl_relaxed(wdt->base + WDTLOCK);
  149. spin_unlock(&wdt->lock);
  150. return 0;
  151. }
  152. static int wdt_ping(struct watchdog_device *wdd)
  153. {
  154. return wdt_config(wdd, true);
  155. }
  156. /* enables watchdog timers reset */
  157. static int wdt_enable(struct watchdog_device *wdd)
  158. {
  159. return wdt_config(wdd, false);
  160. }
  161. /* disables watchdog timers reset */
  162. static int wdt_disable(struct watchdog_device *wdd)
  163. {
  164. struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
  165. spin_lock(&wdt->lock);
  166. writel_relaxed(UNLOCK, wdt->base + WDTLOCK);
  167. writel_relaxed(0, wdt->base + WDTCONTROL);
  168. writel_relaxed(LOCK, wdt->base + WDTLOCK);
  169. /* Flush posted writes. */
  170. readl_relaxed(wdt->base + WDTLOCK);
  171. spin_unlock(&wdt->lock);
  172. clk_disable_unprepare(wdt->clk);
  173. return 0;
  174. }
  175. static const struct watchdog_info wdt_info = {
  176. .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
  177. .identity = MODULE_NAME,
  178. };
  179. static const struct watchdog_ops wdt_ops = {
  180. .owner = THIS_MODULE,
  181. .start = wdt_enable,
  182. .stop = wdt_disable,
  183. .ping = wdt_ping,
  184. .set_timeout = wdt_setload,
  185. .get_timeleft = wdt_timeleft,
  186. .restart = wdt_restart,
  187. };
  188. static int
  189. sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
  190. {
  191. struct sp805_wdt *wdt;
  192. int ret = 0;
  193. wdt = devm_kzalloc(&adev->dev, sizeof(*wdt), GFP_KERNEL);
  194. if (!wdt) {
  195. ret = -ENOMEM;
  196. goto err;
  197. }
  198. wdt->base = devm_ioremap_resource(&adev->dev, &adev->res);
  199. if (IS_ERR(wdt->base))
  200. return PTR_ERR(wdt->base);
  201. if (adev->dev.of_node) {
  202. wdt->clk = devm_clk_get(&adev->dev, NULL);
  203. if (IS_ERR(wdt->clk)) {
  204. dev_err(&adev->dev, "Clock not found\n");
  205. return PTR_ERR(wdt->clk);
  206. }
  207. wdt->rate = clk_get_rate(wdt->clk);
  208. } else if (has_acpi_companion(&adev->dev)) {
  209. /*
  210. * When Driver probe with ACPI device, clock devices
  211. * are not available, so watchdog rate get from
  212. * clock-frequency property given in _DSD object.
  213. */
  214. device_property_read_u64(&adev->dev, "clock-frequency",
  215. &wdt->rate);
  216. if (!wdt->rate) {
  217. dev_err(&adev->dev, "no clock-frequency property\n");
  218. return -ENODEV;
  219. }
  220. }
  221. wdt->adev = adev;
  222. wdt->wdd.info = &wdt_info;
  223. wdt->wdd.ops = &wdt_ops;
  224. wdt->wdd.parent = &adev->dev;
  225. spin_lock_init(&wdt->lock);
  226. watchdog_set_nowayout(&wdt->wdd, nowayout);
  227. watchdog_set_drvdata(&wdt->wdd, wdt);
  228. watchdog_set_restart_priority(&wdt->wdd, 128);
  229. /*
  230. * If 'timeout-sec' devicetree property is specified, use that.
  231. * Otherwise, use DEFAULT_TIMEOUT
  232. */
  233. wdt->wdd.timeout = DEFAULT_TIMEOUT;
  234. watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
  235. wdt_setload(&wdt->wdd, wdt->wdd.timeout);
  236. /*
  237. * If HW is already running, enable/reset the wdt and set the running
  238. * bit to tell the wdt subsystem
  239. */
  240. if (wdt_is_running(&wdt->wdd)) {
  241. wdt_enable(&wdt->wdd);
  242. set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
  243. }
  244. ret = watchdog_register_device(&wdt->wdd);
  245. if (ret)
  246. goto err;
  247. amba_set_drvdata(adev, wdt);
  248. dev_info(&adev->dev, "registration successful\n");
  249. return 0;
  250. err:
  251. dev_err(&adev->dev, "Probe Failed!!!\n");
  252. return ret;
  253. }
  254. static int sp805_wdt_remove(struct amba_device *adev)
  255. {
  256. struct sp805_wdt *wdt = amba_get_drvdata(adev);
  257. watchdog_unregister_device(&wdt->wdd);
  258. watchdog_set_drvdata(&wdt->wdd, NULL);
  259. return 0;
  260. }
  261. static int __maybe_unused sp805_wdt_suspend(struct device *dev)
  262. {
  263. struct sp805_wdt *wdt = dev_get_drvdata(dev);
  264. if (watchdog_active(&wdt->wdd))
  265. return wdt_disable(&wdt->wdd);
  266. return 0;
  267. }
  268. static int __maybe_unused sp805_wdt_resume(struct device *dev)
  269. {
  270. struct sp805_wdt *wdt = dev_get_drvdata(dev);
  271. if (watchdog_active(&wdt->wdd))
  272. return wdt_enable(&wdt->wdd);
  273. return 0;
  274. }
  275. static SIMPLE_DEV_PM_OPS(sp805_wdt_dev_pm_ops, sp805_wdt_suspend,
  276. sp805_wdt_resume);
  277. static const struct amba_id sp805_wdt_ids[] = {
  278. {
  279. .id = 0x00141805,
  280. .mask = 0x00ffffff,
  281. },
  282. { 0, 0 },
  283. };
  284. MODULE_DEVICE_TABLE(amba, sp805_wdt_ids);
  285. static struct amba_driver sp805_wdt_driver = {
  286. .drv = {
  287. .name = MODULE_NAME,
  288. .pm = &sp805_wdt_dev_pm_ops,
  289. },
  290. .id_table = sp805_wdt_ids,
  291. .probe = sp805_wdt_probe,
  292. .remove = sp805_wdt_remove,
  293. };
  294. module_amba_driver(sp805_wdt_driver);
  295. MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>");
  296. MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
  297. MODULE_LICENSE("GPL");