sama5d4_wdt.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Driver for Atmel SAMA5D4 Watchdog Timer
  4. *
  5. * Copyright (C) 2015 Atmel Corporation
  6. */
  7. #include <linux/delay.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/of.h>
  13. #include <linux/of_irq.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/reboot.h>
  16. #include <linux/watchdog.h>
  17. #include "at91sam9_wdt.h"
  18. /* minimum and maximum watchdog timeout, in seconds */
  19. #define MIN_WDT_TIMEOUT 1
  20. #define MAX_WDT_TIMEOUT 16
  21. #define WDT_DEFAULT_TIMEOUT MAX_WDT_TIMEOUT
  22. #define WDT_SEC2TICKS(s) ((s) ? (((s) << 8) - 1) : 0)
  23. struct sama5d4_wdt {
  24. struct watchdog_device wdd;
  25. void __iomem *reg_base;
  26. u32 mr;
  27. unsigned long last_ping;
  28. };
  29. static int wdt_timeout;
  30. static bool nowayout = WATCHDOG_NOWAYOUT;
  31. module_param(wdt_timeout, int, 0);
  32. MODULE_PARM_DESC(wdt_timeout,
  33. "Watchdog timeout in seconds. (default = "
  34. __MODULE_STRING(WDT_DEFAULT_TIMEOUT) ")");
  35. module_param(nowayout, bool, 0);
  36. MODULE_PARM_DESC(nowayout,
  37. "Watchdog cannot be stopped once started (default="
  38. __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  39. #define wdt_enabled (!(wdt->mr & AT91_WDT_WDDIS))
  40. #define wdt_read(wdt, field) \
  41. readl_relaxed((wdt)->reg_base + (field))
  42. /* 4 slow clock periods is 4/32768 = 122.07µs*/
  43. #define WDT_DELAY usecs_to_jiffies(123)
  44. static void wdt_write(struct sama5d4_wdt *wdt, u32 field, u32 val)
  45. {
  46. /*
  47. * WDT_CR and WDT_MR must not be modified within three slow clock
  48. * periods following a restart of the watchdog performed by a write
  49. * access in WDT_CR.
  50. */
  51. while (time_before(jiffies, wdt->last_ping + WDT_DELAY))
  52. usleep_range(30, 125);
  53. writel_relaxed(val, wdt->reg_base + field);
  54. wdt->last_ping = jiffies;
  55. }
  56. static void wdt_write_nosleep(struct sama5d4_wdt *wdt, u32 field, u32 val)
  57. {
  58. if (time_before(jiffies, wdt->last_ping + WDT_DELAY))
  59. udelay(123);
  60. writel_relaxed(val, wdt->reg_base + field);
  61. wdt->last_ping = jiffies;
  62. }
  63. static int sama5d4_wdt_start(struct watchdog_device *wdd)
  64. {
  65. struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
  66. wdt->mr &= ~AT91_WDT_WDDIS;
  67. wdt_write(wdt, AT91_WDT_MR, wdt->mr);
  68. return 0;
  69. }
  70. static int sama5d4_wdt_stop(struct watchdog_device *wdd)
  71. {
  72. struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
  73. wdt->mr |= AT91_WDT_WDDIS;
  74. wdt_write(wdt, AT91_WDT_MR, wdt->mr);
  75. return 0;
  76. }
  77. static int sama5d4_wdt_ping(struct watchdog_device *wdd)
  78. {
  79. struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
  80. wdt_write(wdt, AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT);
  81. return 0;
  82. }
  83. static int sama5d4_wdt_set_timeout(struct watchdog_device *wdd,
  84. unsigned int timeout)
  85. {
  86. struct sama5d4_wdt *wdt = watchdog_get_drvdata(wdd);
  87. u32 value = WDT_SEC2TICKS(timeout);
  88. wdt->mr &= ~AT91_WDT_WDV;
  89. wdt->mr |= AT91_WDT_SET_WDV(value);
  90. /*
  91. * WDDIS has to be 0 when updating WDD/WDV. The datasheet states: When
  92. * setting the WDDIS bit, and while it is set, the fields WDV and WDD
  93. * must not be modified.
  94. * If the watchdog is enabled, then the timeout can be updated. Else,
  95. * wait that the user enables it.
  96. */
  97. if (wdt_enabled)
  98. wdt_write(wdt, AT91_WDT_MR, wdt->mr & ~AT91_WDT_WDDIS);
  99. wdd->timeout = timeout;
  100. return 0;
  101. }
  102. static const struct watchdog_info sama5d4_wdt_info = {
  103. .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
  104. .identity = "Atmel SAMA5D4 Watchdog",
  105. };
  106. static const struct watchdog_ops sama5d4_wdt_ops = {
  107. .owner = THIS_MODULE,
  108. .start = sama5d4_wdt_start,
  109. .stop = sama5d4_wdt_stop,
  110. .ping = sama5d4_wdt_ping,
  111. .set_timeout = sama5d4_wdt_set_timeout,
  112. };
  113. static irqreturn_t sama5d4_wdt_irq_handler(int irq, void *dev_id)
  114. {
  115. struct sama5d4_wdt *wdt = platform_get_drvdata(dev_id);
  116. if (wdt_read(wdt, AT91_WDT_SR)) {
  117. pr_crit("Atmel Watchdog Software Reset\n");
  118. emergency_restart();
  119. pr_crit("Reboot didn't succeed\n");
  120. }
  121. return IRQ_HANDLED;
  122. }
  123. static int of_sama5d4_wdt_init(struct device_node *np, struct sama5d4_wdt *wdt)
  124. {
  125. const char *tmp;
  126. wdt->mr = AT91_WDT_WDDIS;
  127. if (!of_property_read_string(np, "atmel,watchdog-type", &tmp) &&
  128. !strcmp(tmp, "software"))
  129. wdt->mr |= AT91_WDT_WDFIEN;
  130. else
  131. wdt->mr |= AT91_WDT_WDRSTEN;
  132. if (of_property_read_bool(np, "atmel,idle-halt"))
  133. wdt->mr |= AT91_WDT_WDIDLEHLT;
  134. if (of_property_read_bool(np, "atmel,dbg-halt"))
  135. wdt->mr |= AT91_WDT_WDDBGHLT;
  136. return 0;
  137. }
  138. static int sama5d4_wdt_init(struct sama5d4_wdt *wdt)
  139. {
  140. u32 reg;
  141. /*
  142. * When booting and resuming, the bootloader may have changed the
  143. * watchdog configuration.
  144. * If the watchdog is already running, we can safely update it.
  145. * Else, we have to disable it properly.
  146. */
  147. if (wdt_enabled) {
  148. wdt_write_nosleep(wdt, AT91_WDT_MR, wdt->mr);
  149. } else {
  150. reg = wdt_read(wdt, AT91_WDT_MR);
  151. if (!(reg & AT91_WDT_WDDIS))
  152. wdt_write_nosleep(wdt, AT91_WDT_MR,
  153. reg | AT91_WDT_WDDIS);
  154. }
  155. return 0;
  156. }
  157. static int sama5d4_wdt_probe(struct platform_device *pdev)
  158. {
  159. struct device *dev = &pdev->dev;
  160. struct watchdog_device *wdd;
  161. struct sama5d4_wdt *wdt;
  162. void __iomem *regs;
  163. u32 irq = 0;
  164. u32 timeout;
  165. int ret;
  166. wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
  167. if (!wdt)
  168. return -ENOMEM;
  169. wdd = &wdt->wdd;
  170. wdd->timeout = WDT_DEFAULT_TIMEOUT;
  171. wdd->info = &sama5d4_wdt_info;
  172. wdd->ops = &sama5d4_wdt_ops;
  173. wdd->min_timeout = MIN_WDT_TIMEOUT;
  174. wdd->max_timeout = MAX_WDT_TIMEOUT;
  175. wdt->last_ping = jiffies;
  176. watchdog_set_drvdata(wdd, wdt);
  177. regs = devm_platform_ioremap_resource(pdev, 0);
  178. if (IS_ERR(regs))
  179. return PTR_ERR(regs);
  180. wdt->reg_base = regs;
  181. irq = irq_of_parse_and_map(dev->of_node, 0);
  182. if (!irq)
  183. dev_warn(dev, "failed to get IRQ from DT\n");
  184. ret = of_sama5d4_wdt_init(dev->of_node, wdt);
  185. if (ret)
  186. return ret;
  187. if ((wdt->mr & AT91_WDT_WDFIEN) && irq) {
  188. ret = devm_request_irq(dev, irq, sama5d4_wdt_irq_handler,
  189. IRQF_SHARED | IRQF_IRQPOLL |
  190. IRQF_NO_SUSPEND, pdev->name, pdev);
  191. if (ret) {
  192. dev_err(dev, "cannot register interrupt handler\n");
  193. return ret;
  194. }
  195. }
  196. watchdog_init_timeout(wdd, wdt_timeout, dev);
  197. timeout = WDT_SEC2TICKS(wdd->timeout);
  198. wdt->mr |= AT91_WDT_SET_WDD(WDT_SEC2TICKS(MAX_WDT_TIMEOUT));
  199. wdt->mr |= AT91_WDT_SET_WDV(timeout);
  200. ret = sama5d4_wdt_init(wdt);
  201. if (ret)
  202. return ret;
  203. watchdog_set_nowayout(wdd, nowayout);
  204. watchdog_stop_on_unregister(wdd);
  205. ret = devm_watchdog_register_device(dev, wdd);
  206. if (ret)
  207. return ret;
  208. platform_set_drvdata(pdev, wdt);
  209. dev_info(dev, "initialized (timeout = %d sec, nowayout = %d)\n",
  210. wdd->timeout, nowayout);
  211. return 0;
  212. }
  213. static const struct of_device_id sama5d4_wdt_of_match[] = {
  214. { .compatible = "atmel,sama5d4-wdt", },
  215. { }
  216. };
  217. MODULE_DEVICE_TABLE(of, sama5d4_wdt_of_match);
  218. #ifdef CONFIG_PM_SLEEP
  219. static int sama5d4_wdt_suspend_late(struct device *dev)
  220. {
  221. struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
  222. if (watchdog_active(&wdt->wdd))
  223. sama5d4_wdt_stop(&wdt->wdd);
  224. return 0;
  225. }
  226. static int sama5d4_wdt_resume_early(struct device *dev)
  227. {
  228. struct sama5d4_wdt *wdt = dev_get_drvdata(dev);
  229. /*
  230. * FIXME: writing MR also pings the watchdog which may not be desired.
  231. * This should only be done when the registers are lost on suspend but
  232. * there is no way to get this information right now.
  233. */
  234. sama5d4_wdt_init(wdt);
  235. if (watchdog_active(&wdt->wdd))
  236. sama5d4_wdt_start(&wdt->wdd);
  237. return 0;
  238. }
  239. #endif
  240. static const struct dev_pm_ops sama5d4_wdt_pm_ops = {
  241. SET_LATE_SYSTEM_SLEEP_PM_OPS(sama5d4_wdt_suspend_late,
  242. sama5d4_wdt_resume_early)
  243. };
  244. static struct platform_driver sama5d4_wdt_driver = {
  245. .probe = sama5d4_wdt_probe,
  246. .driver = {
  247. .name = "sama5d4_wdt",
  248. .pm = &sama5d4_wdt_pm_ops,
  249. .of_match_table = sama5d4_wdt_of_match,
  250. }
  251. };
  252. module_platform_driver(sama5d4_wdt_driver);
  253. MODULE_AUTHOR("Atmel Corporation");
  254. MODULE_DESCRIPTION("Atmel SAMA5D4 Watchdog Timer driver");
  255. MODULE_LICENSE("GPL v2");