tusb6010.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * TUSB6010 USB 2.0 OTG Dual Role controller
  4. *
  5. * Copyright (C) 2006 Nokia Corporation
  6. * Tony Lindgren <tony@atomide.com>
  7. *
  8. * Notes:
  9. * - Driver assumes that interface to external host (main CPU) is
  10. * configured for NOR FLASH interface instead of VLYNQ serial
  11. * interface.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/err.h>
  17. #include <linux/prefetch.h>
  18. #include <linux/usb.h>
  19. #include <linux/irq.h>
  20. #include <linux/io.h>
  21. #include <linux/device.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/usb/usb_phy_generic.h>
  25. #include "musb_core.h"
  26. struct tusb6010_glue {
  27. struct device *dev;
  28. struct platform_device *musb;
  29. struct platform_device *phy;
  30. };
  31. static void tusb_musb_set_vbus(struct musb *musb, int is_on);
  32. #define TUSB_REV_MAJOR(reg_val) ((reg_val >> 4) & 0xf)
  33. #define TUSB_REV_MINOR(reg_val) (reg_val & 0xf)
  34. /*
  35. * Checks the revision. We need to use the DMA register as 3.0 does not
  36. * have correct versions for TUSB_PRCM_REV or TUSB_INT_CTRL_REV.
  37. */
  38. static u8 tusb_get_revision(struct musb *musb)
  39. {
  40. void __iomem *tbase = musb->ctrl_base;
  41. u32 die_id;
  42. u8 rev;
  43. rev = musb_readl(tbase, TUSB_DMA_CTRL_REV) & 0xff;
  44. if (TUSB_REV_MAJOR(rev) == 3) {
  45. die_id = TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase,
  46. TUSB_DIDR1_HI));
  47. if (die_id >= TUSB_DIDR1_HI_REV_31)
  48. rev |= 1;
  49. }
  50. return rev;
  51. }
  52. static void tusb_print_revision(struct musb *musb)
  53. {
  54. void __iomem *tbase = musb->ctrl_base;
  55. u8 rev;
  56. rev = musb->tusb_revision;
  57. pr_info("tusb: %s%i.%i %s%i.%i %s%i.%i %s%i.%i %s%i %s%i.%i\n",
  58. "prcm",
  59. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_PRCM_REV)),
  60. TUSB_REV_MINOR(musb_readl(tbase, TUSB_PRCM_REV)),
  61. "int",
  62. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  63. TUSB_REV_MINOR(musb_readl(tbase, TUSB_INT_CTRL_REV)),
  64. "gpio",
  65. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_GPIO_REV)),
  66. TUSB_REV_MINOR(musb_readl(tbase, TUSB_GPIO_REV)),
  67. "dma",
  68. TUSB_REV_MAJOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  69. TUSB_REV_MINOR(musb_readl(tbase, TUSB_DMA_CTRL_REV)),
  70. "dieid",
  71. TUSB_DIDR1_HI_CHIP_REV(musb_readl(tbase, TUSB_DIDR1_HI)),
  72. "rev",
  73. TUSB_REV_MAJOR(rev), TUSB_REV_MINOR(rev));
  74. }
  75. #define WBUS_QUIRK_MASK (TUSB_PHY_OTG_CTRL_TESTM2 | TUSB_PHY_OTG_CTRL_TESTM1 \
  76. | TUSB_PHY_OTG_CTRL_TESTM0)
  77. /*
  78. * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
  79. * Disables power detection in PHY for the duration of idle.
  80. */
  81. static void tusb_wbus_quirk(struct musb *musb, int enabled)
  82. {
  83. void __iomem *tbase = musb->ctrl_base;
  84. static u32 phy_otg_ctrl, phy_otg_ena;
  85. u32 tmp;
  86. if (enabled) {
  87. phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  88. phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  89. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT
  90. | phy_otg_ena | WBUS_QUIRK_MASK;
  91. musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
  92. tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
  93. tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
  94. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
  95. dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
  96. musb_readl(tbase, TUSB_PHY_OTG_CTRL),
  97. musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
  98. } else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
  99. & TUSB_PHY_OTG_CTRL_TESTM2) {
  100. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl;
  101. musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
  102. tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
  103. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
  104. dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
  105. musb_readl(tbase, TUSB_PHY_OTG_CTRL),
  106. musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
  107. phy_otg_ctrl = 0;
  108. phy_otg_ena = 0;
  109. }
  110. }
  111. static u32 tusb_fifo_offset(u8 epnum)
  112. {
  113. return 0x200 + (epnum * 0x20);
  114. }
  115. static u32 tusb_ep_offset(u8 epnum, u16 offset)
  116. {
  117. return 0x10 + offset;
  118. }
  119. /* TUSB mapping: "flat" plus ep0 special cases */
  120. static void tusb_ep_select(void __iomem *mbase, u8 epnum)
  121. {
  122. musb_writeb(mbase, MUSB_INDEX, epnum);
  123. }
  124. /*
  125. * TUSB6010 doesn't allow 8-bit access; 16-bit access is the minimum.
  126. */
  127. static u8 tusb_readb(const void __iomem *addr, unsigned offset)
  128. {
  129. u16 tmp;
  130. u8 val;
  131. tmp = __raw_readw(addr + (offset & ~1));
  132. if (offset & 1)
  133. val = (tmp >> 8);
  134. else
  135. val = tmp & 0xff;
  136. return val;
  137. }
  138. static void tusb_writeb(void __iomem *addr, unsigned offset, u8 data)
  139. {
  140. u16 tmp;
  141. tmp = __raw_readw(addr + (offset & ~1));
  142. if (offset & 1)
  143. tmp = (data << 8) | (tmp & 0xff);
  144. else
  145. tmp = (tmp & 0xff00) | data;
  146. __raw_writew(tmp, addr + (offset & ~1));
  147. }
  148. /*
  149. * TUSB 6010 may use a parallel bus that doesn't support byte ops;
  150. * so both loading and unloading FIFOs need explicit byte counts.
  151. */
  152. static inline void
  153. tusb_fifo_write_unaligned(void __iomem *fifo, const u8 *buf, u16 len)
  154. {
  155. u32 val;
  156. int i;
  157. if (len > 4) {
  158. for (i = 0; i < (len >> 2); i++) {
  159. memcpy(&val, buf, 4);
  160. musb_writel(fifo, 0, val);
  161. buf += 4;
  162. }
  163. len %= 4;
  164. }
  165. if (len > 0) {
  166. /* Write the rest 1 - 3 bytes to FIFO */
  167. val = 0;
  168. memcpy(&val, buf, len);
  169. musb_writel(fifo, 0, val);
  170. }
  171. }
  172. static inline void tusb_fifo_read_unaligned(void __iomem *fifo,
  173. void *buf, u16 len)
  174. {
  175. u32 val;
  176. int i;
  177. if (len > 4) {
  178. for (i = 0; i < (len >> 2); i++) {
  179. val = musb_readl(fifo, 0);
  180. memcpy(buf, &val, 4);
  181. buf += 4;
  182. }
  183. len %= 4;
  184. }
  185. if (len > 0) {
  186. /* Read the rest 1 - 3 bytes from FIFO */
  187. val = musb_readl(fifo, 0);
  188. memcpy(buf, &val, len);
  189. }
  190. }
  191. static void tusb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
  192. {
  193. struct musb *musb = hw_ep->musb;
  194. void __iomem *ep_conf = hw_ep->conf;
  195. void __iomem *fifo = hw_ep->fifo;
  196. u8 epnum = hw_ep->epnum;
  197. prefetch(buf);
  198. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  199. 'T', epnum, fifo, len, buf);
  200. if (epnum)
  201. musb_writel(ep_conf, TUSB_EP_TX_OFFSET,
  202. TUSB_EP_CONFIG_XFR_SIZE(len));
  203. else
  204. musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_DIR_TX |
  205. TUSB_EP0_CONFIG_XFR_SIZE(len));
  206. if (likely((0x01 & (unsigned long) buf) == 0)) {
  207. /* Best case is 32bit-aligned destination address */
  208. if ((0x02 & (unsigned long) buf) == 0) {
  209. if (len >= 4) {
  210. iowrite32_rep(fifo, buf, len >> 2);
  211. buf += (len & ~0x03);
  212. len &= 0x03;
  213. }
  214. } else {
  215. if (len >= 2) {
  216. u32 val;
  217. int i;
  218. /* Cannot use writesw, fifo is 32-bit */
  219. for (i = 0; i < (len >> 2); i++) {
  220. val = (u32)(*(u16 *)buf);
  221. buf += 2;
  222. val |= (*(u16 *)buf) << 16;
  223. buf += 2;
  224. musb_writel(fifo, 0, val);
  225. }
  226. len &= 0x03;
  227. }
  228. }
  229. }
  230. if (len > 0)
  231. tusb_fifo_write_unaligned(fifo, buf, len);
  232. }
  233. static void tusb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
  234. {
  235. struct musb *musb = hw_ep->musb;
  236. void __iomem *ep_conf = hw_ep->conf;
  237. void __iomem *fifo = hw_ep->fifo;
  238. u8 epnum = hw_ep->epnum;
  239. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  240. 'R', epnum, fifo, len, buf);
  241. if (epnum)
  242. musb_writel(ep_conf, TUSB_EP_RX_OFFSET,
  243. TUSB_EP_CONFIG_XFR_SIZE(len));
  244. else
  245. musb_writel(ep_conf, 0, TUSB_EP0_CONFIG_XFR_SIZE(len));
  246. if (likely((0x01 & (unsigned long) buf) == 0)) {
  247. /* Best case is 32bit-aligned destination address */
  248. if ((0x02 & (unsigned long) buf) == 0) {
  249. if (len >= 4) {
  250. ioread32_rep(fifo, buf, len >> 2);
  251. buf += (len & ~0x03);
  252. len &= 0x03;
  253. }
  254. } else {
  255. if (len >= 2) {
  256. u32 val;
  257. int i;
  258. /* Cannot use readsw, fifo is 32-bit */
  259. for (i = 0; i < (len >> 2); i++) {
  260. val = musb_readl(fifo, 0);
  261. *(u16 *)buf = (u16)(val & 0xffff);
  262. buf += 2;
  263. *(u16 *)buf = (u16)(val >> 16);
  264. buf += 2;
  265. }
  266. len &= 0x03;
  267. }
  268. }
  269. }
  270. if (len > 0)
  271. tusb_fifo_read_unaligned(fifo, buf, len);
  272. }
  273. static struct musb *the_musb;
  274. /* This is used by gadget drivers, and OTG transceiver logic, allowing
  275. * at most mA current to be drawn from VBUS during a Default-B session
  276. * (that is, while VBUS exceeds 4.4V). In Default-A (including pure host
  277. * mode), or low power Default-B sessions, something else supplies power.
  278. * Caller must take care of locking.
  279. */
  280. static int tusb_draw_power(struct usb_phy *x, unsigned mA)
  281. {
  282. struct musb *musb = the_musb;
  283. void __iomem *tbase = musb->ctrl_base;
  284. u32 reg;
  285. /* tps65030 seems to consume max 100mA, with maybe 60mA available
  286. * (measured on one board) for things other than tps and tusb.
  287. *
  288. * Boards sharing the CPU clock with CLKIN will need to prevent
  289. * certain idle sleep states while the USB link is active.
  290. *
  291. * REVISIT we could use VBUS to supply only _one_ of { 1.5V, 3.3V }.
  292. * The actual current usage would be very board-specific. For now,
  293. * it's simpler to just use an aggregate (also board-specific).
  294. */
  295. if (x->otg->default_a || mA < (musb->min_power << 1))
  296. mA = 0;
  297. reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
  298. if (mA) {
  299. musb->is_bus_powered = 1;
  300. reg |= TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN;
  301. } else {
  302. musb->is_bus_powered = 0;
  303. reg &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
  304. }
  305. musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
  306. dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
  307. return 0;
  308. }
  309. /* workaround for issue 13: change clock during chip idle
  310. * (to be fixed in rev3 silicon) ... symptoms include disconnect
  311. * or looping suspend/resume cycles
  312. */
  313. static void tusb_set_clock_source(struct musb *musb, unsigned mode)
  314. {
  315. void __iomem *tbase = musb->ctrl_base;
  316. u32 reg;
  317. reg = musb_readl(tbase, TUSB_PRCM_CONF);
  318. reg &= ~TUSB_PRCM_CONF_SYS_CLKSEL(0x3);
  319. /* 0 = refclk (clkin, XI)
  320. * 1 = PHY 60 MHz (internal PLL)
  321. * 2 = not supported
  322. * 3 = what?
  323. */
  324. if (mode > 0)
  325. reg |= TUSB_PRCM_CONF_SYS_CLKSEL(mode & 0x3);
  326. musb_writel(tbase, TUSB_PRCM_CONF, reg);
  327. /* FIXME tusb6010_platform_retime(mode == 0); */
  328. }
  329. /*
  330. * Idle TUSB6010 until next wake-up event; NOR access always wakes.
  331. * Other code ensures that we idle unless we're connected _and_ the
  332. * USB link is not suspended ... and tells us the relevant wakeup
  333. * events. SW_EN for voltage is handled separately.
  334. */
  335. static void tusb_allow_idle(struct musb *musb, u32 wakeup_enables)
  336. {
  337. void __iomem *tbase = musb->ctrl_base;
  338. u32 reg;
  339. if ((wakeup_enables & TUSB_PRCM_WBUS)
  340. && (musb->tusb_revision == TUSB_REV_30))
  341. tusb_wbus_quirk(musb, 1);
  342. tusb_set_clock_source(musb, 0);
  343. wakeup_enables |= TUSB_PRCM_WNORCS;
  344. musb_writel(tbase, TUSB_PRCM_WAKEUP_MASK, ~wakeup_enables);
  345. /* REVISIT writeup of WID implies that if WID set and ID is grounded,
  346. * TUSB_PHY_OTG_CTRL.TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP must be cleared.
  347. * Presumably that's mostly to save power, hence WID is immaterial ...
  348. */
  349. reg = musb_readl(tbase, TUSB_PRCM_MNGMT);
  350. /* issue 4: when driving vbus, use hipower (vbus_det) comparator */
  351. if (is_host_active(musb)) {
  352. reg |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  353. reg &= ~TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
  354. } else {
  355. reg |= TUSB_PRCM_MNGMT_OTG_SESS_END_EN;
  356. reg &= ~TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  357. }
  358. reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
  359. musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
  360. dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
  361. }
  362. /*
  363. * Updates cable VBUS status. Caller must take care of locking.
  364. */
  365. static int tusb_musb_vbus_status(struct musb *musb)
  366. {
  367. void __iomem *tbase = musb->ctrl_base;
  368. u32 otg_stat, prcm_mngmt;
  369. int ret = 0;
  370. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  371. prcm_mngmt = musb_readl(tbase, TUSB_PRCM_MNGMT);
  372. /* Temporarily enable VBUS detection if it was disabled for
  373. * suspend mode. Unless it's enabled otg_stat and devctl will
  374. * not show correct VBUS state.
  375. */
  376. if (!(prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) {
  377. u32 tmp = prcm_mngmt;
  378. tmp |= TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN;
  379. musb_writel(tbase, TUSB_PRCM_MNGMT, tmp);
  380. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  381. musb_writel(tbase, TUSB_PRCM_MNGMT, prcm_mngmt);
  382. }
  383. if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID)
  384. ret = 1;
  385. return ret;
  386. }
  387. static void musb_do_idle(struct timer_list *t)
  388. {
  389. struct musb *musb = from_timer(musb, t, dev_timer);
  390. unsigned long flags;
  391. spin_lock_irqsave(&musb->lock, flags);
  392. switch (musb->xceiv->otg->state) {
  393. case OTG_STATE_A_WAIT_BCON:
  394. if ((musb->a_wait_bcon != 0)
  395. && (musb->idle_timeout == 0
  396. || time_after(jiffies, musb->idle_timeout))) {
  397. dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
  398. usb_otg_state_string(musb->xceiv->otg->state));
  399. }
  400. /* FALLTHROUGH */
  401. case OTG_STATE_A_IDLE:
  402. tusb_musb_set_vbus(musb, 0);
  403. default:
  404. break;
  405. }
  406. if (!musb->is_active) {
  407. u32 wakeups;
  408. /* wait until hub_wq handles port change status */
  409. if (is_host_active(musb) && (musb->port1_status >> 16))
  410. goto done;
  411. if (!musb->gadget_driver) {
  412. wakeups = 0;
  413. } else {
  414. wakeups = TUSB_PRCM_WHOSTDISCON
  415. | TUSB_PRCM_WBUS
  416. | TUSB_PRCM_WVBUS;
  417. wakeups |= TUSB_PRCM_WID;
  418. }
  419. tusb_allow_idle(musb, wakeups);
  420. }
  421. done:
  422. spin_unlock_irqrestore(&musb->lock, flags);
  423. }
  424. /*
  425. * Maybe put TUSB6010 into idle mode mode depending on USB link status,
  426. * like "disconnected" or "suspended". We'll be woken out of it by
  427. * connect, resume, or disconnect.
  428. *
  429. * Needs to be called as the last function everywhere where there is
  430. * register access to TUSB6010 because of NOR flash wake-up.
  431. * Caller should own controller spinlock.
  432. *
  433. * Delay because peripheral enables D+ pullup 3msec after SE0, and
  434. * we don't want to treat that full speed J as a wakeup event.
  435. * ... peripherals must draw only suspend current after 10 msec.
  436. */
  437. static void tusb_musb_try_idle(struct musb *musb, unsigned long timeout)
  438. {
  439. unsigned long default_timeout = jiffies + msecs_to_jiffies(3);
  440. static unsigned long last_timer;
  441. if (timeout == 0)
  442. timeout = default_timeout;
  443. /* Never idle if active, or when VBUS timeout is not set as host */
  444. if (musb->is_active || ((musb->a_wait_bcon == 0)
  445. && (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON))) {
  446. dev_dbg(musb->controller, "%s active, deleting timer\n",
  447. usb_otg_state_string(musb->xceiv->otg->state));
  448. del_timer(&musb->dev_timer);
  449. last_timer = jiffies;
  450. return;
  451. }
  452. if (time_after(last_timer, timeout)) {
  453. if (!timer_pending(&musb->dev_timer))
  454. last_timer = timeout;
  455. else {
  456. dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
  457. return;
  458. }
  459. }
  460. last_timer = timeout;
  461. dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
  462. usb_otg_state_string(musb->xceiv->otg->state),
  463. (unsigned long)jiffies_to_msecs(timeout - jiffies));
  464. mod_timer(&musb->dev_timer, timeout);
  465. }
  466. /* ticks of 60 MHz clock */
  467. #define DEVCLOCK 60000000
  468. #define OTG_TIMER_MS(msecs) ((msecs) \
  469. ? (TUSB_DEV_OTG_TIMER_VAL((DEVCLOCK/1000)*(msecs)) \
  470. | TUSB_DEV_OTG_TIMER_ENABLE) \
  471. : 0)
  472. static void tusb_musb_set_vbus(struct musb *musb, int is_on)
  473. {
  474. void __iomem *tbase = musb->ctrl_base;
  475. u32 conf, prcm, timer;
  476. u8 devctl;
  477. struct usb_otg *otg = musb->xceiv->otg;
  478. /* HDRC controls CPEN, but beware current surges during device
  479. * connect. They can trigger transient overcurrent conditions
  480. * that must be ignored.
  481. */
  482. prcm = musb_readl(tbase, TUSB_PRCM_MNGMT);
  483. conf = musb_readl(tbase, TUSB_DEV_CONF);
  484. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  485. if (is_on) {
  486. timer = OTG_TIMER_MS(OTG_TIME_A_WAIT_VRISE);
  487. otg->default_a = 1;
  488. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
  489. devctl |= MUSB_DEVCTL_SESSION;
  490. conf |= TUSB_DEV_CONF_USB_HOST_MODE;
  491. MUSB_HST_MODE(musb);
  492. } else {
  493. u32 otg_stat;
  494. timer = 0;
  495. /* If ID pin is grounded, we want to be a_idle */
  496. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  497. if (!(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS)) {
  498. switch (musb->xceiv->otg->state) {
  499. case OTG_STATE_A_WAIT_VRISE:
  500. case OTG_STATE_A_WAIT_BCON:
  501. musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
  502. break;
  503. case OTG_STATE_A_WAIT_VFALL:
  504. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  505. break;
  506. default:
  507. musb->xceiv->otg->state = OTG_STATE_A_IDLE;
  508. }
  509. musb->is_active = 0;
  510. otg->default_a = 1;
  511. MUSB_HST_MODE(musb);
  512. } else {
  513. musb->is_active = 0;
  514. otg->default_a = 0;
  515. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  516. MUSB_DEV_MODE(musb);
  517. }
  518. devctl &= ~MUSB_DEVCTL_SESSION;
  519. conf &= ~TUSB_DEV_CONF_USB_HOST_MODE;
  520. }
  521. prcm &= ~(TUSB_PRCM_MNGMT_15_SW_EN | TUSB_PRCM_MNGMT_33_SW_EN);
  522. musb_writel(tbase, TUSB_PRCM_MNGMT, prcm);
  523. musb_writel(tbase, TUSB_DEV_OTG_TIMER, timer);
  524. musb_writel(tbase, TUSB_DEV_CONF, conf);
  525. musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  526. dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
  527. usb_otg_state_string(musb->xceiv->otg->state),
  528. musb_readb(musb->mregs, MUSB_DEVCTL),
  529. musb_readl(tbase, TUSB_DEV_OTG_STAT),
  530. conf, prcm);
  531. }
  532. /*
  533. * Sets the mode to OTG, peripheral or host by changing the ID detection.
  534. * Caller must take care of locking.
  535. *
  536. * Note that if a mini-A cable is plugged in the ID line will stay down as
  537. * the weak ID pull-up is not able to pull the ID up.
  538. */
  539. static int tusb_musb_set_mode(struct musb *musb, u8 musb_mode)
  540. {
  541. void __iomem *tbase = musb->ctrl_base;
  542. u32 otg_stat, phy_otg_ctrl, phy_otg_ena, dev_conf;
  543. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  544. phy_otg_ctrl = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  545. phy_otg_ena = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  546. dev_conf = musb_readl(tbase, TUSB_DEV_CONF);
  547. switch (musb_mode) {
  548. case MUSB_HOST: /* Disable PHY ID detect, ground ID */
  549. phy_otg_ctrl &= ~TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  550. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  551. dev_conf |= TUSB_DEV_CONF_ID_SEL;
  552. dev_conf &= ~TUSB_DEV_CONF_SOFT_ID;
  553. break;
  554. case MUSB_PERIPHERAL: /* Disable PHY ID detect, keep ID pull-up on */
  555. phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  556. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  557. dev_conf |= (TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
  558. break;
  559. case MUSB_OTG: /* Use PHY ID detection */
  560. phy_otg_ctrl |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  561. phy_otg_ena |= TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  562. dev_conf &= ~(TUSB_DEV_CONF_ID_SEL | TUSB_DEV_CONF_SOFT_ID);
  563. break;
  564. default:
  565. dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
  566. return -EINVAL;
  567. }
  568. musb_writel(tbase, TUSB_PHY_OTG_CTRL,
  569. TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ctrl);
  570. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE,
  571. TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena);
  572. musb_writel(tbase, TUSB_DEV_CONF, dev_conf);
  573. otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  574. if ((musb_mode == MUSB_PERIPHERAL) &&
  575. !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS))
  576. INFO("Cannot be peripheral with mini-A cable "
  577. "otg_stat: %08x\n", otg_stat);
  578. return 0;
  579. }
  580. static inline unsigned long
  581. tusb_otg_ints(struct musb *musb, u32 int_src, void __iomem *tbase)
  582. {
  583. u32 otg_stat = musb_readl(tbase, TUSB_DEV_OTG_STAT);
  584. unsigned long idle_timeout = 0;
  585. struct usb_otg *otg = musb->xceiv->otg;
  586. /* ID pin */
  587. if ((int_src & TUSB_INT_SRC_ID_STATUS_CHNG)) {
  588. int default_a;
  589. default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
  590. dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
  591. otg->default_a = default_a;
  592. tusb_musb_set_vbus(musb, default_a);
  593. /* Don't allow idling immediately */
  594. if (default_a)
  595. idle_timeout = jiffies + (HZ * 3);
  596. }
  597. /* VBUS state change */
  598. if (int_src & TUSB_INT_SRC_VBUS_SENSE_CHNG) {
  599. /* B-dev state machine: no vbus ~= disconnect */
  600. if (!otg->default_a) {
  601. /* ? musb_root_disconnect(musb); */
  602. musb->port1_status &=
  603. ~(USB_PORT_STAT_CONNECTION
  604. | USB_PORT_STAT_ENABLE
  605. | USB_PORT_STAT_LOW_SPEED
  606. | USB_PORT_STAT_HIGH_SPEED
  607. | USB_PORT_STAT_TEST
  608. );
  609. if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
  610. dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
  611. if (musb->xceiv->otg->state != OTG_STATE_B_IDLE) {
  612. /* INTR_DISCONNECT can hide... */
  613. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  614. musb->int_usb |= MUSB_INTR_DISCONNECT;
  615. }
  616. musb->is_active = 0;
  617. }
  618. dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
  619. usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
  620. idle_timeout = jiffies + (1 * HZ);
  621. schedule_delayed_work(&musb->irq_work, 0);
  622. } else /* A-dev state machine */ {
  623. dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
  624. usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
  625. switch (musb->xceiv->otg->state) {
  626. case OTG_STATE_A_IDLE:
  627. dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
  628. musb_platform_set_vbus(musb, 1);
  629. /* CONNECT can wake if a_wait_bcon is set */
  630. if (musb->a_wait_bcon != 0)
  631. musb->is_active = 0;
  632. else
  633. musb->is_active = 1;
  634. /*
  635. * OPT FS A TD.4.6 needs few seconds for
  636. * A_WAIT_VRISE
  637. */
  638. idle_timeout = jiffies + (2 * HZ);
  639. break;
  640. case OTG_STATE_A_WAIT_VRISE:
  641. /* ignore; A-session-valid < VBUS_VALID/2,
  642. * we monitor this with the timer
  643. */
  644. break;
  645. case OTG_STATE_A_WAIT_VFALL:
  646. /* REVISIT this irq triggers during short
  647. * spikes caused by enumeration ...
  648. */
  649. if (musb->vbuserr_retry) {
  650. musb->vbuserr_retry--;
  651. tusb_musb_set_vbus(musb, 1);
  652. } else {
  653. musb->vbuserr_retry
  654. = VBUSERR_RETRY_COUNT;
  655. tusb_musb_set_vbus(musb, 0);
  656. }
  657. break;
  658. default:
  659. break;
  660. }
  661. }
  662. }
  663. /* OTG timer expiration */
  664. if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
  665. u8 devctl;
  666. dev_dbg(musb->controller, "%s timer, %03x\n",
  667. usb_otg_state_string(musb->xceiv->otg->state), otg_stat);
  668. switch (musb->xceiv->otg->state) {
  669. case OTG_STATE_A_WAIT_VRISE:
  670. /* VBUS has probably been valid for a while now,
  671. * but may well have bounced out of range a bit
  672. */
  673. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  674. if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
  675. if ((devctl & MUSB_DEVCTL_VBUS)
  676. != MUSB_DEVCTL_VBUS) {
  677. dev_dbg(musb->controller, "devctl %02x\n", devctl);
  678. break;
  679. }
  680. musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
  681. musb->is_active = 0;
  682. idle_timeout = jiffies
  683. + msecs_to_jiffies(musb->a_wait_bcon);
  684. } else {
  685. /* REVISIT report overcurrent to hub? */
  686. ERR("vbus too slow, devctl %02x\n", devctl);
  687. tusb_musb_set_vbus(musb, 0);
  688. }
  689. break;
  690. case OTG_STATE_A_WAIT_BCON:
  691. if (musb->a_wait_bcon != 0)
  692. idle_timeout = jiffies
  693. + msecs_to_jiffies(musb->a_wait_bcon);
  694. break;
  695. case OTG_STATE_A_SUSPEND:
  696. break;
  697. case OTG_STATE_B_WAIT_ACON:
  698. break;
  699. default:
  700. break;
  701. }
  702. }
  703. schedule_delayed_work(&musb->irq_work, 0);
  704. return idle_timeout;
  705. }
  706. static irqreturn_t tusb_musb_interrupt(int irq, void *__hci)
  707. {
  708. struct musb *musb = __hci;
  709. void __iomem *tbase = musb->ctrl_base;
  710. unsigned long flags, idle_timeout = 0;
  711. u32 int_mask, int_src;
  712. spin_lock_irqsave(&musb->lock, flags);
  713. /* Mask all interrupts to allow using both edge and level GPIO irq */
  714. int_mask = musb_readl(tbase, TUSB_INT_MASK);
  715. musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
  716. int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
  717. dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
  718. musb->int_usb = (u8) int_src;
  719. /* Acknowledge wake-up source interrupts */
  720. if (int_src & TUSB_INT_SRC_DEV_WAKEUP) {
  721. u32 reg;
  722. u32 i;
  723. if (musb->tusb_revision == TUSB_REV_30)
  724. tusb_wbus_quirk(musb, 0);
  725. /* there are issues re-locking the PLL on wakeup ... */
  726. /* work around issue 8 */
  727. for (i = 0xf7f7f7; i > 0xf7f7f7 - 1000; i--) {
  728. musb_writel(tbase, TUSB_SCRATCH_PAD, 0);
  729. musb_writel(tbase, TUSB_SCRATCH_PAD, i);
  730. reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
  731. if (reg == i)
  732. break;
  733. dev_dbg(musb->controller, "TUSB NOR not ready\n");
  734. }
  735. /* work around issue 13 (2nd half) */
  736. tusb_set_clock_source(musb, 1);
  737. reg = musb_readl(tbase, TUSB_PRCM_WAKEUP_SOURCE);
  738. musb_writel(tbase, TUSB_PRCM_WAKEUP_CLEAR, reg);
  739. if (reg & ~TUSB_PRCM_WNORCS) {
  740. musb->is_active = 1;
  741. schedule_delayed_work(&musb->irq_work, 0);
  742. }
  743. dev_dbg(musb->controller, "wake %sactive %02x\n",
  744. musb->is_active ? "" : "in", reg);
  745. /* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
  746. }
  747. if (int_src & TUSB_INT_SRC_USB_IP_CONN)
  748. del_timer(&musb->dev_timer);
  749. /* OTG state change reports (annoyingly) not issued by Mentor core */
  750. if (int_src & (TUSB_INT_SRC_VBUS_SENSE_CHNG
  751. | TUSB_INT_SRC_OTG_TIMEOUT
  752. | TUSB_INT_SRC_ID_STATUS_CHNG))
  753. idle_timeout = tusb_otg_ints(musb, int_src, tbase);
  754. /*
  755. * Just clear the DMA interrupt if it comes as the completion for both
  756. * TX and RX is handled by the DMA callback in tusb6010_omap
  757. */
  758. if ((int_src & TUSB_INT_SRC_TXRX_DMA_DONE)) {
  759. u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
  760. dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
  761. musb_writel(tbase, TUSB_DMA_INT_CLEAR, dma_src);
  762. }
  763. /* EP interrupts. In OCP mode tusb6010 mirrors the MUSB interrupts */
  764. if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX)) {
  765. u32 musb_src = musb_readl(tbase, TUSB_USBIP_INT_SRC);
  766. musb_writel(tbase, TUSB_USBIP_INT_CLEAR, musb_src);
  767. musb->int_rx = (((musb_src >> 16) & 0xffff) << 1);
  768. musb->int_tx = (musb_src & 0xffff);
  769. } else {
  770. musb->int_rx = 0;
  771. musb->int_tx = 0;
  772. }
  773. if (int_src & (TUSB_INT_SRC_USB_IP_TX | TUSB_INT_SRC_USB_IP_RX | 0xff))
  774. musb_interrupt(musb);
  775. /* Acknowledge TUSB interrupts. Clear only non-reserved bits */
  776. musb_writel(tbase, TUSB_INT_SRC_CLEAR,
  777. int_src & ~TUSB_INT_MASK_RESERVED_BITS);
  778. tusb_musb_try_idle(musb, idle_timeout);
  779. musb_writel(tbase, TUSB_INT_MASK, int_mask);
  780. spin_unlock_irqrestore(&musb->lock, flags);
  781. return IRQ_HANDLED;
  782. }
  783. static int dma_off;
  784. /*
  785. * Enables TUSB6010. Caller must take care of locking.
  786. * REVISIT:
  787. * - Check what is unnecessary in MGC_HdrcStart()
  788. */
  789. static void tusb_musb_enable(struct musb *musb)
  790. {
  791. void __iomem *tbase = musb->ctrl_base;
  792. /* Setup TUSB6010 main interrupt mask. Enable all interrupts except SOF.
  793. * REVISIT: Enable and deal with TUSB_INT_SRC_USB_IP_SOF */
  794. musb_writel(tbase, TUSB_INT_MASK, TUSB_INT_SRC_USB_IP_SOF);
  795. /* Setup TUSB interrupt, disable DMA and GPIO interrupts */
  796. musb_writel(tbase, TUSB_USBIP_INT_MASK, 0);
  797. musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
  798. musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
  799. /* Clear all subsystem interrups */
  800. musb_writel(tbase, TUSB_USBIP_INT_CLEAR, 0x7fffffff);
  801. musb_writel(tbase, TUSB_DMA_INT_CLEAR, 0x7fffffff);
  802. musb_writel(tbase, TUSB_GPIO_INT_CLEAR, 0x1ff);
  803. /* Acknowledge pending interrupt(s) */
  804. musb_writel(tbase, TUSB_INT_SRC_CLEAR, ~TUSB_INT_MASK_RESERVED_BITS);
  805. /* Only 0 clock cycles for minimum interrupt de-assertion time and
  806. * interrupt polarity active low seems to work reliably here */
  807. musb_writel(tbase, TUSB_INT_CTRL_CONF,
  808. TUSB_INT_CTRL_CONF_INT_RELCYC(0));
  809. irq_set_irq_type(musb->nIrq, IRQ_TYPE_LEVEL_LOW);
  810. /* maybe force into the Default-A OTG state machine */
  811. if (!(musb_readl(tbase, TUSB_DEV_OTG_STAT)
  812. & TUSB_DEV_OTG_STAT_ID_STATUS))
  813. musb_writel(tbase, TUSB_INT_SRC_SET,
  814. TUSB_INT_SRC_ID_STATUS_CHNG);
  815. if (is_dma_capable() && dma_off)
  816. printk(KERN_WARNING "%s %s: dma not reactivated\n",
  817. __FILE__, __func__);
  818. else
  819. dma_off = 1;
  820. }
  821. /*
  822. * Disables TUSB6010. Caller must take care of locking.
  823. */
  824. static void tusb_musb_disable(struct musb *musb)
  825. {
  826. void __iomem *tbase = musb->ctrl_base;
  827. /* FIXME stop DMA, IRQs, timers, ... */
  828. /* disable all IRQs */
  829. musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
  830. musb_writel(tbase, TUSB_USBIP_INT_MASK, 0x7fffffff);
  831. musb_writel(tbase, TUSB_DMA_INT_MASK, 0x7fffffff);
  832. musb_writel(tbase, TUSB_GPIO_INT_MASK, 0x1ff);
  833. del_timer(&musb->dev_timer);
  834. if (is_dma_capable() && !dma_off) {
  835. printk(KERN_WARNING "%s %s: dma still active\n",
  836. __FILE__, __func__);
  837. dma_off = 1;
  838. }
  839. }
  840. /*
  841. * Sets up TUSB6010 CPU interface specific signals and registers
  842. * Note: Settings optimized for OMAP24xx
  843. */
  844. static void tusb_setup_cpu_interface(struct musb *musb)
  845. {
  846. void __iomem *tbase = musb->ctrl_base;
  847. /*
  848. * Disable GPIO[5:0] pullups (used as output DMA requests)
  849. * Don't disable GPIO[7:6] as they are needed for wake-up.
  850. */
  851. musb_writel(tbase, TUSB_PULLUP_1_CTRL, 0x0000003F);
  852. /* Disable all pullups on NOR IF, DMAREQ0 and DMAREQ1 */
  853. musb_writel(tbase, TUSB_PULLUP_2_CTRL, 0x01FFFFFF);
  854. /* Turn GPIO[5:0] to DMAREQ[5:0] signals */
  855. musb_writel(tbase, TUSB_GPIO_CONF, TUSB_GPIO_CONF_DMAREQ(0x3f));
  856. /* Burst size 16x16 bits, all six DMA requests enabled, DMA request
  857. * de-assertion time 2 system clocks p 62 */
  858. musb_writel(tbase, TUSB_DMA_REQ_CONF,
  859. TUSB_DMA_REQ_CONF_BURST_SIZE(2) |
  860. TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) |
  861. TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2));
  862. /* Set 0 wait count for synchronous burst access */
  863. musb_writel(tbase, TUSB_WAIT_COUNT, 1);
  864. }
  865. static int tusb_musb_start(struct musb *musb)
  866. {
  867. void __iomem *tbase = musb->ctrl_base;
  868. int ret = 0;
  869. unsigned long flags;
  870. u32 reg;
  871. if (musb->board_set_power)
  872. ret = musb->board_set_power(1);
  873. if (ret != 0) {
  874. printk(KERN_ERR "tusb: Cannot enable TUSB6010\n");
  875. return ret;
  876. }
  877. spin_lock_irqsave(&musb->lock, flags);
  878. if (musb_readl(tbase, TUSB_PROD_TEST_RESET) !=
  879. TUSB_PROD_TEST_RESET_VAL) {
  880. printk(KERN_ERR "tusb: Unable to detect TUSB6010\n");
  881. goto err;
  882. }
  883. musb->tusb_revision = tusb_get_revision(musb);
  884. tusb_print_revision(musb);
  885. if (musb->tusb_revision < 2) {
  886. printk(KERN_ERR "tusb: Unsupported TUSB6010 revision %i\n",
  887. musb->tusb_revision);
  888. goto err;
  889. }
  890. /* The uint bit for "USB non-PDR interrupt enable" has to be 1 when
  891. * NOR FLASH interface is used */
  892. musb_writel(tbase, TUSB_VLYNQ_CTRL, 8);
  893. /* Select PHY free running 60MHz as a system clock */
  894. tusb_set_clock_source(musb, 1);
  895. /* VBus valid timer 1us, disable DFT/Debug and VLYNQ clocks for
  896. * power saving, enable VBus detect and session end comparators,
  897. * enable IDpullup, enable VBus charging */
  898. musb_writel(tbase, TUSB_PRCM_MNGMT,
  899. TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(0xa) |
  900. TUSB_PRCM_MNGMT_VBUS_VALID_FLT_EN |
  901. TUSB_PRCM_MNGMT_OTG_SESS_END_EN |
  902. TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN |
  903. TUSB_PRCM_MNGMT_OTG_ID_PULLUP);
  904. tusb_setup_cpu_interface(musb);
  905. /* simplify: always sense/pullup ID pins, as if in OTG mode */
  906. reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE);
  907. reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  908. musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, reg);
  909. reg = musb_readl(tbase, TUSB_PHY_OTG_CTRL);
  910. reg |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_OTG_ID_PULLUP;
  911. musb_writel(tbase, TUSB_PHY_OTG_CTRL, reg);
  912. spin_unlock_irqrestore(&musb->lock, flags);
  913. return 0;
  914. err:
  915. spin_unlock_irqrestore(&musb->lock, flags);
  916. if (musb->board_set_power)
  917. musb->board_set_power(0);
  918. return -ENODEV;
  919. }
  920. static int tusb_musb_init(struct musb *musb)
  921. {
  922. struct platform_device *pdev;
  923. struct resource *mem;
  924. void __iomem *sync = NULL;
  925. int ret;
  926. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  927. if (IS_ERR_OR_NULL(musb->xceiv))
  928. return -EPROBE_DEFER;
  929. pdev = to_platform_device(musb->controller);
  930. /* dma address for async dma */
  931. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  932. musb->async = mem->start;
  933. /* dma address for sync dma */
  934. mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  935. if (!mem) {
  936. pr_debug("no sync dma resource?\n");
  937. ret = -ENODEV;
  938. goto done;
  939. }
  940. musb->sync = mem->start;
  941. sync = ioremap(mem->start, resource_size(mem));
  942. if (!sync) {
  943. pr_debug("ioremap for sync failed\n");
  944. ret = -ENOMEM;
  945. goto done;
  946. }
  947. musb->sync_va = sync;
  948. /* Offsets from base: VLYNQ at 0x000, MUSB regs at 0x400,
  949. * FIFOs at 0x600, TUSB at 0x800
  950. */
  951. musb->mregs += TUSB_BASE_OFFSET;
  952. ret = tusb_musb_start(musb);
  953. if (ret) {
  954. printk(KERN_ERR "Could not start tusb6010 (%d)\n",
  955. ret);
  956. goto done;
  957. }
  958. musb->isr = tusb_musb_interrupt;
  959. musb->xceiv->set_power = tusb_draw_power;
  960. the_musb = musb;
  961. timer_setup(&musb->dev_timer, musb_do_idle, 0);
  962. done:
  963. if (ret < 0) {
  964. if (sync)
  965. iounmap(sync);
  966. usb_put_phy(musb->xceiv);
  967. }
  968. return ret;
  969. }
  970. static int tusb_musb_exit(struct musb *musb)
  971. {
  972. del_timer_sync(&musb->dev_timer);
  973. the_musb = NULL;
  974. if (musb->board_set_power)
  975. musb->board_set_power(0);
  976. iounmap(musb->sync_va);
  977. usb_put_phy(musb->xceiv);
  978. return 0;
  979. }
  980. static const struct musb_platform_ops tusb_ops = {
  981. .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB |
  982. MUSB_G_NO_SKB_RESERVE,
  983. .init = tusb_musb_init,
  984. .exit = tusb_musb_exit,
  985. .ep_offset = tusb_ep_offset,
  986. .ep_select = tusb_ep_select,
  987. .fifo_offset = tusb_fifo_offset,
  988. .readb = tusb_readb,
  989. .writeb = tusb_writeb,
  990. .read_fifo = tusb_read_fifo,
  991. .write_fifo = tusb_write_fifo,
  992. #ifdef CONFIG_USB_TUSB_OMAP_DMA
  993. .dma_init = tusb_dma_controller_create,
  994. .dma_exit = tusb_dma_controller_destroy,
  995. #endif
  996. .enable = tusb_musb_enable,
  997. .disable = tusb_musb_disable,
  998. .set_mode = tusb_musb_set_mode,
  999. .try_idle = tusb_musb_try_idle,
  1000. .vbus_status = tusb_musb_vbus_status,
  1001. .set_vbus = tusb_musb_set_vbus,
  1002. };
  1003. static const struct platform_device_info tusb_dev_info = {
  1004. .name = "musb-hdrc",
  1005. .id = PLATFORM_DEVID_AUTO,
  1006. .dma_mask = DMA_BIT_MASK(32),
  1007. };
  1008. static int tusb_probe(struct platform_device *pdev)
  1009. {
  1010. struct resource musb_resources[3];
  1011. struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  1012. struct platform_device *musb;
  1013. struct tusb6010_glue *glue;
  1014. struct platform_device_info pinfo;
  1015. int ret;
  1016. glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
  1017. if (!glue)
  1018. return -ENOMEM;
  1019. glue->dev = &pdev->dev;
  1020. pdata->platform_ops = &tusb_ops;
  1021. usb_phy_generic_register();
  1022. platform_set_drvdata(pdev, glue);
  1023. memset(musb_resources, 0x00, sizeof(*musb_resources) *
  1024. ARRAY_SIZE(musb_resources));
  1025. musb_resources[0].name = pdev->resource[0].name;
  1026. musb_resources[0].start = pdev->resource[0].start;
  1027. musb_resources[0].end = pdev->resource[0].end;
  1028. musb_resources[0].flags = pdev->resource[0].flags;
  1029. musb_resources[1].name = pdev->resource[1].name;
  1030. musb_resources[1].start = pdev->resource[1].start;
  1031. musb_resources[1].end = pdev->resource[1].end;
  1032. musb_resources[1].flags = pdev->resource[1].flags;
  1033. musb_resources[2].name = pdev->resource[2].name;
  1034. musb_resources[2].start = pdev->resource[2].start;
  1035. musb_resources[2].end = pdev->resource[2].end;
  1036. musb_resources[2].flags = pdev->resource[2].flags;
  1037. pinfo = tusb_dev_info;
  1038. pinfo.parent = &pdev->dev;
  1039. pinfo.res = musb_resources;
  1040. pinfo.num_res = ARRAY_SIZE(musb_resources);
  1041. pinfo.data = pdata;
  1042. pinfo.size_data = sizeof(*pdata);
  1043. glue->musb = musb = platform_device_register_full(&pinfo);
  1044. if (IS_ERR(musb)) {
  1045. ret = PTR_ERR(musb);
  1046. dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
  1047. return ret;
  1048. }
  1049. return 0;
  1050. }
  1051. static int tusb_remove(struct platform_device *pdev)
  1052. {
  1053. struct tusb6010_glue *glue = platform_get_drvdata(pdev);
  1054. platform_device_unregister(glue->musb);
  1055. usb_phy_generic_unregister(glue->phy);
  1056. return 0;
  1057. }
  1058. static struct platform_driver tusb_driver = {
  1059. .probe = tusb_probe,
  1060. .remove = tusb_remove,
  1061. .driver = {
  1062. .name = "musb-tusb",
  1063. },
  1064. };
  1065. MODULE_DESCRIPTION("TUSB6010 MUSB Glue Layer");
  1066. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  1067. MODULE_LICENSE("GPL v2");
  1068. module_platform_driver(tusb_driver);