musb_gadget_ep0.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MUSB OTG peripheral driver ep0 handling
  4. *
  5. * Copyright 2005 Mentor Graphics Corporation
  6. * Copyright (C) 2005-2006 by Texas Instruments
  7. * Copyright (C) 2006-2007 Nokia Corporation
  8. * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/list.h>
  12. #include <linux/timer.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/device.h>
  15. #include <linux/interrupt.h>
  16. #include "musb_core.h"
  17. /* ep0 is always musb->endpoints[0].ep_in */
  18. #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
  19. /*
  20. * locking note: we use only the controller lock, for simpler correctness.
  21. * It's always held with IRQs blocked.
  22. *
  23. * It protects the ep0 request queue as well as ep0_state, not just the
  24. * controller and indexed registers. And that lock stays held unless it
  25. * needs to be dropped to allow reentering this driver ... like upcalls to
  26. * the gadget driver, or adjusting endpoint halt status.
  27. */
  28. static char *decode_ep0stage(u8 stage)
  29. {
  30. switch (stage) {
  31. case MUSB_EP0_STAGE_IDLE: return "idle";
  32. case MUSB_EP0_STAGE_SETUP: return "setup";
  33. case MUSB_EP0_STAGE_TX: return "in";
  34. case MUSB_EP0_STAGE_RX: return "out";
  35. case MUSB_EP0_STAGE_ACKWAIT: return "wait";
  36. case MUSB_EP0_STAGE_STATUSIN: return "in/status";
  37. case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
  38. default: return "?";
  39. }
  40. }
  41. /* handle a standard GET_STATUS request
  42. * Context: caller holds controller lock
  43. */
  44. static int service_tx_status_request(
  45. struct musb *musb,
  46. const struct usb_ctrlrequest *ctrlrequest)
  47. {
  48. void __iomem *mbase = musb->mregs;
  49. int handled = 1;
  50. u8 result[2], epnum = 0;
  51. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  52. result[1] = 0;
  53. switch (recip) {
  54. case USB_RECIP_DEVICE:
  55. result[0] = musb->g.is_selfpowered << USB_DEVICE_SELF_POWERED;
  56. result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  57. if (musb->g.is_otg) {
  58. result[0] |= musb->g.b_hnp_enable
  59. << USB_DEVICE_B_HNP_ENABLE;
  60. result[0] |= musb->g.a_alt_hnp_support
  61. << USB_DEVICE_A_ALT_HNP_SUPPORT;
  62. result[0] |= musb->g.a_hnp_support
  63. << USB_DEVICE_A_HNP_SUPPORT;
  64. }
  65. break;
  66. case USB_RECIP_INTERFACE:
  67. result[0] = 0;
  68. break;
  69. case USB_RECIP_ENDPOINT: {
  70. int is_in;
  71. struct musb_ep *ep;
  72. u16 tmp;
  73. void __iomem *regs;
  74. epnum = (u8) ctrlrequest->wIndex;
  75. if (!epnum) {
  76. result[0] = 0;
  77. break;
  78. }
  79. is_in = epnum & USB_DIR_IN;
  80. epnum &= 0x0f;
  81. if (epnum >= MUSB_C_NUM_EPS) {
  82. handled = -EINVAL;
  83. break;
  84. }
  85. if (is_in)
  86. ep = &musb->endpoints[epnum].ep_in;
  87. else
  88. ep = &musb->endpoints[epnum].ep_out;
  89. regs = musb->endpoints[epnum].regs;
  90. if (!ep->desc) {
  91. handled = -EINVAL;
  92. break;
  93. }
  94. musb_ep_select(mbase, epnum);
  95. if (is_in)
  96. tmp = musb_readw(regs, MUSB_TXCSR)
  97. & MUSB_TXCSR_P_SENDSTALL;
  98. else
  99. tmp = musb_readw(regs, MUSB_RXCSR)
  100. & MUSB_RXCSR_P_SENDSTALL;
  101. musb_ep_select(mbase, 0);
  102. result[0] = tmp ? 1 : 0;
  103. } break;
  104. default:
  105. /* class, vendor, etc ... delegate */
  106. handled = 0;
  107. break;
  108. }
  109. /* fill up the fifo; caller updates csr0 */
  110. if (handled > 0) {
  111. u16 len = le16_to_cpu(ctrlrequest->wLength);
  112. if (len > 2)
  113. len = 2;
  114. musb_write_fifo(&musb->endpoints[0], len, result);
  115. }
  116. return handled;
  117. }
  118. /*
  119. * handle a control-IN request, the end0 buffer contains the current request
  120. * that is supposed to be a standard control request. Assumes the fifo to
  121. * be at least 2 bytes long.
  122. *
  123. * @return 0 if the request was NOT HANDLED,
  124. * < 0 when error
  125. * > 0 when the request is processed
  126. *
  127. * Context: caller holds controller lock
  128. */
  129. static int
  130. service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  131. {
  132. int handled = 0; /* not handled */
  133. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  134. == USB_TYPE_STANDARD) {
  135. switch (ctrlrequest->bRequest) {
  136. case USB_REQ_GET_STATUS:
  137. handled = service_tx_status_request(musb,
  138. ctrlrequest);
  139. break;
  140. /* case USB_REQ_SYNC_FRAME: */
  141. default:
  142. break;
  143. }
  144. }
  145. return handled;
  146. }
  147. /*
  148. * Context: caller holds controller lock
  149. */
  150. static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
  151. {
  152. musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
  153. }
  154. /*
  155. * Tries to start B-device HNP negotiation if enabled via sysfs
  156. */
  157. static inline void musb_try_b_hnp_enable(struct musb *musb)
  158. {
  159. void __iomem *mbase = musb->mregs;
  160. u8 devctl;
  161. musb_dbg(musb, "HNP: Setting HR");
  162. devctl = musb_readb(mbase, MUSB_DEVCTL);
  163. musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
  164. }
  165. /*
  166. * Handle all control requests with no DATA stage, including standard
  167. * requests such as:
  168. * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
  169. * always delegated to the gadget driver
  170. * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
  171. * always handled here, except for class/vendor/... features
  172. *
  173. * Context: caller holds controller lock
  174. */
  175. static int
  176. service_zero_data_request(struct musb *musb,
  177. struct usb_ctrlrequest *ctrlrequest)
  178. __releases(musb->lock)
  179. __acquires(musb->lock)
  180. {
  181. int handled = -EINVAL;
  182. void __iomem *mbase = musb->mregs;
  183. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  184. /* the gadget driver handles everything except what we MUST handle */
  185. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  186. == USB_TYPE_STANDARD) {
  187. switch (ctrlrequest->bRequest) {
  188. case USB_REQ_SET_ADDRESS:
  189. /* change it after the status stage */
  190. musb->set_address = true;
  191. musb->address = (u8) (ctrlrequest->wValue & 0x7f);
  192. handled = 1;
  193. break;
  194. case USB_REQ_CLEAR_FEATURE:
  195. switch (recip) {
  196. case USB_RECIP_DEVICE:
  197. if (ctrlrequest->wValue
  198. != USB_DEVICE_REMOTE_WAKEUP)
  199. break;
  200. musb->may_wakeup = 0;
  201. handled = 1;
  202. break;
  203. case USB_RECIP_INTERFACE:
  204. break;
  205. case USB_RECIP_ENDPOINT:{
  206. const u8 epnum =
  207. ctrlrequest->wIndex & 0x0f;
  208. struct musb_ep *musb_ep;
  209. struct musb_hw_ep *ep;
  210. struct musb_request *request;
  211. void __iomem *regs;
  212. int is_in;
  213. u16 csr;
  214. if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
  215. ctrlrequest->wValue != USB_ENDPOINT_HALT)
  216. break;
  217. ep = musb->endpoints + epnum;
  218. regs = ep->regs;
  219. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  220. if (is_in)
  221. musb_ep = &ep->ep_in;
  222. else
  223. musb_ep = &ep->ep_out;
  224. if (!musb_ep->desc)
  225. break;
  226. handled = 1;
  227. /* Ignore request if endpoint is wedged */
  228. if (musb_ep->wedged)
  229. break;
  230. musb_ep_select(mbase, epnum);
  231. if (is_in) {
  232. csr = musb_readw(regs, MUSB_TXCSR);
  233. csr |= MUSB_TXCSR_CLRDATATOG |
  234. MUSB_TXCSR_P_WZC_BITS;
  235. csr &= ~(MUSB_TXCSR_P_SENDSTALL |
  236. MUSB_TXCSR_P_SENTSTALL |
  237. MUSB_TXCSR_TXPKTRDY);
  238. musb_writew(regs, MUSB_TXCSR, csr);
  239. } else {
  240. csr = musb_readw(regs, MUSB_RXCSR);
  241. csr |= MUSB_RXCSR_CLRDATATOG |
  242. MUSB_RXCSR_P_WZC_BITS;
  243. csr &= ~(MUSB_RXCSR_P_SENDSTALL |
  244. MUSB_RXCSR_P_SENTSTALL);
  245. musb_writew(regs, MUSB_RXCSR, csr);
  246. }
  247. /* Maybe start the first request in the queue */
  248. request = next_request(musb_ep);
  249. if (!musb_ep->busy && request) {
  250. musb_dbg(musb, "restarting the request");
  251. musb_ep_restart(musb, request);
  252. }
  253. /* select ep0 again */
  254. musb_ep_select(mbase, 0);
  255. } break;
  256. default:
  257. /* class, vendor, etc ... delegate */
  258. handled = 0;
  259. break;
  260. }
  261. break;
  262. case USB_REQ_SET_FEATURE:
  263. switch (recip) {
  264. case USB_RECIP_DEVICE:
  265. handled = 1;
  266. switch (ctrlrequest->wValue) {
  267. case USB_DEVICE_REMOTE_WAKEUP:
  268. musb->may_wakeup = 1;
  269. break;
  270. case USB_DEVICE_TEST_MODE:
  271. if (musb->g.speed != USB_SPEED_HIGH)
  272. goto stall;
  273. if (ctrlrequest->wIndex & 0xff)
  274. goto stall;
  275. switch (ctrlrequest->wIndex >> 8) {
  276. case 1:
  277. pr_debug("TEST_J\n");
  278. /* TEST_J */
  279. musb->test_mode_nr =
  280. MUSB_TEST_J;
  281. break;
  282. case 2:
  283. /* TEST_K */
  284. pr_debug("TEST_K\n");
  285. musb->test_mode_nr =
  286. MUSB_TEST_K;
  287. break;
  288. case 3:
  289. /* TEST_SE0_NAK */
  290. pr_debug("TEST_SE0_NAK\n");
  291. musb->test_mode_nr =
  292. MUSB_TEST_SE0_NAK;
  293. break;
  294. case 4:
  295. /* TEST_PACKET */
  296. pr_debug("TEST_PACKET\n");
  297. musb->test_mode_nr =
  298. MUSB_TEST_PACKET;
  299. break;
  300. case 0xc0:
  301. /* TEST_FORCE_HS */
  302. pr_debug("TEST_FORCE_HS\n");
  303. musb->test_mode_nr =
  304. MUSB_TEST_FORCE_HS;
  305. break;
  306. case 0xc1:
  307. /* TEST_FORCE_FS */
  308. pr_debug("TEST_FORCE_FS\n");
  309. musb->test_mode_nr =
  310. MUSB_TEST_FORCE_FS;
  311. break;
  312. case 0xc2:
  313. /* TEST_FIFO_ACCESS */
  314. pr_debug("TEST_FIFO_ACCESS\n");
  315. musb->test_mode_nr =
  316. MUSB_TEST_FIFO_ACCESS;
  317. break;
  318. case 0xc3:
  319. /* TEST_FORCE_HOST */
  320. pr_debug("TEST_FORCE_HOST\n");
  321. musb->test_mode_nr =
  322. MUSB_TEST_FORCE_HOST;
  323. break;
  324. default:
  325. goto stall;
  326. }
  327. /* enter test mode after irq */
  328. if (handled > 0)
  329. musb->test_mode = true;
  330. break;
  331. case USB_DEVICE_B_HNP_ENABLE:
  332. if (!musb->g.is_otg)
  333. goto stall;
  334. musb->g.b_hnp_enable = 1;
  335. musb_try_b_hnp_enable(musb);
  336. break;
  337. case USB_DEVICE_A_HNP_SUPPORT:
  338. if (!musb->g.is_otg)
  339. goto stall;
  340. musb->g.a_hnp_support = 1;
  341. break;
  342. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  343. if (!musb->g.is_otg)
  344. goto stall;
  345. musb->g.a_alt_hnp_support = 1;
  346. break;
  347. case USB_DEVICE_DEBUG_MODE:
  348. handled = 0;
  349. break;
  350. stall:
  351. default:
  352. handled = -EINVAL;
  353. break;
  354. }
  355. break;
  356. case USB_RECIP_INTERFACE:
  357. break;
  358. case USB_RECIP_ENDPOINT:{
  359. const u8 epnum =
  360. ctrlrequest->wIndex & 0x0f;
  361. struct musb_ep *musb_ep;
  362. struct musb_hw_ep *ep;
  363. void __iomem *regs;
  364. int is_in;
  365. u16 csr;
  366. if (epnum == 0 || epnum >= MUSB_C_NUM_EPS ||
  367. ctrlrequest->wValue != USB_ENDPOINT_HALT)
  368. break;
  369. ep = musb->endpoints + epnum;
  370. regs = ep->regs;
  371. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  372. if (is_in)
  373. musb_ep = &ep->ep_in;
  374. else
  375. musb_ep = &ep->ep_out;
  376. if (!musb_ep->desc)
  377. break;
  378. musb_ep_select(mbase, epnum);
  379. if (is_in) {
  380. csr = musb_readw(regs, MUSB_TXCSR);
  381. if (csr & MUSB_TXCSR_FIFONOTEMPTY)
  382. csr |= MUSB_TXCSR_FLUSHFIFO;
  383. csr |= MUSB_TXCSR_P_SENDSTALL
  384. | MUSB_TXCSR_CLRDATATOG
  385. | MUSB_TXCSR_P_WZC_BITS;
  386. musb_writew(regs, MUSB_TXCSR, csr);
  387. } else {
  388. csr = musb_readw(regs, MUSB_RXCSR);
  389. csr |= MUSB_RXCSR_P_SENDSTALL
  390. | MUSB_RXCSR_FLUSHFIFO
  391. | MUSB_RXCSR_CLRDATATOG
  392. | MUSB_RXCSR_P_WZC_BITS;
  393. musb_writew(regs, MUSB_RXCSR, csr);
  394. }
  395. /* select ep0 again */
  396. musb_ep_select(mbase, 0);
  397. handled = 1;
  398. } break;
  399. default:
  400. /* class, vendor, etc ... delegate */
  401. handled = 0;
  402. break;
  403. }
  404. break;
  405. default:
  406. /* delegate SET_CONFIGURATION, etc */
  407. handled = 0;
  408. }
  409. } else
  410. handled = 0;
  411. return handled;
  412. }
  413. /* we have an ep0out data packet
  414. * Context: caller holds controller lock
  415. */
  416. static void ep0_rxstate(struct musb *musb)
  417. {
  418. void __iomem *regs = musb->control_ep->regs;
  419. struct musb_request *request;
  420. struct usb_request *req;
  421. u16 count, csr;
  422. request = next_ep0_request(musb);
  423. req = &request->request;
  424. /* read packet and ack; or stall because of gadget driver bug:
  425. * should have provided the rx buffer before setup() returned.
  426. */
  427. if (req) {
  428. void *buf = req->buf + req->actual;
  429. unsigned len = req->length - req->actual;
  430. /* read the buffer */
  431. count = musb_readb(regs, MUSB_COUNT0);
  432. if (count > len) {
  433. req->status = -EOVERFLOW;
  434. count = len;
  435. }
  436. if (count > 0) {
  437. musb_read_fifo(&musb->endpoints[0], count, buf);
  438. req->actual += count;
  439. }
  440. csr = MUSB_CSR0_P_SVDRXPKTRDY;
  441. if (count < 64 || req->actual == req->length) {
  442. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  443. csr |= MUSB_CSR0_P_DATAEND;
  444. } else
  445. req = NULL;
  446. } else
  447. csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
  448. /* Completion handler may choose to stall, e.g. because the
  449. * message just received holds invalid data.
  450. */
  451. if (req) {
  452. musb->ackpend = csr;
  453. musb_g_ep0_giveback(musb, req);
  454. if (!musb->ackpend)
  455. return;
  456. musb->ackpend = 0;
  457. }
  458. musb_ep_select(musb->mregs, 0);
  459. musb_writew(regs, MUSB_CSR0, csr);
  460. }
  461. /*
  462. * transmitting to the host (IN), this code might be called from IRQ
  463. * and from kernel thread.
  464. *
  465. * Context: caller holds controller lock
  466. */
  467. static void ep0_txstate(struct musb *musb)
  468. {
  469. void __iomem *regs = musb->control_ep->regs;
  470. struct musb_request *req = next_ep0_request(musb);
  471. struct usb_request *request;
  472. u16 csr = MUSB_CSR0_TXPKTRDY;
  473. u8 *fifo_src;
  474. u8 fifo_count;
  475. if (!req) {
  476. /* WARN_ON(1); */
  477. musb_dbg(musb, "odd; csr0 %04x", musb_readw(regs, MUSB_CSR0));
  478. return;
  479. }
  480. request = &req->request;
  481. /* load the data */
  482. fifo_src = (u8 *) request->buf + request->actual;
  483. fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
  484. request->length - request->actual);
  485. musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
  486. request->actual += fifo_count;
  487. /* update the flags */
  488. if (fifo_count < MUSB_MAX_END0_PACKET
  489. || (request->actual == request->length
  490. && !request->zero)) {
  491. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  492. csr |= MUSB_CSR0_P_DATAEND;
  493. } else
  494. request = NULL;
  495. /* report completions as soon as the fifo's loaded; there's no
  496. * win in waiting till this last packet gets acked. (other than
  497. * very precise fault reporting, needed by USB TMC; possible with
  498. * this hardware, but not usable from portable gadget drivers.)
  499. */
  500. if (request) {
  501. musb->ackpend = csr;
  502. musb_g_ep0_giveback(musb, request);
  503. if (!musb->ackpend)
  504. return;
  505. musb->ackpend = 0;
  506. }
  507. /* send it out, triggering a "txpktrdy cleared" irq */
  508. musb_ep_select(musb->mregs, 0);
  509. musb_writew(regs, MUSB_CSR0, csr);
  510. }
  511. /*
  512. * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
  513. * Fields are left in USB byte-order.
  514. *
  515. * Context: caller holds controller lock.
  516. */
  517. static void
  518. musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
  519. {
  520. struct musb_request *r;
  521. void __iomem *regs = musb->control_ep->regs;
  522. musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
  523. /* NOTE: earlier 2.6 versions changed setup packets to host
  524. * order, but now USB packets always stay in USB byte order.
  525. */
  526. musb_dbg(musb, "SETUP req%02x.%02x v%04x i%04x l%d",
  527. req->bRequestType,
  528. req->bRequest,
  529. le16_to_cpu(req->wValue),
  530. le16_to_cpu(req->wIndex),
  531. le16_to_cpu(req->wLength));
  532. /* clean up any leftover transfers */
  533. r = next_ep0_request(musb);
  534. if (r)
  535. musb_g_ep0_giveback(musb, &r->request);
  536. /* For zero-data requests we want to delay the STATUS stage to
  537. * avoid SETUPEND errors. If we read data (OUT), delay accepting
  538. * packets until there's a buffer to store them in.
  539. *
  540. * If we write data, the controller acts happier if we enable
  541. * the TX FIFO right away, and give the controller a moment
  542. * to switch modes...
  543. */
  544. musb->set_address = false;
  545. musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
  546. if (req->wLength == 0) {
  547. if (req->bRequestType & USB_DIR_IN)
  548. musb->ackpend |= MUSB_CSR0_TXPKTRDY;
  549. musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
  550. } else if (req->bRequestType & USB_DIR_IN) {
  551. musb->ep0_state = MUSB_EP0_STAGE_TX;
  552. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
  553. while ((musb_readw(regs, MUSB_CSR0)
  554. & MUSB_CSR0_RXPKTRDY) != 0)
  555. cpu_relax();
  556. musb->ackpend = 0;
  557. } else
  558. musb->ep0_state = MUSB_EP0_STAGE_RX;
  559. }
  560. static int
  561. forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  562. __releases(musb->lock)
  563. __acquires(musb->lock)
  564. {
  565. int retval;
  566. if (!musb->gadget_driver)
  567. return -EOPNOTSUPP;
  568. spin_unlock(&musb->lock);
  569. retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
  570. spin_lock(&musb->lock);
  571. return retval;
  572. }
  573. /*
  574. * Handle peripheral ep0 interrupt
  575. *
  576. * Context: irq handler; we won't re-enter the driver that way.
  577. */
  578. irqreturn_t musb_g_ep0_irq(struct musb *musb)
  579. {
  580. u16 csr;
  581. u16 len;
  582. void __iomem *mbase = musb->mregs;
  583. void __iomem *regs = musb->endpoints[0].regs;
  584. irqreturn_t retval = IRQ_NONE;
  585. musb_ep_select(mbase, 0); /* select ep0 */
  586. csr = musb_readw(regs, MUSB_CSR0);
  587. len = musb_readb(regs, MUSB_COUNT0);
  588. musb_dbg(musb, "csr %04x, count %d, ep0stage %s",
  589. csr, len, decode_ep0stage(musb->ep0_state));
  590. if (csr & MUSB_CSR0_P_DATAEND) {
  591. /*
  592. * If DATAEND is set we should not call the callback,
  593. * hence the status stage is not complete.
  594. */
  595. return IRQ_HANDLED;
  596. }
  597. /* I sent a stall.. need to acknowledge it now.. */
  598. if (csr & MUSB_CSR0_P_SENTSTALL) {
  599. musb_writew(regs, MUSB_CSR0,
  600. csr & ~MUSB_CSR0_P_SENTSTALL);
  601. retval = IRQ_HANDLED;
  602. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  603. csr = musb_readw(regs, MUSB_CSR0);
  604. }
  605. /* request ended "early" */
  606. if (csr & MUSB_CSR0_P_SETUPEND) {
  607. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
  608. retval = IRQ_HANDLED;
  609. /* Transition into the early status phase */
  610. switch (musb->ep0_state) {
  611. case MUSB_EP0_STAGE_TX:
  612. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  613. break;
  614. case MUSB_EP0_STAGE_RX:
  615. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  616. break;
  617. default:
  618. ERR("SetupEnd came in a wrong ep0stage %s\n",
  619. decode_ep0stage(musb->ep0_state));
  620. }
  621. csr = musb_readw(regs, MUSB_CSR0);
  622. /* NOTE: request may need completion */
  623. }
  624. /* docs from Mentor only describe tx, rx, and idle/setup states.
  625. * we need to handle nuances around status stages, and also the
  626. * case where status and setup stages come back-to-back ...
  627. */
  628. switch (musb->ep0_state) {
  629. case MUSB_EP0_STAGE_TX:
  630. /* irq on clearing txpktrdy */
  631. if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
  632. ep0_txstate(musb);
  633. retval = IRQ_HANDLED;
  634. }
  635. break;
  636. case MUSB_EP0_STAGE_RX:
  637. /* irq on set rxpktrdy */
  638. if (csr & MUSB_CSR0_RXPKTRDY) {
  639. ep0_rxstate(musb);
  640. retval = IRQ_HANDLED;
  641. }
  642. break;
  643. case MUSB_EP0_STAGE_STATUSIN:
  644. /* end of sequence #2 (OUT/RX state) or #3 (no data) */
  645. /* update address (if needed) only @ the end of the
  646. * status phase per usb spec, which also guarantees
  647. * we get 10 msec to receive this irq... until this
  648. * is done we won't see the next packet.
  649. */
  650. if (musb->set_address) {
  651. musb->set_address = false;
  652. musb_writeb(mbase, MUSB_FADDR, musb->address);
  653. }
  654. /* enter test mode if needed (exit by reset) */
  655. else if (musb->test_mode) {
  656. musb_dbg(musb, "entering TESTMODE");
  657. if (MUSB_TEST_PACKET == musb->test_mode_nr)
  658. musb_load_testpacket(musb);
  659. musb_writeb(mbase, MUSB_TESTMODE,
  660. musb->test_mode_nr);
  661. }
  662. /* FALLTHROUGH */
  663. case MUSB_EP0_STAGE_STATUSOUT:
  664. /* end of sequence #1: write to host (TX state) */
  665. {
  666. struct musb_request *req;
  667. req = next_ep0_request(musb);
  668. if (req)
  669. musb_g_ep0_giveback(musb, &req->request);
  670. }
  671. /*
  672. * In case when several interrupts can get coalesced,
  673. * check to see if we've already received a SETUP packet...
  674. */
  675. if (csr & MUSB_CSR0_RXPKTRDY)
  676. goto setup;
  677. retval = IRQ_HANDLED;
  678. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  679. break;
  680. case MUSB_EP0_STAGE_IDLE:
  681. /*
  682. * This state is typically (but not always) indiscernible
  683. * from the status states since the corresponding interrupts
  684. * tend to happen within too little period of time (with only
  685. * a zero-length packet in between) and so get coalesced...
  686. */
  687. retval = IRQ_HANDLED;
  688. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  689. /* FALLTHROUGH */
  690. case MUSB_EP0_STAGE_SETUP:
  691. setup:
  692. if (csr & MUSB_CSR0_RXPKTRDY) {
  693. struct usb_ctrlrequest setup;
  694. int handled = 0;
  695. if (len != 8) {
  696. ERR("SETUP packet len %d != 8 ?\n", len);
  697. break;
  698. }
  699. musb_read_setup(musb, &setup);
  700. retval = IRQ_HANDLED;
  701. /* sometimes the RESET won't be reported */
  702. if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
  703. u8 power;
  704. printk(KERN_NOTICE "%s: peripheral reset "
  705. "irq lost!\n",
  706. musb_driver_name);
  707. power = musb_readb(mbase, MUSB_POWER);
  708. musb->g.speed = (power & MUSB_POWER_HSMODE)
  709. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  710. }
  711. switch (musb->ep0_state) {
  712. /* sequence #3 (no data stage), includes requests
  713. * we can't forward (notably SET_ADDRESS and the
  714. * device/endpoint feature set/clear operations)
  715. * plus SET_CONFIGURATION and others we must
  716. */
  717. case MUSB_EP0_STAGE_ACKWAIT:
  718. handled = service_zero_data_request(
  719. musb, &setup);
  720. /*
  721. * We're expecting no data in any case, so
  722. * always set the DATAEND bit -- doing this
  723. * here helps avoid SetupEnd interrupt coming
  724. * in the idle stage when we're stalling...
  725. */
  726. musb->ackpend |= MUSB_CSR0_P_DATAEND;
  727. /* status stage might be immediate */
  728. if (handled > 0)
  729. musb->ep0_state =
  730. MUSB_EP0_STAGE_STATUSIN;
  731. break;
  732. /* sequence #1 (IN to host), includes GET_STATUS
  733. * requests that we can't forward, GET_DESCRIPTOR
  734. * and others that we must
  735. */
  736. case MUSB_EP0_STAGE_TX:
  737. handled = service_in_request(musb, &setup);
  738. if (handled > 0) {
  739. musb->ackpend = MUSB_CSR0_TXPKTRDY
  740. | MUSB_CSR0_P_DATAEND;
  741. musb->ep0_state =
  742. MUSB_EP0_STAGE_STATUSOUT;
  743. }
  744. break;
  745. /* sequence #2 (OUT from host), always forward */
  746. default: /* MUSB_EP0_STAGE_RX */
  747. break;
  748. }
  749. musb_dbg(musb, "handled %d, csr %04x, ep0stage %s",
  750. handled, csr,
  751. decode_ep0stage(musb->ep0_state));
  752. /* unless we need to delegate this to the gadget
  753. * driver, we know how to wrap this up: csr0 has
  754. * not yet been written.
  755. */
  756. if (handled < 0)
  757. goto stall;
  758. else if (handled > 0)
  759. goto finish;
  760. handled = forward_to_driver(musb, &setup);
  761. if (handled < 0) {
  762. musb_ep_select(mbase, 0);
  763. stall:
  764. musb_dbg(musb, "stall (%d)", handled);
  765. musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
  766. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  767. finish:
  768. musb_writew(regs, MUSB_CSR0,
  769. musb->ackpend);
  770. musb->ackpend = 0;
  771. }
  772. }
  773. break;
  774. case MUSB_EP0_STAGE_ACKWAIT:
  775. /* This should not happen. But happens with tusb6010 with
  776. * g_file_storage and high speed. Do nothing.
  777. */
  778. retval = IRQ_HANDLED;
  779. break;
  780. default:
  781. /* "can't happen" */
  782. WARN_ON(1);
  783. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
  784. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  785. break;
  786. }
  787. return retval;
  788. }
  789. static int
  790. musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
  791. {
  792. /* always enabled */
  793. return -EINVAL;
  794. }
  795. static int musb_g_ep0_disable(struct usb_ep *e)
  796. {
  797. /* always enabled */
  798. return -EINVAL;
  799. }
  800. static int
  801. musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
  802. {
  803. struct musb_ep *ep;
  804. struct musb_request *req;
  805. struct musb *musb;
  806. int status;
  807. unsigned long lockflags;
  808. void __iomem *regs;
  809. if (!e || !r)
  810. return -EINVAL;
  811. ep = to_musb_ep(e);
  812. musb = ep->musb;
  813. regs = musb->control_ep->regs;
  814. req = to_musb_request(r);
  815. req->musb = musb;
  816. req->request.actual = 0;
  817. req->request.status = -EINPROGRESS;
  818. req->tx = ep->is_in;
  819. spin_lock_irqsave(&musb->lock, lockflags);
  820. if (!list_empty(&ep->req_list)) {
  821. status = -EBUSY;
  822. goto cleanup;
  823. }
  824. switch (musb->ep0_state) {
  825. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  826. case MUSB_EP0_STAGE_TX: /* control-IN data */
  827. case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
  828. status = 0;
  829. break;
  830. default:
  831. musb_dbg(musb, "ep0 request queued in state %d",
  832. musb->ep0_state);
  833. status = -EINVAL;
  834. goto cleanup;
  835. }
  836. /* add request to the list */
  837. list_add_tail(&req->list, &ep->req_list);
  838. musb_dbg(musb, "queue to %s (%s), length=%d",
  839. ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
  840. req->request.length);
  841. musb_ep_select(musb->mregs, 0);
  842. /* sequence #1, IN ... start writing the data */
  843. if (musb->ep0_state == MUSB_EP0_STAGE_TX)
  844. ep0_txstate(musb);
  845. /* sequence #3, no-data ... issue IN status */
  846. else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
  847. if (req->request.length)
  848. status = -EINVAL;
  849. else {
  850. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  851. musb_writew(regs, MUSB_CSR0,
  852. musb->ackpend | MUSB_CSR0_P_DATAEND);
  853. musb->ackpend = 0;
  854. musb_g_ep0_giveback(ep->musb, r);
  855. }
  856. /* else for sequence #2 (OUT), caller provides a buffer
  857. * before the next packet arrives. deferred responses
  858. * (after SETUP is acked) are racey.
  859. */
  860. } else if (musb->ackpend) {
  861. musb_writew(regs, MUSB_CSR0, musb->ackpend);
  862. musb->ackpend = 0;
  863. }
  864. cleanup:
  865. spin_unlock_irqrestore(&musb->lock, lockflags);
  866. return status;
  867. }
  868. static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
  869. {
  870. /* we just won't support this */
  871. return -EINVAL;
  872. }
  873. static int musb_g_ep0_halt(struct usb_ep *e, int value)
  874. {
  875. struct musb_ep *ep;
  876. struct musb *musb;
  877. void __iomem *base, *regs;
  878. unsigned long flags;
  879. int status;
  880. u16 csr;
  881. if (!e || !value)
  882. return -EINVAL;
  883. ep = to_musb_ep(e);
  884. musb = ep->musb;
  885. base = musb->mregs;
  886. regs = musb->control_ep->regs;
  887. status = 0;
  888. spin_lock_irqsave(&musb->lock, flags);
  889. if (!list_empty(&ep->req_list)) {
  890. status = -EBUSY;
  891. goto cleanup;
  892. }
  893. musb_ep_select(base, 0);
  894. csr = musb->ackpend;
  895. switch (musb->ep0_state) {
  896. /* Stalls are usually issued after parsing SETUP packet, either
  897. * directly in irq context from setup() or else later.
  898. */
  899. case MUSB_EP0_STAGE_TX: /* control-IN data */
  900. case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
  901. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  902. csr = musb_readw(regs, MUSB_CSR0);
  903. /* FALLTHROUGH */
  904. /* It's also OK to issue stalls during callbacks when a non-empty
  905. * DATA stage buffer has been read (or even written).
  906. */
  907. case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
  908. case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
  909. csr |= MUSB_CSR0_P_SENDSTALL;
  910. musb_writew(regs, MUSB_CSR0, csr);
  911. musb->ep0_state = MUSB_EP0_STAGE_IDLE;
  912. musb->ackpend = 0;
  913. break;
  914. default:
  915. musb_dbg(musb, "ep0 can't halt in state %d", musb->ep0_state);
  916. status = -EINVAL;
  917. }
  918. cleanup:
  919. spin_unlock_irqrestore(&musb->lock, flags);
  920. return status;
  921. }
  922. const struct usb_ep_ops musb_g_ep0_ops = {
  923. .enable = musb_g_ep0_enable,
  924. .disable = musb_g_ep0_disable,
  925. .alloc_request = musb_alloc_request,
  926. .free_request = musb_free_request,
  927. .queue = musb_g_ep0_queue,
  928. .dequeue = musb_g_ep0_dequeue,
  929. .set_halt = musb_g_ep0_halt,
  930. };